| commit | 54042f4ba49b388064806cd60a497bf3d24a4e3a | |
| author | Mark Abraham <mark.j.abraham@gmail.com> | |
| Thu, 13 Jul 2017 11:23:52 +0000 (13 11:23 +0000) | ||
| committer | Mark Abraham <mark.j.abraham@gmail.com> | |
| Mon, 21 Aug 2017 12:45:11 +0000 (21 14:45 +0200) | ||
| tree | 8270bbe4266289da75820e7101bcd3bad6e02065 | treesnapshot (tar.gz zip) |
| parent | c33d8d64fa8c0fa27f6e429c24bf295c5eff5c61 | commitdiff |
Fix compilation issues with ARM SIMD
ARM_NEON has never supported double precision SIMD, so disabled it
with GROMACS double-precision build.
The maskzR* functions used the wrong argument order in the debug-mode
pre-masking (and sometimes in a typo-ed syntax).
In the shift operators, the clang-based compilers (including the
armclang v6 compiler series) seem to check that the required immediate
integer argument is given before inlining the call to the operator
function. The inlining seems to permit gcc to recognize that the
callers always use an immediate. In theory, the new code might
generate code that runs a trifle slower, but we don't use it at the
moment and the cost might be negligible if other effects dominate
performance.
Change-Id: I61dd4d906f7d5b77bc4e851cfaaaff059e5a67fe
ARM_NEON has never supported double precision SIMD, so disabled it
with GROMACS double-precision build.
The maskzR* functions used the wrong argument order in the debug-mode
pre-masking (and sometimes in a typo-ed syntax).
In the shift operators, the clang-based compilers (including the
armclang v6 compiler series) seem to check that the required immediate
integer argument is given before inlining the call to the operator
function. The inlining seems to permit gcc to recognize that the
callers always use an immediate. In theory, the new code might
generate code that runs a trifle slower, but we don't use it at the
moment and the cost might be negligible if other effects dominate
performance.
Change-Id: I61dd4d906f7d5b77bc4e851cfaaaff059e5a67fe