| commit | 97a58d885b01ecf432e0d96248556245a232597e | |
| author | Stefan Liebler <stli@linux.ibm.com> | |
| Wed, 18 Oct 2023 13:08:40 +0000 (18 15:08 +0200) | ||
| committer | Stefan Liebler <stli@linux.ibm.com> | |
| Thu, 19 Oct 2023 12:28:22 +0000 (19 14:28 +0200) | ||
| tree | 84eed7270c358bce0cfc0a89751fd1de0289f58c | treesnapshot (tar.gz zip) |
| parent | c06e10c8130358c409c1d2837f8171ef70169d03 | commitdiff |
s390: Fix undefined behaviour in feenableexcept, fedisableexcept [BZ #30960]
If feenableexcept or fedisableexcept gets excepts=FE_INVALID=0x80
as input, we have a signed left shift: 0x80 << 24 which is not
representable as int and thus is undefined behaviour according to
C standard.
This patch casts excepts as unsigned int before shifting, which is
defined.
For me, the observed undefined behaviour is that the shift is done
with "unsigned"-instructions, which is exactly what we want.
Furthermore, I don't get any exception-flags.
After the fix, the code is using the same instruction sequence as
before.
If feenableexcept or fedisableexcept gets excepts=FE_INVALID=0x80
as input, we have a signed left shift: 0x80 << 24 which is not
representable as int and thus is undefined behaviour according to
C standard.
This patch casts excepts as unsigned int before shifting, which is
defined.
For me, the observed undefined behaviour is that the shift is done
with "unsigned"-instructions, which is exactly what we want.
Furthermore, I don't get any exception-flags.
After the fix, the code is using the same instruction sequence as
before.
| sysdeps/s390/fpu/fedisblxcpt.c | diffblobblamehistory | |
| sysdeps/s390/fpu/feenablxcpt.c | diffblobblamehistory |