From e556195b9c8f7f7a9879a2f37fa75fc9c82f5117 Mon Sep 17 00:00:00 2001 From: bert Date: Sun, 21 Feb 2016 16:17:20 +0100 Subject: [PATCH] Added a description of djopt(vianudge) in the user docs. Signed-off-by: bert --- doc/Makefile.am | 8 ++++-- doc/vianudge.out.pcb | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ doc/vianudge.pcb | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++ src/djopt.c | 11 +++++++ 4 files changed, 177 insertions(+), 2 deletions(-) create mode 100644 doc/vianudge.out.pcb create mode 100644 doc/vianudge.pcb diff --git a/doc/Makefile.am b/doc/Makefile.am index 9fb2102244..a2bd29e543 100644 --- a/doc/Makefile.am +++ b/doc/Makefile.am @@ -111,7 +111,9 @@ pcb_files= \ orthopull.pcb \ orthopull.out.pcb \ unjaggy.pcb \ - unjaggy.out.pcb + unjaggy.out.pcb \ + vianudge.pcb \ + vianudge.out.pcb pcb_output_noinst= \ ${pcb_files:.pcb=.pdf} @@ -133,7 +135,9 @@ images= \ orthopull.eps \ orthopull.out.eps \ unjaggy.eps \ - unjaggy.out.eps + unjaggy.out.eps \ + vianudge.eps \ + vianudge.out.eps images_output_noinst= \ ${images:.eps=.pdf} diff --git a/doc/vianudge.out.pcb b/doc/vianudge.out.pcb new file mode 100644 index 0000000000..14ff8be532 --- /dev/null +++ b/doc/vianudge.out.pcb @@ -0,0 +1,79 @@ +# release: pcb-rnd 1.0.7 + +# To read pcb files, the pcb version (or the git source date) must be >= the file version +FileVersion[20070407] + +PCB["" 140000 67500] + +Grid[2500.0 0 0 1] +Cursor[17500 22500 0.000000] +PolyArea[3100.006200] +Thermal[0.500000] +DRC[1200 900 1000 700 1500 1000] +Flags("nameonpcb,clearnew,snappin") +Groups("1,3,4,c:2,5,6,s:7:8") +Styles["Signal,1000,7874,3150,2000:Power,2000,8661,3937,2000:Fat,8000,13780,4724,2500:Sig-tight,1000,6400,3150,1200"] + +Via[85000 27500 8661 4000 0 3937 "" ""] + +Element["" "Standard SMT resistor, capacitor etc" "R101" "1206" 57500 10000 -5650 4350 0 100 ""] +( + Pad[5905 -1181 5905 1181 5118 2000 5718 "1" "1" "square"] + Pad[-5905 -1181 -5905 1181 5118 2000 5718 "2" "2" "square"] + ElementLine [-2362 3740 2362 3740 800] + ElementLine [-2362 -3740 2362 -3740 800] + + ) + +Element["onsolder" "Standard SMT resistor, capacitor etc" "R102" "1206" 10000 10000 5650 4350 2 100 "auto"] +( + Pad[-5905 -1181 -5905 1181 5118 2000 5718 "1" "1" "onsolder,square"] + Pad[5905 -1181 5905 1181 5118 2000 5718 "2" "2" "onsolder,square"] + ElementLine [-2362 3740 2362 3740 800] + ElementLine [-2362 -3740 2362 -3740 800] + + ) +Layer(1 "component") +( + Line[63405 10000 85000 10000 1000 4000 "clearline"] + Line[85000 10000 85000 27500 1000 4000 "clearline"] +) +Layer(2 "solder") +( + Line[15905 10000 30000 10000 2000 4000 "clearline"] + Line[30000 10000 30000 27500 2000 4000 "clearline"] + Line[30000 27500 85000 27500 2000 4000 "clearline"] + Line[85000 27500 85000 27500 2000 4000 "clearline"] +) +Layer(3 "comp-GND") +( +) +Layer(4 "comp-power") +( +) +Layer(5 "sold-GND") +( +) +Layer(6 "sold-power") +( +) +Layer(7 "signal3") +( +) +Layer(8 "outline") +( +) +Layer(9 "silk") +( +) +Layer(10 "silk") +( +) +NetList() +( + Net("GND" "(unknown)") + ( + Connect("R101-1") + Connect("R102-2") + ) +) diff --git a/doc/vianudge.pcb b/doc/vianudge.pcb new file mode 100644 index 0000000000..141cef54cf --- /dev/null +++ b/doc/vianudge.pcb @@ -0,0 +1,81 @@ +# release: pcb-rnd 1.0.7 + +# To read pcb files, the pcb version (or the git source date) must be >= the file version +FileVersion[20070407] + +PCB["" 140000 67500] + +Grid[2500.0 0 0 1] +Cursor[17500 22500 0.000000] +PolyArea[3100.006200] +Thermal[0.500000] +DRC[1200 900 1000 700 1500 1000] +Flags("nameonpcb,clearnew,snappin") +Groups("1,3,4,c:2,5,6,s:7:8") +Styles["Signal,1000,7874,3150,2000:Power,2000,8661,3937,2000:Fat,8000,13780,4724,2500:Sig-tight,1000,6400,3150,1200"] + + +Attribute("PCB::grid::unit" "mm") +Via[85000 50000 8661 4000 0 3937 "" ""] + +Element["" "Standard SMT resistor, capacitor etc" "R101" "1206" 57500 10000 -5650 4350 0 100 ""] +( + Pad[5905 -1181 5905 1181 5118 2000 5718 "1" "1" "square"] + Pad[-5905 -1181 -5905 1181 5118 2000 5718 "2" "2" "square"] + ElementLine [-2362 3740 2362 3740 800] + ElementLine [-2362 -3740 2362 -3740 800] + + ) + +Element["onsolder" "Standard SMT resistor, capacitor etc" "R102" "1206" 10000 10000 5650 4350 2 100 "auto"] +( + Pad[-5905 -1181 -5905 1181 5118 2000 5718 "1" "1" "onsolder,square"] + Pad[5905 -1181 5905 1181 5118 2000 5718 "2" "2" "onsolder,square"] + ElementLine [-2362 3740 2362 3740 800] + ElementLine [-2362 -3740 2362 -3740 800] + + ) +Layer(1 "component") +( + Line[63405 10000 85000 10000 1000 4000 "clearline"] + Line[85000 10000 85000 50000 1000 4000 "clearline"] +) +Layer(2 "solder") +( + Line[15905 10000 30000 10000 2000 4000 "clearline"] + Line[30000 10000 30000 27500 2000 4000 "clearline"] + Line[30000 27500 85000 27500 2000 4000 "clearline"] + Line[85000 50000 85000 27500 2000 4000 "clearline"] +) +Layer(3 "comp-GND") +( +) +Layer(4 "comp-power") +( +) +Layer(5 "sold-GND") +( +) +Layer(6 "sold-power") +( +) +Layer(7 "signal3") +( +) +Layer(8 "outline") +( +) +Layer(9 "silk") +( +) +Layer(10 "silk") +( +) +NetList() +( + Net("GND" "(unknown)") + ( + Connect("R101-1") + Connect("R102-2") + ) +) diff --git a/src/djopt.c b/src/djopt.c index 80157c2d94..cb67e68657 100644 --- a/src/djopt.c +++ b/src/djopt.c @@ -2935,6 +2935,17 @@ Looks for vias where all traces leave in the same direction. Tries to move via in that direction to eliminate one of the traces (and thus a corner). +Example: + +Before vianudge: + +@center @image{vianudge,,,Example pcb before vianudge,png} + +After vianudge: + +@center @image{vianudge.out,,,Example pcb after vianudge,png} + + @item viatrim Looks for traces that go from via to via, where moving that trace to a different layer eliminates one or both vias. -- 2.11.4.GIT