media/libspeex_resampler/src/resample_neon.c

   1 /* Copyright (C) 2007-2008 Jean-Marc Valin
   2  * Copyright (C) 2008 Thorvald Natvig
   3  * Copyright (C) 2011 Texas Instruments
   4  *               author Jyri Sarha
   5  */
   6 /**
   7    @file resample_neon.h
   8    @brief Resampler functions (NEON version)
   9 */
  10 /*
  11    Redistribution and use in source and binary forms, with or without
  12    modification, are permitted provided that the following conditions
  13    are met:
  14
  15    - Redistributions of source code must retain the above copyright
  16    notice, this list of conditions and the following disclaimer.
  17
  18    - Redistributions in binary form must reproduce the above copyright
  19    notice, this list of conditions and the following disclaimer in the
  20    documentation and/or other materials provided with the distribution.
  21
  22    - Neither the name of the Xiph.org Foundation nor the names of its
  23    contributors may be used to endorse or promote products derived from
  24    this software without specific prior written permission.
  25
  26    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27    ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28    LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29    A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR
  30    CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31    EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32    PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33    PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34    LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35    NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 */
  38
  39 #include <stdint.h>
  40 #include "simd_detect.h"
  41
  42 #ifdef FIXED_POINT
  43 #if defined(__aarch64__)
  44 static inline int32_t saturate_32bit_to_16bit(int32_t a) {
  45     int32_t ret;
  46     asm ("fmov s0, %w[a]\n"
  47          "sqxtn h0, s0\n"
  48          "sxtl v0.4s, v0.4h\n"
  49          "fmov %w[ret], s0\n"
  50          : [ret] "=r" (ret)
  51          : [a] "r" (a)
  52          : "v0" );
  53     return ret;
  54 }
  55 #elif defined(__thumb2__)
  56 static inline int32_t saturate_32bit_to_16bit(int32_t a) {
  57     int32_t ret;
  58     asm ("ssat %[ret], #16, %[a]"
  59          : [ret] "=r" (ret)
  60          : [a] "r" (a)
  61          : );
  62     return ret;
  63 }
  64 #else
  65 static inline int32_t saturate_32bit_to_16bit(int32_t a) {
  66     int32_t ret;
  67     asm ("vmov.s32 d0[0], %[a]\n"
  68          "vqmovn.s32 d0, q0\n"
  69          "vmov.s16 %[ret], d0[0]\n"
  70          : [ret] "=r" (ret)
  71          : [a] "r" (a)
  72          : "q0");
  73     return ret;
  74 }
  75 #endif
  76 #undef WORD2INT
  77 #define WORD2INT(x) (saturate_32bit_to_16bit(x))
  78
  79 #define OVERRIDE_INNER_PRODUCT_SINGLE
  80 /* Only works when len % 4 == 0 and len >= 4 */
  81 #if defined(__aarch64__)
  82 inline int32_t inner_product_single(const int16_t *a, const int16_t *b, unsigned int len)
  83 {
  84     int32_t ret;
  85     uint32_t remainder = len % 16;
  86     len = len - remainder;
  87
  88     asm volatile ("      cmp %w[len], #0\n"
  89                   "      b.ne 1f\n"
  90                   "      ld1 {v16.4h}, [%[b]], #8\n"
  91                   "      ld1 {v20.4h}, [%[a]], #8\n"
  92                   "      subs %w[remainder], %w[remainder], #4\n"
  93                   "      smull v0.4s, v16.4h, v20.4h\n"
  94                   "      b.ne 4f\n"
  95                   "      b 5f\n"
  96                   "1:"
  97                   "      ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [%[b]], #32\n"
  98                   "      ld1 {v20.4h, v21.4h, v22.4h, v23.4h}, [%[a]], #32\n"
  99                   "      subs %w[len], %w[len], #16\n"
 100                   "      smull v0.4s, v16.4h, v20.4h\n"
 101                   "      smlal v0.4s, v17.4h, v21.4h\n"
 102                   "      smlal v0.4s, v18.4h, v22.4h\n"
 103                   "      smlal v0.4s, v19.4h, v23.4h\n"
 104                   "      b.eq 3f\n"
 105                   "2:"
 106                   "      ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [%[b]], #32\n"
 107                   "      ld1 {v20.4h, v21.4h, v22.4h, v23.4h}, [%[a]], #32\n"
 108                   "      subs %w[len], %w[len], #16\n"
 109                   "      smlal v0.4s, v16.4h, v20.4h\n"
 110                   "      smlal v0.4s, v17.4h, v21.4h\n"
 111                   "      smlal v0.4s, v18.4h, v22.4h\n"
 112                   "      smlal v0.4s, v19.4h, v23.4h\n"
 113                   "      b.ne 2b\n"
 114                   "3:"
 115                   "      cmp %w[remainder], #0\n"
 116                   "      b.eq 5f\n"
 117                   "4:"
 118                   "      ld1 {v18.4h}, [%[b]], #8\n"
 119                   "      ld1 {v22.4h}, [%[a]], #8\n"
 120                   "      subs %w[remainder], %w[remainder], #4\n"
 121                   "      smlal v0.4s, v18.4h, v22.4h\n"
 122                   "      b.ne 4b\n"
 123                   "5:"
 124                   "      saddlv d0, v0.4s\n"
 125                   "      sqxtn s0, d0\n"
 126                   "      sqrshrn h0, s0, #15\n"
 127                   "      sxtl v0.4s, v0.4h\n"
 128                   "      fmov %w[ret], s0\n"
 129                   : [ret] "=r" (ret), [a] "+r" (a), [b] "+r" (b),
 130                     [len] "+r" (len), [remainder] "+r" (remainder)
 131                   :
 132                   : "cc", "v0",
 133                     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23");
 134     return ret;
 135 }
 136 #else
 137 inline int32_t inner_product_single(const int16_t *a, const int16_t *b, unsigned int len)
 138 {
 139     int32_t ret;
 140     uint32_t remainder = len % 16;
 141     len = len - remainder;
 142
 143     asm volatile ("      cmp %[len], #0\n"
 144                   "      bne 1f\n"
 145                   "      vld1.16 {d16}, [%[b]]!\n"
 146                   "      vld1.16 {d20}, [%[a]]!\n"
 147                   "      subs %[remainder], %[remainder], #4\n"
 148                   "      vmull.s16 q0, d16, d20\n"
 149                   "      beq 5f\n"
 150                   "      b 4f\n"
 151                   "1:"
 152                   "      vld1.16 {d16, d17, d18, d19}, [%[b]]!\n"
 153                   "      vld1.16 {d20, d21, d22, d23}, [%[a]]!\n"
 154                   "      subs %[len], %[len], #16\n"
 155                   "      vmull.s16 q0, d16, d20\n"
 156                   "      vmlal.s16 q0, d17, d21\n"
 157                   "      vmlal.s16 q0, d18, d22\n"
 158                   "      vmlal.s16 q0, d19, d23\n"
 159                   "      beq 3f\n"
 160                   "2:"
 161                   "      vld1.16 {d16, d17, d18, d19}, [%[b]]!\n"
 162                   "      vld1.16 {d20, d21, d22, d23}, [%[a]]!\n"
 163                   "      subs %[len], %[len], #16\n"
 164                   "      vmlal.s16 q0, d16, d20\n"
 165                   "      vmlal.s16 q0, d17, d21\n"
 166                   "      vmlal.s16 q0, d18, d22\n"
 167                   "      vmlal.s16 q0, d19, d23\n"
 168                   "      bne 2b\n"
 169                   "3:"
 170                   "      cmp %[remainder], #0\n"
 171                   "      beq 5f\n"
 172                   "4:"
 173                   "      vld1.16 {d16}, [%[b]]!\n"
 174                   "      vld1.16 {d20}, [%[a]]!\n"
 175                   "      subs %[remainder], %[remainder], #4\n"
 176                   "      vmlal.s16 q0, d16, d20\n"
 177                   "      bne 4b\n"
 178                   "5:"
 179                   "      vaddl.s32 q0, d0, d1\n"
 180                   "      vadd.s64 d0, d0, d1\n"
 181                   "      vqmovn.s64 d0, q0\n"
 182                   "      vqrshrn.s32 d0, q0, #15\n"
 183                   "      vmov.s16 %[ret], d0[0]\n"
 184                   : [ret] "=r" (ret), [a] "+r" (a), [b] "+r" (b),
 185                     [len] "+r" (len), [remainder] "+r" (remainder)
 186                   :
 187                   : "cc", "q0",
 188                     "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23");
 189
 190     return ret;
 191 }
 192 #endif  // !defined(__aarch64__)
 193
 194 #elif defined(FLOATING_POINT)
 195 #if defined(__aarch64__)
 196 static inline int32_t saturate_float_to_16bit(float a) {
 197     int32_t ret;
 198     asm ("fcvtas s1, %s[a]\n"
 199          "sqxtn h1, s1\n"
 200          "sxtl v1.4s, v1.4h\n"
 201          "fmov %w[ret], s1\n"
 202          : [ret] "=r" (ret)
 203          : [a] "w" (a)
 204          : "v1");
 205     return ret;
 206 }
 207 #else
 208 static inline int32_t saturate_float_to_16bit(float a) {
 209     int32_t ret;
 210     asm ("vmov.f32 d0[0], %[a]\n"
 211          "vcvt.s32.f32 d0, d0, #15\n"
 212          "vqrshrn.s32 d0, q0, #15\n"
 213          "vmov.s16 %[ret], d0[0]\n"
 214          : [ret] "=r" (ret)
 215          : [a] "r" (a)
 216          : "q0");
 217     return ret;
 218 }
 219 #endif
 220
 221 #undef WORD2INT
 222 #define WORD2INT(x) (saturate_float_to_16bit(x))
 223
 224 #define OVERRIDE_INNER_PRODUCT_SINGLE
 225 /* Only works when len % 4 == 0 and len >= 4 */
 226 #if defined(__aarch64__)
 227 inline float inner_product_single(const float *a, const float *b, unsigned int len)
 228 {
 229     float ret;
 230     uint32_t remainder = len % 16;
 231     len = len - remainder;
 232
 233     asm volatile ("      cmp %w[len], #0\n"
 234                   "      b.ne 1f\n"
 235                   "      ld1 {v16.4s}, [%[b]], #16\n"
 236                   "      ld1 {v20.4s}, [%[a]], #16\n"
 237                   "      subs %w[remainder], %w[remainder], #4\n"
 238                   "      fmul v1.4s, v16.4s, v20.4s\n"
 239                   "      b.ne 4f\n"
 240                   "      b 5f\n"
 241                   "1:"
 242                   "      ld1 {v16.4s, v17.4s, v18.4s, v19.4s}, [%[b]], #64\n"
 243                   "      ld1 {v20.4s, v21.4s, v22.4s, v23.4s}, [%[a]], #64\n"
 244                   "      subs %w[len], %w[len], #16\n"
 245                   "      fmul v1.4s, v16.4s, v20.4s\n"
 246                   "      fmul v2.4s, v17.4s, v21.4s\n"
 247                   "      fmul v3.4s, v18.4s, v22.4s\n"
 248                   "      fmul v4.4s, v19.4s, v23.4s\n"
 249                   "      b.eq 3f\n"
 250                   "2:"
 251                   "      ld1 {v16.4s, v17.4s, v18.4s, v19.4s}, [%[b]], #64\n"
 252                   "      ld1 {v20.4s, v21.4s, v22.4s, v23.4s}, [%[a]], #64\n"
 253                   "      subs %w[len], %w[len], #16\n"
 254                   "      fmla v1.4s, v16.4s, v20.4s\n"
 255                   "      fmla v2.4s, v17.4s, v21.4s\n"
 256                   "      fmla v3.4s, v18.4s, v22.4s\n"
 257                   "      fmla v4.4s, v19.4s, v23.4s\n"
 258                   "      b.ne 2b\n"
 259                   "3:"
 260                   "      fadd v16.4s, v1.4s, v2.4s\n"
 261                   "      fadd v17.4s, v3.4s, v4.4s\n"
 262                   "      cmp %w[remainder], #0\n"
 263                   "      fadd v1.4s, v16.4s, v17.4s\n"
 264                   "      b.eq 5f\n"
 265                   "4:"
 266                   "      ld1 {v18.4s}, [%[b]], #16\n"
 267                   "      ld1 {v22.4s}, [%[a]], #16\n"
 268                   "      subs %w[remainder], %w[remainder], #4\n"
 269                   "      fmla v1.4s, v18.4s, v22.4s\n"
 270                   "      b.ne 4b\n"
 271                   "5:"
 272                   "      faddp v1.4s, v1.4s, v1.4s\n"
 273                   "      faddp %[ret].4s, v1.4s, v1.4s\n"
 274                   : [ret] "=w" (ret), [a] "+r" (a), [b] "+r" (b),
 275                     [len] "+r" (len), [remainder] "+r" (remainder)
 276                   :
 277                   : "cc", "v1", "v2", "v3", "v4",
 278                     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23");
 279     return ret;
 280 }
 281 #else
 282 inline float inner_product_single(const float *a, const float *b, unsigned int len)
 283 {
 284     float ret;
 285     uint32_t remainder = len % 16;
 286     len = len - remainder;
 287
 288     asm volatile ("      cmp %[len], #0\n"
 289                   "      bne 1f\n"
 290                   "      vld1.32 {q4}, [%[b]]!\n"
 291                   "      vld1.32 {q8}, [%[a]]!\n"
 292                   "      subs %[remainder], %[remainder], #4\n"
 293                   "      vmul.f32 q0, q4, q8\n"
 294                   "      bne 4f\n"
 295                   "      b 5f\n"
 296                   "1:"
 297                   "      vld1.32 {q4, q5}, [%[b]]!\n"
 298                   "      vld1.32 {q8, q9}, [%[a]]!\n"
 299                   "      vld1.32 {q6, q7}, [%[b]]!\n"
 300                   "      vld1.32 {q10, q11}, [%[a]]!\n"
 301                   "      subs %[len], %[len], #16\n"
 302                   "      vmul.f32 q0, q4, q8\n"
 303                   "      vmul.f32 q1, q5, q9\n"
 304                   "      vmul.f32 q2, q6, q10\n"
 305                   "      vmul.f32 q3, q7, q11\n"
 306                   "      beq 3f\n"
 307                   "2:"
 308                   "      vld1.32 {q4, q5}, [%[b]]!\n"
 309                   "      vld1.32 {q8, q9}, [%[a]]!\n"
 310                   "      vld1.32 {q6, q7}, [%[b]]!\n"
 311                   "      vld1.32 {q10, q11}, [%[a]]!\n"
 312                   "      subs %[len], %[len], #16\n"
 313                   "      vmla.f32 q0, q4, q8\n"
 314                   "      vmla.f32 q1, q5, q9\n"
 315                   "      vmla.f32 q2, q6, q10\n"
 316                   "      vmla.f32 q3, q7, q11\n"
 317                   "      bne 2b\n"
 318                   "3:"
 319                   "      vadd.f32 q4, q0, q1\n"
 320                   "      vadd.f32 q5, q2, q3\n"
 321                   "      cmp %[remainder], #0\n"
 322                   "      vadd.f32 q0, q4, q5\n"
 323                   "      beq 5f\n"
 324                   "4:"
 325                   "      vld1.32 {q6}, [%[b]]!\n"
 326                   "      vld1.32 {q10}, [%[a]]!\n"
 327                   "      subs %[remainder], %[remainder], #4\n"
 328                   "      vmla.f32 q0, q6, q10\n"
 329                   "      bne 4b\n"
 330                   "5:"
 331                   "      vadd.f32 d0, d0, d1\n"
 332                   "      vpadd.f32 d0, d0, d0\n"
 333                   "      vmov.f32 %[ret], d0[0]\n"
 334                   : [ret] "=r" (ret), [a] "+r" (a), [b] "+r" (b),
 335                     [len] "+l" (len), [remainder] "+l" (remainder)
 336                   :
 337                   : "cc", "q0", "q1", "q2", "q3",
 338                     "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11");
 339     return ret;
 340 }
 341 #endif  // defined(__aarch64__)
 342 #endif