rtl/NiosDevKit-EP1C20/src/fpgammix.v

   1 module fpgammix(// Clock and reset
   2             input  wire        clkin        // K5  PLL1 input clock (50 MHz)
   3            ,output wire        pld_clkout   // L8  Clock to zero-skew buffer Lancelot board
   4            ,input  wire        pld_clkfb    // L14 Feedback from pld_clkout to PLL2
   5            ,input  wire        reset_n      // C4  CPU Reset button
   6
   7            // Push buttons LEDs 7-segments
   8            ,input  wire  [3:0] sw           // Pushbutton switches
   9            ,output wire  [7:0] led          // Debugging LEDs
  10            ,output wire  [7:0] s7_0         // Debugging 7-segment LEDs
  11            ,output wire  [7:0] s7_1         // --
  12
  13            // Debug serial connection
  14            ,output wire        ttyb_txd     // Debug TxD
  15            ,input              ttyb_rxd     // Debug RxD
  16
  17            // Flash-SRAM-Ethernet bus
  18            ,output wire [22:0] fse_a        // Mainboard common bus address
  19            ,inout  wire [31:0] fse_d        // Mainboard common bus data
  20            ,output wire        flash_cs_n   // Flash ROM CS#
  21            ,output wire        enet_aen     // Ethernet Access Enable
  22            ,output wire        sram_cs_n    // SRAM CS#
  23            ,output wire  [3:0] sram_be_n    // SRAM byte enables
  24            ,output wire        sram_oe_n    // SRAM OE#
  25            ,output             sram_we_n    // SRAM WE#
  26
  27            // CompactFlash slot
  28            ,output wire [10:0] cf_a         // CompactFlash address bus
  29            ,inout  wire [15:0] cf_d         // CompactFlash data bus
  30            ,input              cf_rdy       // CompactFlash RDY
  31            ,input              cf_wait_n    // CompactFlash WAIT#
  32            ,output             cf_ce1_n     // CompactFlash CE1#
  33            ,output             cf_ce2_n     // CompactFlash CE2#
  34            ,output             cf_oe_n      // CompactFlash OE#
  35            ,output             cf_we_n      // CompactFlash WE#
  36            ,output             cf_reg_n     // CompactFlash REG#
  37            ,input              cf_cd1_n     // CompactFlash card detect
  38
  39            // Lancelot VGA interface
  40            ,output wire  [7:0] vga_r        // VGA red
  41            ,output wire  [7:0] vga_g        // VGA green
  42            ,output wire  [7:0] vga_b        // VGA blue
  43            ,output wire        vga_hs       // VGA horz sync
  44            ,output wire        vga_vs       // VGA vert sync
  45            ,output wire        vga_blank_n  // VGA DAC force blank
  46            ,output wire        vga_sync_n   // VGA sync enable
  47            ,output wire        vga_sync_t   // VGA sync on R/G/B
  48            ,output wire        vga_m1       // VGA color space config
  49            ,output wire        vga_m2       // VGA color space config
  50
  51            // Lancelot PS/2 keyboard/mouse
  52            ,output             ps2_sel      // PS/2 port enable
  53            ,inout              ps2_kclk     // PS/2 keyboard clock
  54            ,inout              ps2_kdata    // PS/2 keyboard data
  55            ,inout              ps2_mclk     // PS/2 mouse clock
  56            ,inout              ps2_mdata    // PS/2 mouse data
  57
  58            // Lancelot Audio
  59            ,output wire        audio_l      // 1-bit Sigma-delta converter
  60            ,output wire        audio_r      // 1-bit Sigma-delta converter
  61            );
  62
  63    wire            reset,
  64                    reset_stb; // Dummy, not used
  65    wire            clk25MHz, clk100MHz, pll1_locked;
  66
  67    /* Filter the reset signal and synchronize it. Purists may not like
  68       the fact that a short async reset will be ignored.  Whatever. */
  69    filter filter_reset(clk25MHz, ~reset_n | ~pll1_locked, reset, reset_stb);
  70
  71    pll1 pll1(
  72         .inclk0(clkin),         // 50 MHz input clock
  73         .c0(clk100MHz),         // x2/1 = 100 MHz output clock
  74         .c1(clk25MHz),          // x1/2 =  25 MHz output clock
  75         .locked(pll1_locked),
  76         .e0(pld_clkout)         // External only output x1/2 = 25 MHz
  77         );
  78
  79    system
  80          (clk25MHz     // 25 MHz clock
  81          ,reset        // C4  CPU Reset button
  82
  83          ,sw           // Pushbutton switches
  84          ,led          // Debugging LEDs
  85          ,s7_0         // Debugging 7-segment LEDs
  86          ,s7_1         // --
  87
  88          ,ttyb_txd     // Debug TxD
  89          ,ttyb_rxd     // Debug RxD
  90
  91          ,fse_a        // Mainboard common bus address
  92          ,fse_d        // Mainboard common bus data
  93          ,flash_cs_n   // Flash ROM CS#
  94          ,enet_aen     // Ethernet Access Enable
  95          ,sram_cs_n    // SRAM CS#
  96          ,sram_be_n    // SRAM byte enables
  97          ,sram_oe_n    // SRAM OE#
  98          ,sram_we_n    // SRAM WE#
  99
 100          ,cf_a         // CompactFlash address bus
 101          ,cf_d         // CompactFlash data bus
 102          ,cf_rdy       // CompactFlash RDY
 103          ,cf_wait_n    // CompactFlash WAIT#
 104          ,cf_ce1_n     // CompactFlash CE1#
 105          ,cf_ce2_n     // CompactFlash CE2#
 106          ,cf_oe_n      // CompactFlash OE#
 107          ,cf_we_n      // CompactFlash WE#
 108          ,cf_reg_n     // CompactFlash REG#
 109          ,cf_cd1_n     // CompactFlash card detect
 110
 111          ,vga_r        // VGA red
 112          ,vga_g        // VGA green
 113          ,vga_b        // VGA blue
 114          ,vga_hs       // VGA horz sync
 115          ,vga_vs       // VGA vert sync
 116          ,vga_blank_n  // VGA DAC force blank
 117          ,vga_sync_n   // VGA sync enable
 118          ,vga_sync_t   // VGA sync on R/G/B
 119          ,vga_m1       // VGA color space config
 120          ,vga_m2       // VGA color space config
 121
 122          ,ps2_sel      // PS/2 port input/output select
 123          ,ps2_kclk     // PS/2 keyboard clock
 124          ,ps2_kdata    // PS/2 keyboard data
 125          ,ps2_mclk     // PS/2 mouse clock
 126          ,ps2_mdata    // PS/2 mouse data
 127
 128
 129          ,audio_l      // 1-bit Sigma-delta converter
 130          ,audio_r      // 1-bit Sigma-delta converter
 131          );
 132 endmodule // main