initial
[fpgammix.git] / rtl / Icarus / regfile.v
blob1a7dc0f508da7baef4aa527a7742cf1102008f72
1 // -----------------------------------------------------------------------
2 //
3 // Copyright 2004 Tommy Thorn - All Rights Reserved
4 //
5 // This program is free software; you can redistribute it and/or modify
6 // it under the terms of the GNU General Public License as published by
7 // the Free Software Foundation, Inc., 53 Temple Place Ste 330,
8 // Bostom MA 02111-1307, USA; either version 2 of the License, or
9 // (at your option) any later version; incorporated herein by reference.
11 // -----------------------------------------------------------------------
13 `timescale 1ns/10ps
15 `define D 8 /* A parameter would be more useful */
17 module regfile(input wire clock,
19 input wire rden,
20 input wire [`D:0] rdaddress,
21 output wire [63:0] q /* rddata would have been better */,
23 input wire wren,
24 input wire [`D:0] wraddress,
25 input wire [63:0] data /* wrdata would have been better */);
27 parameter ID = 0;
28 parameter V = 0;
30 reg [`D:0] addr_delayed = 0;
31 reg [63:0] ram[(2 << `D) - 1: 0];
33 /* XXX Accidentally found a bug in Icarus as I had accidentally written
34 reg [63:0] ram[(2 << `D) - 1: 0];
35 turning
36 assign q = ram[addr_delayed];
37 into a bit extract rather than a memory lookup.
39 turned out that for addr_delayed == ??? it would crash with a
40 segmentation error.
43 assign q = ram[addr_delayed];
45 always @(posedge clock) if (1) begin
46 if(V)$display("%05d REGFILE addr_delayed=#%x q=#%x rdaddress=%x rden%x",
47 $time,
48 addr_delayed, q, rdaddress, rden);
50 if (rden) begin
51 if(V)$display("%05d REGFILE %c read from XXXXX", $time, ID);
52 addr_delayed <= rdaddress;
53 // $display("regfile %2x -> %x", rdaddress, ram0[rdaddress]);
54 // for (i = 0; i < 256; i = i + 1) $display("regfile %2x -> %2x", i, ram0[i]);
55 end
56 if (wren) begin
57 if(V)$display("%05d RF Writing %x -> [%x]", $time, data, wraddress);
58 ram[wraddress] <= data;
59 end
60 end
62 reg [`D+1:0] i;
63 initial for (i = 0; i < 1 << (`D+1); i = i + 1) ram[i] = 0;
64 endmodule