?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
V4L/DVB (12510): soc-camera: (partially) convert to v4l2-(sub)dev API
[firewire-audio.git] / drivers / media / video / ov772x.c
blob119159773a68fea92f1e30334fade584c2491416
1 /*
2 * ov772x Camera Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov7670 and soc_camera_platform driver,
8 *
9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 * Copyright (C) 2008 Magnus Damm
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/videodev2.h>
24 #include <media/v4l2-chip-ident.h>
25 #include <media/v4l2-subdev.h>
26 #include <media/soc_camera.h>
27 #include <media/ov772x.h>
28
29 /*
30 * register offset
31 */
32 #define GAIN 0x00 /* AGC - Gain control gain setting */
33 #define BLUE 0x01 /* AWB - Blue channel gain setting */
34 #define RED 0x02 /* AWB - Red channel gain setting */
35 #define GREEN 0x03 /* AWB - Green channel gain setting */
36 #define COM1 0x04 /* Common control 1 */
37 #define BAVG 0x05 /* U/B Average Level */
38 #define GAVG 0x06 /* Y/Gb Average Level */
39 #define RAVG 0x07 /* V/R Average Level */
40 #define AECH 0x08 /* Exposure Value - AEC MSBs */
41 #define COM2 0x09 /* Common control 2 */
42 #define PID 0x0A /* Product ID Number MSB */
43 #define VER 0x0B /* Product ID Number LSB */
44 #define COM3 0x0C /* Common control 3 */
45 #define COM4 0x0D /* Common control 4 */
46 #define COM5 0x0E /* Common control 5 */
47 #define COM6 0x0F /* Common control 6 */
48 #define AEC 0x10 /* Exposure Value */
49 #define CLKRC 0x11 /* Internal clock */
50 #define COM7 0x12 /* Common control 7 */
51 #define COM8 0x13 /* Common control 8 */
52 #define COM9 0x14 /* Common control 9 */
53 #define COM10 0x15 /* Common control 10 */
54 #define REG16 0x16 /* Register 16 */
55 #define HSTART 0x17 /* Horizontal sensor size */
56 #define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */
57 #define VSTART 0x19 /* Vertical frame (row) start high 8-bit */
58 #define VSIZE 0x1A /* Vertical sensor size */
59 #define PSHFT 0x1B /* Data format - pixel delay select */
60 #define MIDH 0x1C /* Manufacturer ID byte - high */
61 #define MIDL 0x1D /* Manufacturer ID byte - low */
62 #define LAEC 0x1F /* Fine AEC value */
63 #define COM11 0x20 /* Common control 11 */
64 #define BDBASE 0x22 /* Banding filter Minimum AEC value */
65 #define DBSTEP 0x23 /* Banding filter Maximum Setp */
66 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
67 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
68 #define VPT 0x26 /* AGC/AEC Fast mode operating region */
69 #define REG28 0x28 /* Register 28 */
70 #define HOUTSIZE 0x29 /* Horizontal data output size MSBs */
71 #define EXHCH 0x2A /* Dummy pixel insert MSB */
72 #define EXHCL 0x2B /* Dummy pixel insert LSB */
73 #define VOUTSIZE 0x2C /* Vertical data output size MSBs */
74 #define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
75 #define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */
76 #define YAVE 0x2F /* Y/G Channel Average value */
77 #define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */
78 #define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */
79 #define HREF 0x32 /* Image start and size control */
80 #define DM_LNL 0x33 /* Dummy line low 8 bits */
81 #define DM_LNH 0x34 /* Dummy line high 8 bits */
82 #define ADOFF_B 0x35 /* AD offset compensation value for B channel */
83 #define ADOFF_R 0x36 /* AD offset compensation value for R channel */
84 #define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */
85 #define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */
86 #define OFF_B 0x39 /* Analog process B channel offset value */
87 #define OFF_R 0x3A /* Analog process R channel offset value */
88 #define OFF_GB 0x3B /* Analog process Gb channel offset value */
89 #define OFF_GR 0x3C /* Analog process Gr channel offset value */
90 #define COM12 0x3D /* Common control 12 */
91 #define COM13 0x3E /* Common control 13 */
92 #define COM14 0x3F /* Common control 14 */
93 #define COM15 0x40 /* Common control 15*/
94 #define COM16 0x41 /* Common control 16 */
95 #define TGT_B 0x42 /* BLC blue channel target value */
96 #define TGT_R 0x43 /* BLC red channel target value */
97 #define TGT_GB 0x44 /* BLC Gb channel target value */
98 #define TGT_GR 0x45 /* BLC Gr channel target value */
99 /* for ov7720 */
100 #define LCC0 0x46 /* Lens correction control 0 */
101 #define LCC1 0x47 /* Lens correction option 1 - X coordinate */
102 #define LCC2 0x48 /* Lens correction option 2 - Y coordinate */
103 #define LCC3 0x49 /* Lens correction option 3 */
104 #define LCC4 0x4A /* Lens correction option 4 - radius of the circular */
105 #define LCC5 0x4B /* Lens correction option 5 */
106 #define LCC6 0x4C /* Lens correction option 6 */
107 /* for ov7725 */
108 #define LC_CTR 0x46 /* Lens correction control */
109 #define LC_XC 0x47 /* X coordinate of lens correction center relative */
110 #define LC_YC 0x48 /* Y coordinate of lens correction center relative */
111 #define LC_COEF 0x49 /* Lens correction coefficient */
112 #define LC_RADI 0x4A /* Lens correction radius */
113 #define LC_COEFB 0x4B /* Lens B channel compensation coefficient */
114 #define LC_COEFR 0x4C /* Lens R channel compensation coefficient */
115
116 #define FIXGAIN 0x4D /* Analog fix gain amplifer */
117 #define AREF0 0x4E /* Sensor reference control */
118 #define AREF1 0x4F /* Sensor reference current control */
119 #define AREF2 0x50 /* Analog reference control */
120 #define AREF3 0x51 /* ADC reference control */
121 #define AREF4 0x52 /* ADC reference control */
122 #define AREF5 0x53 /* ADC reference control */
123 #define AREF6 0x54 /* Analog reference control */
124 #define AREF7 0x55 /* Analog reference control */
125 #define UFIX 0x60 /* U channel fixed value output */
126 #define VFIX 0x61 /* V channel fixed value output */
127 #define AWBB_BLK 0x62 /* AWB option for advanced AWB */
128 #define AWB_CTRL0 0x63 /* AWB control byte 0 */
129 #define DSP_CTRL1 0x64 /* DSP control byte 1 */
130 #define DSP_CTRL2 0x65 /* DSP control byte 2 */
131 #define DSP_CTRL3 0x66 /* DSP control byte 3 */
132 #define DSP_CTRL4 0x67 /* DSP control byte 4 */
133 #define AWB_BIAS 0x68 /* AWB BLC level clip */
134 #define AWB_CTRL1 0x69 /* AWB control 1 */
135 #define AWB_CTRL2 0x6A /* AWB control 2 */
136 #define AWB_CTRL3 0x6B /* AWB control 3 */
137 #define AWB_CTRL4 0x6C /* AWB control 4 */
138 #define AWB_CTRL5 0x6D /* AWB control 5 */
139 #define AWB_CTRL6 0x6E /* AWB control 6 */
140 #define AWB_CTRL7 0x6F /* AWB control 7 */
141 #define AWB_CTRL8 0x70 /* AWB control 8 */
142 #define AWB_CTRL9 0x71 /* AWB control 9 */
143 #define AWB_CTRL10 0x72 /* AWB control 10 */
144 #define AWB_CTRL11 0x73 /* AWB control 11 */
145 #define AWB_CTRL12 0x74 /* AWB control 12 */
146 #define AWB_CTRL13 0x75 /* AWB control 13 */
147 #define AWB_CTRL14 0x76 /* AWB control 14 */
148 #define AWB_CTRL15 0x77 /* AWB control 15 */
149 #define AWB_CTRL16 0x78 /* AWB control 16 */
150 #define AWB_CTRL17 0x79 /* AWB control 17 */
151 #define AWB_CTRL18 0x7A /* AWB control 18 */
152 #define AWB_CTRL19 0x7B /* AWB control 19 */
153 #define AWB_CTRL20 0x7C /* AWB control 20 */
154 #define AWB_CTRL21 0x7D /* AWB control 21 */
155 #define GAM1 0x7E /* Gamma Curve 1st segment input end point */
156 #define GAM2 0x7F /* Gamma Curve 2nd segment input end point */
157 #define GAM3 0x80 /* Gamma Curve 3rd segment input end point */
158 #define GAM4 0x81 /* Gamma Curve 4th segment input end point */
159 #define GAM5 0x82 /* Gamma Curve 5th segment input end point */
160 #define GAM6 0x83 /* Gamma Curve 6th segment input end point */
161 #define GAM7 0x84 /* Gamma Curve 7th segment input end point */
162 #define GAM8 0x85 /* Gamma Curve 8th segment input end point */
163 #define GAM9 0x86 /* Gamma Curve 9th segment input end point */
164 #define GAM10 0x87 /* Gamma Curve 10th segment input end point */
165 #define GAM11 0x88 /* Gamma Curve 11th segment input end point */
166 #define GAM12 0x89 /* Gamma Curve 12th segment input end point */
167 #define GAM13 0x8A /* Gamma Curve 13th segment input end point */
168 #define GAM14 0x8B /* Gamma Curve 14th segment input end point */
169 #define GAM15 0x8C /* Gamma Curve 15th segment input end point */
170 #define SLOP 0x8D /* Gamma curve highest segment slope */
171 #define DNSTH 0x8E /* De-noise threshold */
172 #define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */
173 #define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
174 #define DNSOFF 0x91 /* Auto De-noise threshold control */
175 #define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */
176 #define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */
177 #define MTX1 0x94 /* Matrix coefficient 1 */
178 #define MTX2 0x95 /* Matrix coefficient 2 */
179 #define MTX3 0x96 /* Matrix coefficient 3 */
180 #define MTX4 0x97 /* Matrix coefficient 4 */
181 #define MTX5 0x98 /* Matrix coefficient 5 */
182 #define MTX6 0x99 /* Matrix coefficient 6 */
183 #define MTX_CTRL 0x9A /* Matrix control */
184 #define BRIGHT 0x9B /* Brightness control */
185 #define CNTRST 0x9C /* Contrast contrast */
186 #define CNTRST_CTRL 0x9D /* Contrast contrast center */
187 #define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */
188 #define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */
189 #define SCAL0 0xA0 /* Scaling control 0 */
190 #define SCAL1 0xA1 /* Scaling control 1 */
191 #define SCAL2 0xA2 /* Scaling control 2 */
192 #define FIFODLYM 0xA3 /* FIFO manual mode delay control */
193 #define FIFODLYA 0xA4 /* FIFO auto mode delay control */
194 #define SDE 0xA6 /* Special digital effect control */
195 #define USAT 0xA7 /* U component saturation control */
196 #define VSAT 0xA8 /* V component saturation control */
197 /* for ov7720 */
198 #define HUE0 0xA9 /* Hue control 0 */
199 #define HUE1 0xAA /* Hue control 1 */
200 /* for ov7725 */
201 #define HUECOS 0xA9 /* Cosine value */
202 #define HUESIN 0xAA /* Sine value */
203
204 #define SIGN 0xAB /* Sign bit for Hue and contrast */
205 #define DSPAUTO 0xAC /* DSP auto function ON/OFF control */
206
207 /*
208 * register detail
209 */
210
211 /* COM2 */
212 #define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
213 /* Output drive capability */
214 #define OCAP_1x 0x00 /* 1x */
215 #define OCAP_2x 0x01 /* 2x */
216 #define OCAP_3x 0x02 /* 3x */
217 #define OCAP_4x 0x03 /* 4x */
218
219 /* COM3 */
220 #define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
221 #define IMG_MASK (VFLIP_IMG | HFLIP_IMG)
222
223 #define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */
224 #define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */
225 #define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */
226 #define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */
227 #define SWAP_ML 0x08 /* Swap output MSB/LSB */
228 /* Tri-state option for output clock */
229 #define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */
230 /* 1: No tri-state at this period */
231 /* Tri-state option for output data */
232 #define NOTRI_DATA 0x02 /* 0: Tri-state at this period */
233 /* 1: No tri-state at this period */
234 #define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */
235
236 /* COM4 */
237 /* PLL frequency control */
238 #define PLL_BYPASS 0x00 /* 00: Bypass PLL */
239 #define PLL_4x 0x40 /* 01: PLL 4x */
240 #define PLL_6x 0x80 /* 10: PLL 6x */
241 #define PLL_8x 0xc0 /* 11: PLL 8x */
242 /* AEC evaluate window */
243 #define AEC_FULL 0x00 /* 00: Full window */
244 #define AEC_1p2 0x10 /* 01: 1/2 window */
245 #define AEC_1p4 0x20 /* 10: 1/4 window */
246 #define AEC_2p3 0x30 /* 11: Low 2/3 window */
247
248 /* COM5 */
249 #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
250 #define AFR_SPPED 0x40 /* Auto frame rate control speed slection */
251 /* Auto frame rate max rate control */
252 #define AFR_NO_RATE 0x00 /* No reduction of frame rate */
253 #define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */
254 #define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */
255 #define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */
256 /* Auto frame rate active point control */
257 #define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */
258 #define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */
259 #define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */
260 #define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */
261 /* AEC max step control */
262 #define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */
263 /* 1 : No limit to AEC increase step */
264
265 /* COM7 */
266 /* SCCB Register Reset */
267 #define SCCB_RESET 0x80 /* 0 : No change */
268 /* 1 : Resets all registers to default */
269 /* Resolution selection */
270 #define SLCT_MASK 0x40 /* Mask of VGA or QVGA */
271 #define SLCT_VGA 0x00 /* 0 : VGA */
272 #define SLCT_QVGA 0x40 /* 1 : QVGA */
273 #define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */
274 /* RGB output format control */
275 #define FMT_MASK 0x0c /* Mask of color format */
276 #define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */
277 #define FMT_RGB565 0x04 /* 01 : RGB 565 */
278 #define FMT_RGB555 0x08 /* 10 : RGB 555 */
279 #define FMT_RGB444 0x0c /* 11 : RGB 444 */
280 /* Output format control */
281 #define OFMT_MASK 0x03 /* Mask of output format */
282 #define OFMT_YUV 0x00 /* 00 : YUV */
283 #define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */
284 #define OFMT_RGB 0x02 /* 10 : RGB */
285 #define OFMT_BRAW 0x03 /* 11 : Bayer RAW */
286
287 /* COM8 */
288 #define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */
289 /* AEC Setp size limit */
290 #define UNLMT_STEP 0x40 /* 0 : Step size is limited */
291 /* 1 : Unlimited step size */
292 #define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */
293 #define AEC_BND 0x10 /* Enable AEC below banding value */
294 #define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */
295 #define AGC_ON 0x04 /* AGC Enable */
296 #define AWB_ON 0x02 /* AWB Enable */
297 #define AEC_ON 0x01 /* AEC Enable */
298
299 /* COM9 */
300 #define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */
301 /* Automatic gain ceiling - maximum AGC value */
302 #define GAIN_2x 0x00 /* 000 : 2x */
303 #define GAIN_4x 0x10 /* 001 : 4x */
304 #define GAIN_8x 0x20 /* 010 : 8x */
305 #define GAIN_16x 0x30 /* 011 : 16x */
306 #define GAIN_32x 0x40 /* 100 : 32x */
307 #define GAIN_64x 0x50 /* 101 : 64x */
308 #define GAIN_128x 0x60 /* 110 : 128x */
309 #define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
310 #define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
311
312 /* COM11 */
313 #define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */
314 #define SGLF_TRIG 0x01 /* Single frame transfer trigger */
315
316 /* EXHCH */
317 #define VSIZE_LSB 0x04 /* Vertical data output size LSB */
318
319 /* DSP_CTRL1 */
320 #define FIFO_ON 0x80 /* FIFO enable/disable selection */
321 #define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */
322 #define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */
323 #define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */
324 #define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */
325 #define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */
326 #define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */
327 #define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */
328
329 /* DSP_CTRL3 */
330 #define UV_MASK 0x80 /* UV output sequence option */
331 #define UV_ON 0x80 /* ON */
332 #define UV_OFF 0x00 /* OFF */
333 #define CBAR_MASK 0x20 /* DSP Color bar mask */
334 #define CBAR_ON 0x20 /* ON */
335 #define CBAR_OFF 0x00 /* OFF */
336
337 /* HSTART */
338 #define HST_VGA 0x23
339 #define HST_QVGA 0x3F
340
341 /* HSIZE */
342 #define HSZ_VGA 0xA0
343 #define HSZ_QVGA 0x50
344
345 /* VSTART */
346 #define VST_VGA 0x07
347 #define VST_QVGA 0x03
348
349 /* VSIZE */
350 #define VSZ_VGA 0xF0
351 #define VSZ_QVGA 0x78
352
353 /* HOUTSIZE */
354 #define HOSZ_VGA 0xA0
355 #define HOSZ_QVGA 0x50
356
357 /* VOUTSIZE */
358 #define VOSZ_VGA 0xF0
359 #define VOSZ_QVGA 0x78
360
361 /* DSPAUTO (DSP Auto Function ON/OFF Control) */
362 #define AWB_ACTRL 0x80 /* AWB auto threshold control */
363 #define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */
364 #define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */
365 #define UV_ACTRL 0x10 /* UV adjust auto slope control */
366 #define SCAL0_ACTRL 0x08 /* Auto scaling factor control */
367 #define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */
368
369 /*
370 * ID
371 */
372 #define OV7720 0x7720
373 #define OV7725 0x7721
374 #define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
375
376 /*
377 * struct
378 */
379 struct regval_list {
380 unsigned char reg_num;
381 unsigned char value;
382 };
383
384 struct ov772x_color_format {
385 char *name;
386 __u32 fourcc;
387 u8 dsp3;
388 u8 com3;
389 u8 com7;
390 };
391
392 struct ov772x_win_size {
393 char *name;
394 __u32 width;
395 __u32 height;
396 unsigned char com7_bit;
397 const struct regval_list *regs;
398 };
399
400 struct ov772x_priv {
401 struct v4l2_subdev subdev;
402 struct ov772x_camera_info *info;
403 const struct ov772x_color_format *fmt;
404 const struct ov772x_win_size *win;
405 int model;
406 unsigned int flag_vflip:1;
407 unsigned int flag_hflip:1;
408 };
409
410 #define ENDMARKER { 0xff, 0xff }
411
412 /*
413 * register setting for window size
414 */
415 static const struct regval_list ov772x_qvga_regs[] = {
416 { HSTART, HST_QVGA },
417 { HSIZE, HSZ_QVGA },
418 { VSTART, VST_QVGA },
419 { VSIZE, VSZ_QVGA },
420 { HOUTSIZE, HOSZ_QVGA },
421 { VOUTSIZE, VOSZ_QVGA },
422 ENDMARKER,
423 };
424
425 static const struct regval_list ov772x_vga_regs[] = {
426 { HSTART, HST_VGA },
427 { HSIZE, HSZ_VGA },
428 { VSTART, VST_VGA },
429 { VSIZE, VSZ_VGA },
430 { HOUTSIZE, HOSZ_VGA },
431 { VOUTSIZE, VOSZ_VGA },
432 ENDMARKER,
433 };
434
435 /*
436 * supported format list
437 */
438
439 #define SETFOURCC(type) .name = (#type), .fourcc = (V4L2_PIX_FMT_ ## type)
440 static const struct soc_camera_data_format ov772x_fmt_lists[] = {
441 {
442 SETFOURCC(YUYV),
443 .depth = 16,
444 .colorspace = V4L2_COLORSPACE_JPEG,
445 },
446 {
447 SETFOURCC(YVYU),
448 .depth = 16,
449 .colorspace = V4L2_COLORSPACE_JPEG,
450 },
451 {
452 SETFOURCC(UYVY),
453 .depth = 16,
454 .colorspace = V4L2_COLORSPACE_JPEG,
455 },
456 {
457 SETFOURCC(RGB555),
458 .depth = 16,
459 .colorspace = V4L2_COLORSPACE_SRGB,
460 },
461 {
462 SETFOURCC(RGB555X),
463 .depth = 16,
464 .colorspace = V4L2_COLORSPACE_SRGB,
465 },
466 {
467 SETFOURCC(RGB565),
468 .depth = 16,
469 .colorspace = V4L2_COLORSPACE_SRGB,
470 },
471 {
472 SETFOURCC(RGB565X),
473 .depth = 16,
474 .colorspace = V4L2_COLORSPACE_SRGB,
475 },
476 };
477
478 /*
479 * color format list
480 */
481 static const struct ov772x_color_format ov772x_cfmts[] = {
482 {
483 SETFOURCC(YUYV),
484 .dsp3 = 0x0,
485 .com3 = SWAP_YUV,
486 .com7 = OFMT_YUV,
487 },
488 {
489 SETFOURCC(YVYU),
490 .dsp3 = UV_ON,
491 .com3 = SWAP_YUV,
492 .com7 = OFMT_YUV,
493 },
494 {
495 SETFOURCC(UYVY),
496 .dsp3 = 0x0,
497 .com3 = 0x0,
498 .com7 = OFMT_YUV,
499 },
500 {
501 SETFOURCC(RGB555),
502 .dsp3 = 0x0,
503 .com3 = SWAP_RGB,
504 .com7 = FMT_RGB555 | OFMT_RGB,
505 },
506 {
507 SETFOURCC(RGB555X),
508 .dsp3 = 0x0,
509 .com3 = 0x0,
510 .com7 = FMT_RGB555 | OFMT_RGB,
511 },
512 {
513 SETFOURCC(RGB565),
514 .dsp3 = 0x0,
515 .com3 = SWAP_RGB,
516 .com7 = FMT_RGB565 | OFMT_RGB,
517 },
518 {
519 SETFOURCC(RGB565X),
520 .dsp3 = 0x0,
521 .com3 = 0x0,
522 .com7 = FMT_RGB565 | OFMT_RGB,
523 },
524 };
525
526
527 /*
528 * window size list
529 */
530 #define VGA_WIDTH 640
531 #define VGA_HEIGHT 480
532 #define QVGA_WIDTH 320
533 #define QVGA_HEIGHT 240
534 #define MAX_WIDTH VGA_WIDTH
535 #define MAX_HEIGHT VGA_HEIGHT
536
537 static const struct ov772x_win_size ov772x_win_vga = {
538 .name = "VGA",
539 .width = VGA_WIDTH,
540 .height = VGA_HEIGHT,
541 .com7_bit = SLCT_VGA,
542 .regs = ov772x_vga_regs,
543 };
544
545 static const struct ov772x_win_size ov772x_win_qvga = {
546 .name = "QVGA",
547 .width = QVGA_WIDTH,
548 .height = QVGA_HEIGHT,
549 .com7_bit = SLCT_QVGA,
550 .regs = ov772x_qvga_regs,
551 };
552
553 static const struct v4l2_queryctrl ov772x_controls[] = {
554 {
555 .id = V4L2_CID_VFLIP,
556 .type = V4L2_CTRL_TYPE_BOOLEAN,
557 .name = "Flip Vertically",
558 .minimum = 0,
559 .maximum = 1,
560 .step = 1,
561 .default_value = 0,
562 },
563 {
564 .id = V4L2_CID_HFLIP,
565 .type = V4L2_CTRL_TYPE_BOOLEAN,
566 .name = "Flip Horizontally",
567 .minimum = 0,
568 .maximum = 1,
569 .step = 1,
570 .default_value = 0,
571 },
572 };
573
574
575 /*
576 * general function
577 */
578
579 static struct ov772x_priv *to_ov772x(const struct i2c_client *client)
580 {
581 return container_of(i2c_get_clientdata(client), struct ov772x_priv, subdev);
582 }
583
584 static int ov772x_write_array(struct i2c_client *client,
585 const struct regval_list *vals)
586 {
587 while (vals->reg_num != 0xff) {
588 int ret = i2c_smbus_write_byte_data(client,
589 vals->reg_num,
590 vals->value);
591 if (ret < 0)
592 return ret;
593 vals++;
594 }
595 return 0;
596 }
597
598 static int ov772x_mask_set(struct i2c_client *client,
599 u8 command,
600 u8 mask,
601 u8 set)
602 {
603 s32 val = i2c_smbus_read_byte_data(client, command);
604 if (val < 0)
605 return val;
606
607 val &= ~mask;
608 val |= set & mask;
609
610 return i2c_smbus_write_byte_data(client, command, val);
611 }
612
613 static int ov772x_reset(struct i2c_client *client)
614 {
615 int ret = i2c_smbus_write_byte_data(client, COM7, SCCB_RESET);
616 msleep(1);
617 return ret;
618 }
619
620 /*
621 * soc_camera_ops function
622 */
623
624 static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
625 {
626 struct i2c_client *client = sd->priv;
627 struct ov772x_priv *priv = to_ov772x(client);
628
629 if (!enable) {
630 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE);
631 return 0;
632 }
633
634 if (!priv->win || !priv->fmt) {
635 dev_err(&client->dev, "norm or win select error\n");
636 return -EPERM;
637 }
638
639 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, 0);
640
641 dev_dbg(&client->dev,
642 "format %s, win %s\n", priv->fmt->name, priv->win->name);
643
644 return 0;
645 }
646
647 static int ov772x_set_bus_param(struct soc_camera_device *icd,
648 unsigned long flags)
649 {
650 return 0;
651 }
652
653 static unsigned long ov772x_query_bus_param(struct soc_camera_device *icd)
654 {
655 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
656 struct ov772x_priv *priv = i2c_get_clientdata(client);
657 struct soc_camera_link *icl = to_soc_camera_link(icd);
658 unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER |
659 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH |
660 SOCAM_DATA_ACTIVE_HIGH | priv->info->buswidth;
661
662 return soc_camera_apply_sensor_flags(icl, flags);
663 }
664
665 static int ov772x_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
666 {
667 struct i2c_client *client = sd->priv;
668 struct ov772x_priv *priv = to_ov772x(client);
669
670 switch (ctrl->id) {
671 case V4L2_CID_VFLIP:
672 ctrl->value = priv->flag_vflip;
673 break;
674 case V4L2_CID_HFLIP:
675 ctrl->value = priv->flag_hflip;
676 break;
677 }
678 return 0;
679 }
680
681 static int ov772x_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
682 {
683 struct i2c_client *client = sd->priv;
684 struct ov772x_priv *priv = to_ov772x(client);
685 int ret = 0;
686 u8 val;
687
688 switch (ctrl->id) {
689 case V4L2_CID_VFLIP:
690 val = ctrl->value ? VFLIP_IMG : 0x00;
691 priv->flag_vflip = ctrl->value;
692 if (priv->info->flags & OV772X_FLAG_VFLIP)
693 val ^= VFLIP_IMG;
694 ret = ov772x_mask_set(client, COM3, VFLIP_IMG, val);
695 break;
696 case V4L2_CID_HFLIP:
697 val = ctrl->value ? HFLIP_IMG : 0x00;
698 priv->flag_hflip = ctrl->value;
699 if (priv->info->flags & OV772X_FLAG_HFLIP)
700 val ^= HFLIP_IMG;
701 ret = ov772x_mask_set(client, COM3, HFLIP_IMG, val);
702 break;
703 }
704
705 return ret;
706 }
707
708 static int ov772x_g_chip_ident(struct v4l2_subdev *sd,
709 struct v4l2_dbg_chip_ident *id)
710 {
711 struct i2c_client *client = sd->priv;
712 struct ov772x_priv *priv = to_ov772x(client);
713
714 id->ident = priv->model;
715 id->revision = 0;
716
717 return 0;
718 }
719
720 #ifdef CONFIG_VIDEO_ADV_DEBUG
721 static int ov772x_g_register(struct v4l2_subdev *sd,
722 struct v4l2_dbg_register *reg)
723 {
724 struct i2c_client *client = sd->priv;
725 int ret;
726
727 reg->size = 1;
728 if (reg->reg > 0xff)
729 return -EINVAL;
730
731 ret = i2c_smbus_read_byte_data(client, reg->reg);
732 if (ret < 0)
733 return ret;
734
735 reg->val = (__u64)ret;
736
737 return 0;
738 }
739
740 static int ov772x_s_register(struct v4l2_subdev *sd,
741 struct v4l2_dbg_register *reg)
742 {
743 struct i2c_client *client = sd->priv;
744
745 if (reg->reg > 0xff ||
746 reg->val > 0xff)
747 return -EINVAL;
748
749 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
750 }
751 #endif
752
753 static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
754 {
755 __u32 diff;
756 const struct ov772x_win_size *win;
757
758 /* default is QVGA */
759 diff = abs(width - ov772x_win_qvga.width) +
760 abs(height - ov772x_win_qvga.height);
761 win = &ov772x_win_qvga;
762
763 /* VGA */
764 if (diff >
765 abs(width - ov772x_win_vga.width) +
766 abs(height - ov772x_win_vga.height))
767 win = &ov772x_win_vga;
768
769 return win;
770 }
771
772 static int ov772x_set_params(struct i2c_client *client,
773 u32 width, u32 height, u32 pixfmt)
774 {
775 struct ov772x_priv *priv = to_ov772x(client);
776 int ret = -EINVAL;
777 u8 val;
778 int i;
779
780 /*
781 * select format
782 */
783 priv->fmt = NULL;
784 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
785 if (pixfmt == ov772x_cfmts[i].fourcc) {
786 priv->fmt = ov772x_cfmts + i;
787 break;
788 }
789 }
790 if (!priv->fmt)
791 goto ov772x_set_fmt_error;
792
793 /*
794 * select win
795 */
796 priv->win = ov772x_select_win(width, height);
797
798 /*
799 * reset hardware
800 */
801 ov772x_reset(client);
802
803 /*
804 * Edge Ctrl
805 */
806 if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
807
808 /*
809 * Manual Edge Control Mode
810 *
811 * Edge auto strength bit is set by default.
812 * Remove it when manual mode.
813 */
814
815 ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00);
816 if (ret < 0)
817 goto ov772x_set_fmt_error;
818
819 ret = ov772x_mask_set(client,
820 EDGE_TRSHLD, EDGE_THRESHOLD_MASK,
821 priv->info->edgectrl.threshold);
822 if (ret < 0)
823 goto ov772x_set_fmt_error;
824
825 ret = ov772x_mask_set(client,
826 EDGE_STRNGT, EDGE_STRENGTH_MASK,
827 priv->info->edgectrl.strength);
828 if (ret < 0)
829 goto ov772x_set_fmt_error;
830
831 } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
832 /*
833 * Auto Edge Control Mode
834 *
835 * set upper and lower limit
836 */
837 ret = ov772x_mask_set(client,
838 EDGE_UPPER, EDGE_UPPER_MASK,
839 priv->info->edgectrl.upper);
840 if (ret < 0)
841 goto ov772x_set_fmt_error;
842
843 ret = ov772x_mask_set(client,
844 EDGE_LOWER, EDGE_LOWER_MASK,
845 priv->info->edgectrl.lower);
846 if (ret < 0)
847 goto ov772x_set_fmt_error;
848 }
849
850 /*
851 * set size format
852 */
853 ret = ov772x_write_array(client, priv->win->regs);
854 if (ret < 0)
855 goto ov772x_set_fmt_error;
856
857 /*
858 * set DSP_CTRL3
859 */
860 val = priv->fmt->dsp3;
861 if (val) {
862 ret = ov772x_mask_set(client,
863 DSP_CTRL3, UV_MASK, val);
864 if (ret < 0)
865 goto ov772x_set_fmt_error;
866 }
867
868 /*
869 * set COM3
870 */
871 val = priv->fmt->com3;
872 if (priv->info->flags & OV772X_FLAG_VFLIP)
873 val |= VFLIP_IMG;
874 if (priv->info->flags & OV772X_FLAG_HFLIP)
875 val |= HFLIP_IMG;
876 if (priv->flag_vflip)
877 val ^= VFLIP_IMG;
878 if (priv->flag_hflip)
879 val ^= HFLIP_IMG;
880
881 ret = ov772x_mask_set(client,
882 COM3, SWAP_MASK | IMG_MASK, val);
883 if (ret < 0)
884 goto ov772x_set_fmt_error;
885
886 /*
887 * set COM7
888 */
889 val = priv->win->com7_bit | priv->fmt->com7;
890 ret = ov772x_mask_set(client,
891 COM7, (SLCT_MASK | FMT_MASK | OFMT_MASK),
892 val);
893 if (ret < 0)
894 goto ov772x_set_fmt_error;
895
896 return ret;
897
898 ov772x_set_fmt_error:
899
900 ov772x_reset(client);
901 priv->win = NULL;
902 priv->fmt = NULL;
903
904 return ret;
905 }
906
907 static int ov772x_set_crop(struct soc_camera_device *icd,
908 struct v4l2_rect *rect)
909 {
910 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
911 struct ov772x_priv *priv = to_ov772x(client);
912
913 if (!priv->fmt)
914 return -EINVAL;
915
916 return ov772x_set_params(client, rect->width, rect->height,
917 priv->fmt->fourcc);
918 }
919
920 static int ov772x_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *f)
921 {
922 struct i2c_client *client = sd->priv;
923 struct v4l2_pix_format *pix = &f->fmt.pix;
924
925 return ov772x_set_params(client, pix->width, pix->height,
926 pix->pixelformat);
927 }
928
929 static int ov772x_try_fmt(struct v4l2_subdev *sd,
930 struct v4l2_format *f)
931 {
932 struct v4l2_pix_format *pix = &f->fmt.pix;
933 const struct ov772x_win_size *win;
934
935 /*
936 * select suitable win
937 */
938 win = ov772x_select_win(pix->width, pix->height);
939
940 pix->width = win->width;
941 pix->height = win->height;
942 pix->field = V4L2_FIELD_NONE;
943
944 return 0;
945 }
946
947 static int ov772x_video_probe(struct soc_camera_device *icd,
948 struct i2c_client *client)
949 {
950 struct ov772x_priv *priv = to_ov772x(client);
951 u8 pid, ver;
952 const char *devname;
953
954 /*
955 * We must have a parent by now. And it cannot be a wrong one.
956 * So this entire test is completely redundant.
957 */
958 if (!icd->dev.parent ||
959 to_soc_camera_host(icd->dev.parent)->nr != icd->iface)
960 return -ENODEV;
961
962 /*
963 * ov772x only use 8 or 10 bit bus width
964 */
965 if (SOCAM_DATAWIDTH_10 != priv->info->buswidth &&
966 SOCAM_DATAWIDTH_8 != priv->info->buswidth) {
967 dev_err(&icd->dev, "bus width error\n");
968 return -ENODEV;
969 }
970
971 icd->formats = ov772x_fmt_lists;
972 icd->num_formats = ARRAY_SIZE(ov772x_fmt_lists);
973
974 /*
975 * check and show product ID and manufacturer ID
976 */
977 pid = i2c_smbus_read_byte_data(client, PID);
978 ver = i2c_smbus_read_byte_data(client, VER);
979
980 switch (VERSION(pid, ver)) {
981 case OV7720:
982 devname = "ov7720";
983 priv->model = V4L2_IDENT_OV7720;
984 break;
985 case OV7725:
986 devname = "ov7725";
987 priv->model = V4L2_IDENT_OV7725;
988 break;
989 default:
990 dev_err(&icd->dev,
991 "Product ID error %x:%x\n", pid, ver);
992 return -ENODEV;
993 }
994
995 dev_info(&icd->dev,
996 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
997 devname,
998 pid,
999 ver,
1000 i2c_smbus_read_byte_data(client, MIDH),
1001 i2c_smbus_read_byte_data(client, MIDL));
1002
1003 return 0;
1004 }
1005
1006 static struct soc_camera_ops ov772x_ops = {
1007 .set_crop = ov772x_set_crop,
1008 .set_bus_param = ov772x_set_bus_param,
1009 .query_bus_param = ov772x_query_bus_param,
1010 .controls = ov772x_controls,
1011 .num_controls = ARRAY_SIZE(ov772x_controls),
1012 };
1013
1014 static struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
1015 .g_ctrl = ov772x_g_ctrl,
1016 .s_ctrl = ov772x_s_ctrl,
1017 .g_chip_ident = ov772x_g_chip_ident,
1018 #ifdef CONFIG_VIDEO_ADV_DEBUG
1019 .g_register = ov772x_g_register,
1020 .s_register = ov772x_s_register,
1021 #endif
1022 };
1023
1024 static struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
1025 .s_stream = ov772x_s_stream,
1026 .s_fmt = ov772x_s_fmt,
1027 .try_fmt = ov772x_try_fmt,
1028 };
1029
1030 static struct v4l2_subdev_ops ov772x_subdev_ops = {
1031 .core = &ov772x_subdev_core_ops,
1032 .video = &ov772x_subdev_video_ops,
1033 };
1034
1035 /*
1036 * i2c_driver function
1037 */
1038
1039 static int ov772x_probe(struct i2c_client *client,
1040 const struct i2c_device_id *did)
1041 {
1042 struct ov772x_priv *priv;
1043 struct ov772x_camera_info *info;
1044 struct soc_camera_device *icd = client->dev.platform_data;
1045 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1046 struct soc_camera_link *icl;
1047 int ret;
1048
1049 if (!icd) {
1050 dev_err(&client->dev, "OV772X: missing soc-camera data!\n");
1051 return -EINVAL;
1052 }
1053
1054 icl = to_soc_camera_link(icd);
1055 if (!icl)
1056 return -EINVAL;
1057
1058 info = container_of(icl, struct ov772x_camera_info, link);
1059
1060 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1061 dev_err(&adapter->dev,
1062 "I2C-Adapter doesn't support "
1063 "I2C_FUNC_SMBUS_BYTE_DATA\n");
1064 return -EIO;
1065 }
1066
1067 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1068 if (!priv)
1069 return -ENOMEM;
1070
1071 priv->info = info;
1072
1073 v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
1074
1075 icd->ops = &ov772x_ops;
1076 icd->width_max = MAX_WIDTH;
1077 icd->height_max = MAX_HEIGHT;
1078
1079 ret = ov772x_video_probe(icd, client);
1080 if (ret) {
1081 icd->ops = NULL;
1082 i2c_set_clientdata(client, NULL);
1083 kfree(priv);
1084 }
1085
1086 return ret;
1087 }
1088
1089 static int ov772x_remove(struct i2c_client *client)
1090 {
1091 struct ov772x_priv *priv = to_ov772x(client);
1092 struct soc_camera_device *icd = client->dev.platform_data;
1093
1094 icd->ops = NULL;
1095 i2c_set_clientdata(client, NULL);
1096 kfree(priv);
1097 return 0;
1098 }
1099
1100 static const struct i2c_device_id ov772x_id[] = {
1101 { "ov772x", 0 },
1102 { }
1103 };
1104 MODULE_DEVICE_TABLE(i2c, ov772x_id);
1105
1106 static struct i2c_driver ov772x_i2c_driver = {
1107 .driver = {
1108 .name = "ov772x",
1109 },
1110 .probe = ov772x_probe,
1111 .remove = ov772x_remove,
1112 .id_table = ov772x_id,
1113 };
1114
1115 /*
1116 * module function
1117 */
1118
1119 static int __init ov772x_module_init(void)
1120 {
1121 return i2c_add_driver(&ov772x_i2c_driver);
1122 }
1123
1124 static void __exit ov772x_module_exit(void)
1125 {
1126 i2c_del_driver(&ov772x_i2c_driver);
1127 }
1128
1129 module_init(ov772x_module_init);
1130 module_exit(ov772x_module_exit);
1131
1132 MODULE_DESCRIPTION("SoC Camera driver for ov772x");
1133 MODULE_AUTHOR("Kuninori Morimoto");
1134 MODULE_LICENSE("GPL v2");
AMDTP streaming driver for the Linux FireWire stack (Juju)