1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
4 ;; 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
6 ;; Author: Michael McNamara (mac@verilog.com)
7 ;; http://www.verilog.com
9 ;; AUTO features, signal, modsig; by: Wilson Snyder
10 ;; (wsnyder@wsnyder.org)
11 ;; http://www.veripool.org
12 ;; Keywords: languages
14 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
15 ;; file on 19/3/2008, and the maintainer agreed that when a bug is
16 ;; filed in the Emacs bug reporting system against this file, a copy
17 ;; of the bug report be sent to the maintainer's email address.
19 ;; This code supports Emacs 21.1 and later
20 ;; And XEmacs 21.1 and later
21 ;; Please do not make changes that break Emacs 21. Thanks!
25 ;; This file is part of GNU Emacs.
27 ;; GNU Emacs is free software: you can redistribute it and/or modify
28 ;; it under the terms of the GNU General Public License as published by
29 ;; the Free Software Foundation, either version 3 of the License, or
30 ;; (at your option) any later version.
32 ;; GNU Emacs is distributed in the hope that it will be useful,
33 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
34 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 ;; GNU General Public License for more details.
37 ;; You should have received a copy of the GNU General Public License
38 ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
42 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of Emacs
47 ;; A major mode for editing Verilog HDL source code. When you have
48 ;; entered Verilog mode, you may get more info by pressing C-h m. You
49 ;; may also get online help describing various functions by: C-h f
50 ;; <Name of function you want described>
52 ;; KNOWN BUGS / BUG REPORTS
53 ;; =======================
55 ;; Verilog is a rapidly evolving language, and hence this mode is
56 ;; under continuous development. Hence this is beta code, and likely
57 ;; has bugs. Please report any issues to the issue tracker at
58 ;; http://www.veripool.org/verilog-mode
59 ;; Please use verilog-submit-bug-report to submit a report; type C-c
60 ;; C-b to invoke this and as a result I will have a much easier time
61 ;; of reproducing the bug you find, and hence fixing it.
63 ;; INSTALLING THE MODE
64 ;; ===================
66 ;; An older version of this mode may be already installed as a part of
67 ;; your environment, and one method of updating would be to update
68 ;; your Emacs environment. Sometimes this is difficult for local
69 ;; political/control reasons, and hence you can always install a
70 ;; private copy (or even a shared copy) which overrides the system
73 ;; You can get step by step help in installing this file by going to
74 ;; <http://www.verilog.com/emacs_install.html>
76 ;; The short list of installation instructions are: To set up
77 ;; automatic Verilog mode, put this file in your load path, and put
78 ;; the following in code (please un comment it first!) in your
79 ;; .emacs, or in your site's site-load.el
81 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
82 ; (add-to-list 'auto-mode-alist '("\\.[ds]?v\\'" . verilog-mode))
84 ;; If you want to customize Verilog mode to fit your needs better,
85 ;; you may add these lines (the values of the variables presented
86 ;; here are the defaults). Note also that if you use an Emacs that
87 ;; supports custom, it's probably better to use the custom menu to
90 ;; Be sure to examine at the help for verilog-auto, and the other
91 ;; verilog-auto-* functions for some major coding time savers.
93 ; ;; User customization for Verilog mode
94 ; (setq verilog-indent-level 3
95 ; verilog-indent-level-module 3
96 ; verilog-indent-level-declaration 3
97 ; verilog-indent-level-behavioral 3
98 ; verilog-indent-level-directive 1
99 ; verilog-case-indent 2
100 ; verilog-auto-newline t
101 ; verilog-auto-indent-on-newline t
102 ; verilog-tab-always-indent t
103 ; verilog-auto-endcomments t
104 ; verilog-minimum-comment-distance 40
105 ; verilog-indent-begin-after-if t
106 ; verilog-auto-lineup 'declarations
107 ; verilog-highlight-p1800-keywords nil
108 ; verilog-linter "my_lint_shell_command"
115 ;; See commit history at http://www.veripool.org/verilog-mode.html
116 ;; (This section is required to appease checkdoc.)
120 ;; This variable will always hold the version number of the mode
121 (defconst verilog-mode-version
"552"
122 "Version of this Verilog mode.")
123 (defconst verilog-mode-release-date
"2009-11-25-GNU"
124 "Release date of this Verilog mode.")
125 (defconst verilog-mode-release-emacs t
126 "If non-nil, this version of Verilog mode was released with Emacs itself.")
128 (defun verilog-version ()
129 "Inform caller of the version of this file."
131 (message "Using verilog-mode version %s" verilog-mode-version
))
133 ;; Insure we have certain packages, and deal with it if we don't
134 ;; Be sure to note which Emacs flavor and version added each feature.
136 ;; Provide stuff if we are XEmacs
137 (when (featurep 'xemacs
)
142 (require 'regexp-opt
)
144 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
151 (defmacro when
(cond &rest body
)
152 (list 'if cond
(cons 'progn body
))))
155 (if (fboundp 'unless
)
157 (defmacro unless
(cond &rest body
)
158 (cons 'if
(cons cond
(cons nil body
)))))
161 (if (fboundp 'store-match-data
)
163 (defmacro store-match-data
(&rest args
) nil
))
166 (if (fboundp 'char-before
)
168 (defmacro char-before
(&rest body
)
169 (char-after (1- (point)))))
175 (if (fboundp 'match-string-no-properties
)
177 (defsubst match-string-no-properties
(num &optional string
)
178 "Return string of text matched by last search, without text properties.
179 NUM specifies which parenthesized expression in the last regexp.
180 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
181 Zero means the entire text matched by the whole regexp or whole string.
182 STRING should be given if the last search was by `string-match' on STRING."
183 (if (match-beginning num
)
187 (match-beginning num
) (match-end num
))))
188 (set-text-properties 0 (length result
) nil result
)
190 (buffer-substring-no-properties (match-beginning num
)
195 (if (and (featurep 'custom
) (fboundp 'custom-declare-variable
))
196 nil
;; We've got what we needed
197 ;; We have the old custom-library, hack around it!
198 (defmacro defgroup
(&rest args
) nil
)
199 (defmacro customize
(&rest args
)
201 "Sorry, Customize is not available with this version of Emacs"))
202 (defmacro defcustom
(var value doc
&rest args
)
203 `(defvar ,var
,value
,doc
))
205 (if (fboundp 'defface
)
207 (defmacro defface
(var values doc
&rest args
)
211 (if (and (featurep 'custom
) (fboundp 'customize-group
))
212 nil
;; We've got what we needed
213 ;; We have an intermediate custom-library, hack around it!
214 (defmacro customize-group
(var &rest args
)
217 ;; OK, do this stuff if we are NOT XEmacs:
218 (unless (featurep 'xemacs
)
219 (unless (fboundp 'region-active-p
)
220 (defmacro region-active-p
()
221 `(and transient-mark-mode mark-active
))))
224 ;; Provide a regular expression optimization routine, using regexp-opt
225 ;; if provided by the user's elisp libraries
227 ;; The below were disabled when GNU Emacs 22 was released;
228 ;; perhaps some still need to be there to support Emacs 21.
229 (if (featurep 'xemacs
)
230 (if (fboundp 'regexp-opt
)
231 ;; regexp-opt is defined, does it take 3 or 2 arguments?
232 (if (fboundp 'function-max-args
)
233 (let ((args (function-max-args `regexp-opt
)))
235 ((eq args
3) ;; It takes 3
236 (condition-case nil
; Hide this defun from emacses
237 ;with just a two input regexp
238 (defun verilog-regexp-opt (a b
)
239 "Deal with differing number of required arguments for `regexp-opt'.
240 Call 'regexp-opt' on A and B."
244 ((eq args
2) ;; It takes 2
245 (defun verilog-regexp-opt (a b
)
246 "Call 'regexp-opt' on A and B."
250 ;; We can't tell; assume it takes 2
251 (defun verilog-regexp-opt (a b
)
252 "Call 'regexp-opt' on A and B."
255 ;; There is no regexp-opt, provide our own
256 (defun verilog-regexp-opt (strings &optional paren shy
)
257 (let ((open (if paren
"\\(" "")) (close (if paren
"\\)" "")))
258 (concat open
(mapconcat 'regexp-quote strings
"\\|") close
)))
261 (defalias 'verilog-regexp-opt
'regexp-opt
)))
264 (defun verilog-regexp-words (a)
265 "Call 'regexp-opt' with word delimiters for the words A."
266 (concat "\\<" (verilog-regexp-opt a t
) "\\>")))
268 (defun verilog-easy-menu-filter (menu)
269 "Filter `easy-menu-define' MENU to support new features."
270 (cond ((not (featurep 'xemacs
))
271 menu
) ;; GNU Emacs - passthru
272 ;; Xemacs doesn't support :help. Strip it.
273 ;; Recursively filter the a submenu
275 (mapcar 'verilog-easy-menu-filter menu
))
276 ;; Look for [:help "blah"] and remove
278 (let ((i 0) (out []))
279 (while (< i
(length menu
))
280 (if (equal `:help
(aref menu i
))
282 (setq out
(vconcat out
(vector (aref menu i
)))
285 (t menu
))) ;; Default - ok
286 ;;(verilog-easy-menu-filter
287 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
288 ;; "----" ["MB" nil :help "Help MB"]))
290 (defun verilog-customize ()
291 "Customize variables and other settings used by Verilog-Mode."
293 (customize-group 'verilog-mode
))
295 (defun verilog-font-customize ()
296 "Customize fonts used by Verilog-Mode."
298 (if (fboundp 'customize-apropos
)
299 (customize-apropos "font-lock-*" 'faces
)))
301 (defun verilog-booleanp (value)
302 "Return t if VALUE is boolean.
303 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
304 This function may be removed when Emacs 21 is no longer supported."
305 (or (equal value t
) (equal value nil
)))
307 (defun verilog-insert-last-command-event ()
308 "Insert the `last-command-event'."
309 (insert (if (featurep 'xemacs
)
310 ;; XEmacs 21.5 doesn't like last-command-event
312 ;; And GNU Emacs 22 has obsoleted last-command-char
313 last-command-event
)))
315 (defalias 'verilog-syntax-ppss
316 (if (fboundp 'syntax-ppss
) 'syntax-ppss
317 (lambda (&optional pos
) (parse-partial-sexp (point-min) (or pos
(point))))))
319 (defgroup verilog-mode nil
320 "Facilitates easy editing of Verilog source text."
324 ; (defgroup verilog-mode-fonts nil
325 ; "Facilitates easy customization fonts used in Verilog source text"
326 ; :link '(customize-apropos "font-lock-*" 'faces)
327 ; :group 'verilog-mode)
329 (defgroup verilog-mode-indent nil
330 "Customize indentation and highlighting of Verilog source text."
331 :group
'verilog-mode
)
333 (defgroup verilog-mode-actions nil
334 "Customize actions on Verilog source text."
335 :group
'verilog-mode
)
337 (defgroup verilog-mode-auto nil
338 "Customize AUTO actions when expanding Verilog source text."
339 :group
'verilog-mode
)
341 (defcustom verilog-linter
342 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
343 "*Unix program and arguments to call to run a lint checker on Verilog source.
344 Depending on the `verilog-set-compile-command', this may be invoked when
345 you type \\[compile]. When the compile completes, \\[next-error] will take
346 you to the next lint error."
348 :group
'verilog-mode-actions
)
349 ;; We don't mark it safe, as it's used as a shell command
351 (defcustom verilog-coverage
352 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
353 "*Program and arguments to use to annotate for coverage Verilog source.
354 Depending on the `verilog-set-compile-command', this may be invoked when
355 you type \\[compile]. When the compile completes, \\[next-error] will take
356 you to the next lint error."
358 :group
'verilog-mode-actions
)
359 ;; We don't mark it safe, as it's used as a shell command
361 (defcustom verilog-simulator
362 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
363 "*Program and arguments to use to interpret Verilog source.
364 Depending on the `verilog-set-compile-command', this may be invoked when
365 you type \\[compile]. When the compile completes, \\[next-error] will take
366 you to the next lint error."
368 :group
'verilog-mode-actions
)
369 ;; We don't mark it safe, as it's used as a shell command
371 (defcustom verilog-compiler
372 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
373 "*Program and arguments to use to compile Verilog source.
374 Depending on the `verilog-set-compile-command', this may be invoked when
375 you type \\[compile]. When the compile completes, \\[next-error] will take
376 you to the next lint error."
378 :group
'verilog-mode-actions
)
379 ;; We don't mark it safe, as it's used as a shell command
381 (defvar verilog-tool
'verilog-linter
382 "Which tool to use for building compiler-command.
383 Either nil, `verilog-linter, `verilog-coverage, `verilog-simulator, or
384 `verilog-compiler. Alternatively use the \"Choose Compilation Action\"
385 menu. See `verilog-set-compile-command' for more information.")
387 (defcustom verilog-highlight-translate-off nil
388 "*Non-nil means background-highlight code excluded from translation.
389 That is, all code between \"// synopsys translate_off\" and
390 \"// synopsys translate_on\" is highlighted using a different background color
391 \(face `verilog-font-lock-translate-off-face').
393 Note: This will slow down on-the-fly fontification (and thus editing).
395 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
396 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
398 :group
'verilog-mode-indent
)
399 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
400 (put 'verilog-highlight-translate-off
'safe-local-variable
'verilog-booleanp
)
402 (defcustom verilog-auto-lineup
'declarations
403 "*Type of statements to lineup across multiple lines.
404 If 'all' is selected, then all line ups described below are done.
406 If 'declaration', then just declarations are lined up with any
407 preceding declarations, taking into account widths and the like,
408 so or example the code:
415 If 'assignment', then assignments are lined up with any preceding
416 assignments, so for example the code
417 a_long_variable <= b + c;
420 a_long_variable <= b + c;
423 In order to speed up editing, large blocks of statements are lined up
424 only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
425 are lineup only when \\[verilog-pretty-declarations] is typed."
427 :type
'(radio (const :tag
"Line up Assignments and Declarations" all
)
428 (const :tag
"Line up Assignment statements" assignments
)
429 (const :tag
"Line up Declarartions" declarations
)
430 (function :tag
"Other"))
431 :group
'verilog-mode-indent
)
433 (defcustom verilog-indent-level
3
434 "*Indentation of Verilog statements with respect to containing block."
435 :group
'verilog-mode-indent
437 (put 'verilog-indent-level
'safe-local-variable
'integerp
)
439 (defcustom verilog-indent-level-module
3
440 "*Indentation of Module level Verilog statements (eg always, initial).
441 Set to 0 to get initial and always statements lined up on the left side of
443 :group
'verilog-mode-indent
445 (put 'verilog-indent-level-module
'safe-local-variable
'integerp
)
447 (defcustom verilog-indent-level-declaration
3
448 "*Indentation of declarations with respect to containing block.
449 Set to 0 to get them list right under containing block."
450 :group
'verilog-mode-indent
452 (put 'verilog-indent-level-declaration
'safe-local-variable
'integerp
)
454 (defcustom verilog-indent-declaration-macros nil
455 "*How to treat macro expansions in a declaration.
460 If non nil, treat as:
464 :group
'verilog-mode-indent
466 (put 'verilog-indent-declaration-macros
'safe-local-variable
'verilog-booleanp
)
468 (defcustom verilog-indent-lists t
469 "*How to treat indenting items in a list.
470 If t (the default), indent as:
471 always @( posedge a or
475 always @( posedge a or
477 :group
'verilog-mode-indent
479 (put 'verilog-indent-lists
'safe-local-variable
'verilog-booleanp
)
481 (defcustom verilog-indent-level-behavioral
3
482 "*Absolute indentation of first begin in a task or function block.
483 Set to 0 to get such code to start at the left side of the screen."
484 :group
'verilog-mode-indent
486 (put 'verilog-indent-level-behavioral
'safe-local-variable
'integerp
)
488 (defcustom verilog-indent-level-directive
1
489 "*Indentation to add to each level of `ifdef declarations.
490 Set to 0 to have all directives start at the left side of the screen."
491 :group
'verilog-mode-indent
493 (put 'verilog-indent-level-directive
'safe-local-variable
'integerp
)
495 (defcustom verilog-cexp-indent
2
496 "*Indentation of Verilog statements split across lines."
497 :group
'verilog-mode-indent
499 (put 'verilog-cexp-indent
'safe-local-variable
'integerp
)
501 (defcustom verilog-case-indent
2
502 "*Indentation for case statements."
503 :group
'verilog-mode-indent
505 (put 'verilog-case-indent
'safe-local-variable
'integerp
)
507 (defcustom verilog-auto-newline t
508 "*True means automatically newline after semicolons."
509 :group
'verilog-mode-indent
511 (put 'verilog-auto-newline
'safe-local-variable
'verilog-booleanp
)
513 (defcustom verilog-auto-indent-on-newline t
514 "*True means automatically indent line after newline."
515 :group
'verilog-mode-indent
517 (put 'verilog-auto-indent-on-newline
'safe-local-variable
'verilog-booleanp
)
519 (defcustom verilog-tab-always-indent t
520 "*True means TAB should always re-indent the current line.
521 A nil value means TAB will only reindent when at the beginning of the line."
522 :group
'verilog-mode-indent
524 (put 'verilog-tab-always-indent
'safe-local-variable
'verilog-booleanp
)
526 (defcustom verilog-tab-to-comment nil
527 "*True means TAB moves to the right hand column in preparation for a comment."
528 :group
'verilog-mode-actions
530 (put 'verilog-tab-to-comment
'safe-local-variable
'verilog-booleanp
)
532 (defcustom verilog-indent-begin-after-if t
533 "*If true, indent begin statements following if, else, while, for and repeat.
534 Otherwise, line them up."
535 :group
'verilog-mode-indent
537 (put 'verilog-indent-begin-after-if
'safe-local-variable
'verilog-booleanp
)
540 (defcustom verilog-align-ifelse nil
541 "*If true, align `else' under matching `if'.
542 Otherwise else is lined up with first character on line holding matching if."
543 :group
'verilog-mode-indent
545 (put 'verilog-align-ifelse
'safe-local-variable
'verilog-booleanp
)
547 (defcustom verilog-minimum-comment-distance
10
548 "*Minimum distance (in lines) between begin and end required before a comment.
549 Setting this variable to zero results in every end acquiring a comment; the
550 default avoids too many redundant comments in tight quarters."
551 :group
'verilog-mode-indent
553 (put 'verilog-minimum-comment-distance
'safe-local-variable
'integerp
)
555 (defcustom verilog-highlight-p1800-keywords nil
556 "*True means highlight words newly reserved by IEEE-1800.
557 These will appear in `verilog-font-lock-p1800-face' in order to gently
558 suggest changing where these words are used as variables to something else.
559 A nil value means highlight these words as appropriate for the SystemVerilog
560 IEEE-1800 standard. Note that changing this will require restarting Emacs
561 to see the effect as font color choices are cached by Emacs."
562 :group
'verilog-mode-indent
564 (put 'verilog-highlight-p1800-keywords
'safe-local-variable
'verilog-booleanp
)
566 (defcustom verilog-highlight-grouping-keywords nil
567 "*True means highlight grouping keywords 'begin' and 'end' more dramatically.
568 If false, these words are in the `font-lock-type-face'; if True then they are in
569 `verilog-font-lock-ams-face'. Some find that special highlighting on these
570 grouping constructs allow the structure of the code to be understood at a glance."
571 :group
'verilog-mode-indent
573 (put 'verilog-highlight-grouping-keywords
'safe-local-variable
'verilog-booleanp
)
575 (defcustom verilog-auto-endcomments t
576 "*True means insert a comment /* ... */ after 'end's.
577 The name of the function or case will be set between the braces."
578 :group
'verilog-mode-actions
580 (put 'verilog-auto-endcomments
'safe-local-variable
'verilog-booleanp
)
582 (defcustom verilog-auto-ignore-concat nil
583 "*True means ignore signals in {...} concatenations for AUTOWIRE etc.
584 This will exclude signals referenced as pin connections in {...}
585 from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
586 for backward compatibility only and not set in new designs; it
587 may be removed in future versions."
588 :group
'verilog-mode-actions
590 (put 'verilog-auto-ignore-concat
'safe-local-variable
'verilog-booleanp
)
592 (defcustom verilog-auto-read-includes nil
593 "*True means to automatically read includes before AUTOs.
594 This will do a `verilog-read-defines' and `verilog-read-includes' before
595 each AUTO expansion. This makes it easier to embed defines and includes,
596 but can result in very slow reading times if there are many or large
598 :group
'verilog-mode-actions
600 (put 'verilog-auto-read-includes
'safe-local-variable
'verilog-booleanp
)
602 (defcustom verilog-auto-save-policy nil
603 "*Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
604 A value of `force' will always do a \\[verilog-auto] automatically if
605 needed on every save. A value of `detect' will do \\[verilog-auto]
606 automatically when it thinks necessary. A value of `ask' will query the
607 user when it thinks updating is needed.
609 You should not rely on the 'ask or 'detect policies, they are safeguards
610 only. They do not detect when AUTOINSTs need to be updated because a
611 sub-module's port list has changed."
612 :group
'verilog-mode-actions
613 :type
'(choice (const nil
) (const ask
) (const detect
) (const force
)))
615 (defcustom verilog-auto-star-expand t
616 "*Non-nil indicates to expand a SystemVerilog .* instance ports.
617 They will be expanded in the same way as if there was a AUTOINST in the
618 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
619 :group
'verilog-mode-actions
621 (put 'verilog-auto-star-expand
'safe-local-variable
'verilog-booleanp
)
623 (defcustom verilog-auto-star-save nil
624 "*Non-nil indicates to save to disk SystemVerilog .* instance expansions.
625 A nil value indicates direct connections will be removed before saving.
626 Only meaningful to those created due to `verilog-auto-star-expand' being set.
628 Instead of setting this, you may want to use /*AUTOINST*/, which will
630 :group
'verilog-mode-actions
632 (put 'verilog-auto-star-save
'safe-local-variable
'verilog-booleanp
)
634 (defvar verilog-auto-update-tick nil
635 "Modification tick at which autos were last performed.")
637 (defvar verilog-auto-last-file-locals nil
638 "Text from file-local-variables during last evaluation.")
642 (defvar verilog-error-regexp-added nil
)
643 ; List of regexps for Verilog compilers, like verilint. See compilation-error-regexp-alist
644 ; for the formatting.
645 ; Here is the version for Emacs 22:
646 (defvar verilog-error-regexp-emacs-alist
649 "\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
651 "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
653 ".*\\*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)" 1 2)
655 "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
657 "\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
660 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
661 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
663 "\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
665 "\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
667 "Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
669 "\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
671 "syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
673 "%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
675 "In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):
679 \\(Warning\\|Error\\|Failure\\)" 1 2)
681 ;; And the version for XEmacs:
682 (defvar verilog-error-regexp-xemacs-alist
684 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
685 ("\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
687 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
688 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
690 ; Error! in file /homes/mac/Axis/Xsim/test.v at line 13 [OBJ_NOT_DECLARED]
691 ("\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
693 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
694 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
695 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
696 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
698 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
700 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
701 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 2) ; vxl
702 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 2)
704 (".*\\*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 2)
706 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 2)
710 (defvar verilog-error-font-lock-keywords
712 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t
)
713 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t
)
715 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t
)
716 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t
)
719 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
720 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
722 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
723 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
725 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t
)
726 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t
)
728 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t
)
729 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t
)
731 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
732 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
734 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
735 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t
)
737 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t
)
738 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
740 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
741 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
743 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 bold t
)
744 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 2 bold t
)
746 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 bold t
)
747 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 2 bold t
)
749 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 bold t
)
750 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t
)
752 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 bold t
)
753 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 2 bold t
)
755 "*Keywords to also highlight in Verilog *compilation* buffers.")
757 (defcustom verilog-library-flags
'("")
758 "*List of standard Verilog arguments to use for /*AUTOINST*/.
759 These arguments are used to find files for `verilog-auto', and match
760 the flags accepted by a standard Verilog-XL simulator.
762 -f filename Reads more `verilog-library-flags' from the filename.
763 +incdir+dir Adds the directory to `verilog-library-directories'.
764 -Idir Adds the directory to `verilog-library-directories'.
765 -y dir Adds the directory to `verilog-library-directories'.
766 +libext+.v Adds the extensions to `verilog-library-extensions'.
767 -v filename Adds the filename to `verilog-library-files'.
769 filename Adds the filename to `verilog-library-files'.
770 This is not recommended, -v is a better choice.
772 You might want these defined in each file; put at the *END* of your file
776 // verilog-library-flags:(\"-y dir -y otherdir\")
779 Verilog-mode attempts to detect changes to this local variable, but they
780 are only insured to be correct when the file is first visited. Thus if you
781 have problems, use \\[find-alternate-file] RET to have these take effect.
783 See also the variables mentioned above."
784 :group
'verilog-mode-auto
785 :type
'(repeat string
))
786 (put 'verilog-library-flags
'safe-local-variable
'listp
)
788 (defcustom verilog-library-directories
'(".")
789 "*List of directories when looking for files for /*AUTOINST*/.
790 The directory may be relative to the current file, or absolute.
791 Environment variables are also expanded in the directory names.
792 Having at least the current directory is a good idea.
794 You might want these defined in each file; put at the *END* of your file
798 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
801 Verilog-mode attempts to detect changes to this local variable, but they
802 are only insured to be correct when the file is first visited. Thus if you
803 have problems, use \\[find-alternate-file] RET to have these take effect.
805 See also `verilog-library-flags', `verilog-library-files'
806 and `verilog-library-extensions'."
807 :group
'verilog-mode-auto
808 :type
'(repeat file
))
809 (put 'verilog-library-directories
'safe-local-variable
'listp
)
811 (defcustom verilog-library-files
'()
812 "*List of files to search for modules.
813 AUTOINST will use this when it needs to resolve a module name.
814 This is a complete path, usually to a technology file with many standard
817 You might want these defined in each file; put at the *END* of your file
821 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
824 Verilog-mode attempts to detect changes to this local variable, but they
825 are only insured to be correct when the file is first visited. Thus if you
826 have problems, use \\[find-alternate-file] RET to have these take effect.
828 See also `verilog-library-flags', `verilog-library-directories'."
829 :group
'verilog-mode-auto
830 :type
'(repeat directory
))
831 (put 'verilog-library-files
'safe-local-variable
'listp
)
833 (defcustom verilog-library-extensions
'(".v" ".sv")
834 "*List of extensions to use when looking for files for /*AUTOINST*/.
835 See also `verilog-library-flags', `verilog-library-directories'."
836 :type
'(repeat string
)
837 :group
'verilog-mode-auto
)
838 (put 'verilog-library-extensions
'safe-local-variable
'listp
)
840 (defcustom verilog-active-low-regexp nil
841 "*If set, treat signals matching this regexp as active low.
842 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
843 you will probably also need `verilog-auto-reset-widths' set."
844 :group
'verilog-mode-auto
846 (put 'verilog-active-low-regexp
'safe-local-variable
'stringp
)
848 (defcustom verilog-auto-sense-include-inputs nil
849 "*If true, AUTOSENSE should include all inputs.
850 If nil, only inputs that are NOT output signals in the same block are
852 :group
'verilog-mode-auto
854 (put 'verilog-auto-sense-include-inputs
'safe-local-variable
'verilog-booleanp
)
856 (defcustom verilog-auto-sense-defines-constant nil
857 "*If true, AUTOSENSE should assume all defines represent constants.
858 When true, the defines will not be included in sensitivity lists. To
859 maintain compatibility with other sites, this should be set at the bottom
860 of each Verilog file that requires it, rather than being set globally."
861 :group
'verilog-mode-auto
863 (put 'verilog-auto-sense-defines-constant
'safe-local-variable
'verilog-booleanp
)
865 (defcustom verilog-auto-reset-widths t
866 "*If true, AUTORESET should determine the width of signals.
867 This is then used to set the width of the zero (32'h0 for example). This
868 is required by some lint tools that aren't smart enough to ignore widths of
869 the constant zero. This may result in ugly code when parameters determine
870 the MSB or LSB of a signal inside an AUTORESET."
872 :group
'verilog-mode-auto
)
873 (put 'verilog-auto-reset-widths
'safe-local-variable
'verilog-booleanp
)
875 (defcustom verilog-assignment-delay
""
876 "*Text used for delays in delayed assignments. Add a trailing space if set."
877 :group
'verilog-mode-auto
879 (put 'verilog-assignment-delay
'safe-local-variable
'stringp
)
881 (defcustom verilog-auto-arg-sort nil
882 "*If set, AUTOARG signal names will be sorted, not in delaration order.
883 Declaration order is advantageous with order based instantiations
884 and is the default for backward compatibility. Sorted order
885 reduces changes when declarations are moved around in a file, and
886 it's bad practice to rely on order based instantiations anyhow."
887 :group
'verilog-mode-auto
889 (put 'verilog-auto-arg-sort
'safe-local-variable
'verilog-booleanp
)
891 (defcustom verilog-auto-inst-param-value nil
892 "*If set, AUTOINST will replace parameters with the parameter value.
893 If nil, leave parameters as symbolic names.
895 Parameters must be in Verilog 2001 format #(...), and if a parameter is not
896 listed as such there (as when the default value is acceptable), it will not
897 be replaced, and will remain symbolic.
899 For example, imagine a submodule uses parameters to declare the size of its
900 inputs. This is then used by a upper module:
902 module InstModule (o,i)
914 Note even though PARAM=10, the AUTOINST has left the parameter as a
915 symbolic name. If `verilog-auto-inst-param-value' is set, this will
924 :group
'verilog-mode-auto
926 (put 'verilog-auto-inst-param-value
'safe-local-variable
'verilog-booleanp
)
928 (defcustom verilog-auto-inst-vector t
929 "*If true, when creating default ports with AUTOINST, use bus subscripts.
930 If nil, skip the subscript when it matches the entire bus as declared in
931 the module (AUTOWIRE signals always are subscripted, you must manually
932 declare the wire to have the subscripts removed.) Setting this to nil may
933 speed up some simulators, but is less general and harder to read, so avoid."
934 :group
'verilog-mode-auto
936 (put 'verilog-auto-inst-vector
'safe-local-variable
'verilog-booleanp
)
938 (defcustom verilog-auto-inst-template-numbers nil
939 "*If true, when creating templated ports with AUTOINST, add a comment.
940 The comment will add the line number of the template that was used for that
941 port declaration. Setting this aids in debugging, but nil is suggested for
942 regular use to prevent large numbers of merge conflicts."
943 :group
'verilog-mode-auto
945 (put 'verilog-auto-inst-template-numbers
'safe-local-variable
'verilog-booleanp
)
947 (defcustom verilog-auto-inst-column
40
948 "*Indent-to column number for net name part of AUTOINST created pin."
949 :group
'verilog-mode-indent
951 (put 'verilog-auto-inst-column
'safe-local-variable
'integerp
)
953 (defcustom verilog-auto-input-ignore-regexp nil
954 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp.
955 See the \\[verilog-faq] for examples on using this."
956 :group
'verilog-mode-auto
958 (put 'verilog-auto-input-ignore-regexp
'safe-local-variable
'stringp
)
960 (defcustom verilog-auto-inout-ignore-regexp nil
961 "*If set, when creating AUTOINOUT list, ignore signals matching this regexp.
962 See the \\[verilog-faq] for examples on using this."
963 :group
'verilog-mode-auto
965 (put 'verilog-auto-inout-ignore-regexp
'safe-local-variable
'stringp
)
967 (defcustom verilog-auto-output-ignore-regexp nil
968 "*If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
969 See the \\[verilog-faq] for examples on using this."
970 :group
'verilog-mode-auto
972 (put 'verilog-auto-output-ignore-regexp
'safe-local-variable
'stringp
)
974 (defcustom verilog-auto-unused-ignore-regexp nil
975 "*If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
976 See the \\[verilog-faq] for examples on using this."
977 :group
'verilog-mode-auto
979 (put 'verilog-auto-unused-ignore-regexp
'safe-local-variable
'stringp
)
981 (defcustom verilog-typedef-regexp nil
982 "*If non-nil, regular expression that matches Verilog-2001 typedef names.
983 For example, \"_t$\" matches typedefs named with _t, as in the C language."
984 :group
'verilog-mode-auto
986 (put 'verilog-typedef-regexp
'safe-local-variable
'stringp
)
988 (defcustom verilog-mode-hook
'verilog-set-compile-command
989 "*Hook run after Verilog mode is loaded."
991 :group
'verilog-mode
)
993 (defcustom verilog-auto-hook nil
994 "*Hook run after `verilog-mode' updates AUTOs."
995 :group
'verilog-mode-auto
998 (defcustom verilog-before-auto-hook nil
999 "*Hook run before `verilog-mode' updates AUTOs."
1000 :group
'verilog-mode-auto
1003 (defcustom verilog-delete-auto-hook nil
1004 "*Hook run after `verilog-mode' deletes AUTOs."
1005 :group
'verilog-mode-auto
1008 (defcustom verilog-before-delete-auto-hook nil
1009 "*Hook run before `verilog-mode' deletes AUTOs."
1010 :group
'verilog-mode-auto
1013 (defcustom verilog-getopt-flags-hook nil
1014 "*Hook run after `verilog-getopt-flags' determines the Verilog option lists."
1015 :group
'verilog-mode-auto
1018 (defcustom verilog-before-getopt-flags-hook nil
1019 "*Hook run before `verilog-getopt-flags' determines the Verilog option lists."
1020 :group
'verilog-mode-auto
1023 (defvar verilog-imenu-generic-expression
1024 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
1025 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
1026 "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
1029 ;; provide a verilog-header function.
1030 ;; Customization variables:
1032 (defvar verilog-date-scientific-format nil
1033 "*If non-nil, dates are written in scientific format (e.g. 1997/09/17).
1034 If nil, in European format (e.g. 17.09.1997). The brain-dead American
1035 format (e.g. 09/17/1997) is not supported.")
1037 (defvar verilog-company nil
1038 "*Default name of Company for Verilog header.
1039 If set will become buffer local.")
1040 (make-variable-buffer-local 'verilog-company
)
1042 (defvar verilog-project nil
1043 "*Default name of Project for Verilog header.
1044 If set will become buffer local.")
1045 (make-variable-buffer-local 'verilog-project
)
1047 (defvar verilog-mode-map
1048 (let ((map (make-sparse-keymap)))
1049 (define-key map
";" 'electric-verilog-semi
)
1050 (define-key map
[(control 59)] 'electric-verilog-semi-with-comment
)
1051 (define-key map
":" 'electric-verilog-colon
)
1052 ;;(define-key map "=" 'electric-verilog-equal)
1053 (define-key map
"\`" 'electric-verilog-tick
)
1054 (define-key map
"\t" 'electric-verilog-tab
)
1055 (define-key map
"\r" 'electric-verilog-terminate-line
)
1056 ;; backspace/delete key bindings
1057 (define-key map
[backspace] 'backward-delete-char-untabify)
1058 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
1059 (define-key map [delete] 'delete-char)
1060 (define-key map [(meta delete)] 'kill-word))
1061 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
1062 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
1063 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
1064 (define-key map "\M-\t" 'verilog-complete-word)
1065 (define-key map "\M-?" 'verilog-show-completions)
1066 (define-key map "\C-c\`" 'verilog-lint-off)
1067 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
1068 (define-key map "\C-c\C-r" 'verilog-label-be)
1069 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
1070 (define-key map "\C-c=" 'verilog-pretty-expr)
1071 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
1072 (define-key map "\M-*" 'verilog-star-comment)
1073 (define-key map "\C-c\C-c" 'verilog-comment-region)
1074 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
1075 (when (featurep 'xemacs)
1076 (define-key map [(meta control h)] 'verilog-mark-defun)
1077 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
1078 (define-key map "\M-\C-e" 'verilog-end-of-defun))
1079 (define-key map "\C-c\C-d" 'verilog-goto-defun)
1080 (define-key map "\C-c\C-k" 'verilog-delete-auto)
1081 (define-key map "\C-c\C-a" 'verilog-auto)
1082 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
1083 (define-key map "\C-c\C-z" 'verilog-inject-auto)
1084 (define-key map "\C-c\C-e" 'verilog-expand-vector)
1085 (define-key map "\C-c\C-h" 'verilog-header)
1087 "Keymap used in Verilog mode.")
1091 verilog-menu verilog-mode-map "Menu for Verilog mode"
1092 (verilog-easy-menu-filter
1094 ("Choose Compilation Action"
1097 (setq verilog-tool nil)
1098 (verilog-set-compile-command))
1100 :selected (equal verilog-tool nil)
1101 :help "When invoking compilation, use compile-command"]
1104 (setq verilog-tool 'verilog-linter)
1105 (verilog-set-compile-command))
1107 :selected (equal verilog-tool `verilog-linter)
1108 :help "When invoking compilation, use lint checker"]
1111 (setq verilog-tool 'verilog-coverage)
1112 (verilog-set-compile-command))
1114 :selected (equal verilog-tool `verilog-coverage)
1115 :help "When invoking compilation, annotate for coverage"]
1118 (setq verilog-tool 'verilog-simulator)
1119 (verilog-set-compile-command))
1121 :selected (equal verilog-tool `verilog-simulator)
1122 :help "When invoking compilation, interpret Verilog source"]
1125 (setq verilog-tool 'verilog-compiler)
1126 (verilog-set-compile-command))
1128 :selected (equal verilog-tool `verilog-compiler)
1129 :help "When invoking compilation, compile Verilog source"]
1132 ["Beginning of function" verilog-beg-of-defun
1134 :help "Move backward to the beginning of the current function or procedure"]
1135 ["End of function" verilog-end-of-defun
1137 :help "Move forward to the end of the current function or procedure"]
1138 ["Mark function" verilog-mark-defun
1140 :help "Mark the current Verilog function or procedure"]
1141 ["Goto function/module" verilog-goto-defun
1142 :help "Move to specified Verilog module/task/function"]
1143 ["Move to beginning of block" electric-verilog-backward-sexp
1144 :help "Move backward over one balanced expression"]
1145 ["Move to end of block" electric-verilog-forward-sexp
1146 :help "Move forward over one balanced expression"]
1149 ["Comment Region" verilog-comment-region
1150 :help "Put marked area into a comment"]
1151 ["UnComment Region" verilog-uncomment-region
1152 :help "Uncomment an area commented with Comment Region"]
1153 ["Multi-line comment insert" verilog-star-comment
1154 :help "Insert Verilog /* */ comment at point"]
1155 ["Lint error to comment" verilog-lint-off
1156 :help "Convert a Verilog linter warning line into a disable statement"]
1160 :help "Perform compilation-action (above) on the current buffer"]
1161 ["AUTO, Save, Compile" verilog-auto-save-compile
1162 :help "Recompute AUTOs, save buffer, and compile"]
1163 ["Next Compile Error" next-error
1164 :help "Visit next compilation error message and corresponding source code"]
1165 ["Ignore Lint Warning at point" verilog-lint-off
1166 :help "Convert a Verilog linter warning line into a disable statement"]
1168 ["Line up declarations around point" verilog-pretty-declarations
1169 :help "Line up declarations around point"]
1170 ["Line up equations around point" verilog-pretty-expr
1171 :help "Line up expressions around point"]
1172 ["Redo/insert comments on every end" verilog-label-be
1173 :help "Label matching begin ... end statements"]
1174 ["Expand [x:y] vector line" verilog-expand-vector
1175 :help "Take a signal vector on the current line and expand it to multiple lines"]
1176 ["Insert begin-end block" verilog-insert-block
1177 :help "Insert begin ... end"]
1178 ["Complete word" verilog-complete-word
1179 :help "Complete word at point"]
1181 ["Recompute AUTOs" verilog-auto
1182 :help "Expand AUTO meta-comment statements"]
1183 ["Kill AUTOs" verilog-delete-auto
1184 :help "Remove AUTO expansions"]
1185 ["Inject AUTOs" verilog-inject-auto
1186 :help "Inject AUTOs into legacy non-AUTO buffer"]
1188 ["AUTO General" (describe-function 'verilog-auto)
1189 :help "Help introduction on AUTOs"]
1190 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1191 :help "Help on verilog-library-flags"]
1192 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1193 :help "Help on verilog-library-directories"]
1194 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1195 :help "Help on verilog-library-files"]
1196 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1197 :help "Help on verilog-library-extensions"]
1198 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1199 :help "Help on reading `defines"]
1200 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1201 :help "Help on parsing `includes"]
1202 ["AUTOARG" (describe-function 'verilog-auto-arg)
1203 :help "Help on AUTOARG - declaring module port list"]
1204 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1205 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1206 ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-complement)
1207 :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
1208 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1209 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1210 ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
1211 :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
1212 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1213 :help "Help on AUTOINOUT - adding inouts from cells"]
1214 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1215 :help "Help on AUTOINPUT - adding inputs from cells"]
1216 ["AUTOINST" (describe-function 'verilog-auto-inst)
1217 :help "Help on AUTOINST - adding pins for cells"]
1218 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1219 :help "Help on expanding Verilog-2001 .* pins"]
1220 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1221 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1222 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1223 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1224 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1225 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1226 ["AUTOREG" (describe-function 'verilog-auto-reg)
1227 :help "Help on AUTOREG - declaring registers for non-wires"]
1228 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1229 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1230 ["AUTORESET" (describe-function 'verilog-auto-reset)
1231 :help "Help on AUTORESET - resetting always blocks"]
1232 ["AUTOSENSE" (describe-function 'verilog-auto-sense)
1233 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1234 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1235 :help "Help on AUTOTIEOFF - tieing off unused outputs"]
1236 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1237 :help "Help on AUTOUNUSED - terminating unused inputs"]
1238 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1239 :help "Help on AUTOWIRE - declaring wires for cells"]
1242 ["Submit bug report" verilog-submit-bug-report
1243 :help "Submit via mail a bug report on verilog-mode.el"]
1244 ["Version and FAQ" verilog-faq
1245 :help "Show the current version, and where to get the FAQ etc"]
1246 ["Customize Verilog Mode..." verilog-customize
1247 :help "Customize variables and other settings used by Verilog-Mode"]
1248 ["Customize Verilog Fonts & Colors" verilog-font-customize
1249 :help "Customize fonts used by Verilog-Mode."])))
1252 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1253 (verilog-easy-menu-filter
1255 ["Header" verilog-sk-header
1256 :help "Insert a header block at the top of file"]
1257 ["Comment" verilog-sk-comment
1258 :help "Insert a comment block"]
1260 ["Module" verilog-sk-module
1261 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1262 ["Primitive" verilog-sk-primitive
1263 :help "Insert a primitive .. (.. );.. endprimitive block"]
1265 ["Input" verilog-sk-input
1266 :help "Insert an input declaration"]
1267 ["Output" verilog-sk-output
1268 :help "Insert an output declaration"]
1269 ["Inout" verilog-sk-inout
1270 :help "Insert an inout declaration"]
1271 ["Wire" verilog-sk-wire
1272 :help "Insert a wire declaration"]
1273 ["Reg" verilog-sk-reg
1274 :help "Insert a register declaration"]
1275 ["Define thing under point as a register" verilog-sk-define-signal
1276 :help "Define signal under point as a register at the top of the module"]
1278 ["Initial" verilog-sk-initial
1279 :help "Insert an initial begin .. end block"]
1280 ["Always" verilog-sk-always
1281 :help "Insert an always @(AS) begin .. end block"]
1282 ["Function" verilog-sk-function
1283 :help "Insert a function .. begin .. end endfunction block"]
1284 ["Task" verilog-sk-task
1285 :help "Insert a task .. begin .. end endtask block"]
1286 ["Specify" verilog-sk-specify
1287 :help "Insert a specify .. endspecify block"]
1288 ["Generate" verilog-sk-generate
1289 :help "Insert a generate .. endgenerate block"]
1291 ["Begin" verilog-sk-begin
1292 :help "Insert a begin .. end block"]
1294 :help "Insert an if (..) begin .. end block"]
1295 ["(if) else" verilog-sk-else-if
1296 :help "Insert an else if (..) begin .. end block"]
1297 ["For" verilog-sk-for
1298 :help "Insert a for (...) begin .. end block"]
1299 ["While" verilog-sk-while
1300 :help "Insert a while (...) begin .. end block"]
1301 ["Fork" verilog-sk-fork
1302 :help "Insert a fork begin .. end .. join block"]
1303 ["Repeat" verilog-sk-repeat
1304 :help "Insert a repeat (..) begin .. end block"]
1305 ["Case" verilog-sk-case
1306 :help "Insert a case block, prompting for details"]
1307 ["Casex" verilog-sk-casex
1308 :help "Insert a casex (...) item: begin.. end endcase block"]
1309 ["Casez" verilog-sk-casez
1310 :help "Insert a casez (...) item: begin.. end endcase block"])))
1312 (defvar verilog-mode-abbrev-table nil
1313 "Abbrev table in use in Verilog-mode buffers.")
1315 (define-abbrev-table 'verilog-mode-abbrev-table ())
1321 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1322 "Replace occurrences of FROM-STRING with TO-STRING.
1323 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
1324 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1325 will break, as the o's continuously replace. xa -> x works ok though."
1326 ;; Hopefully soon to a emacs built-in
1328 (while (string-match from-string string start)
1329 (setq string (replace-match to-string fixedcase literal string)
1330 start (min (length string) (+ (match-beginning 0) (length to-string)))))
1333 (defsubst verilog-string-remove-spaces (string)
1334 "Remove spaces surrounding STRING."
1336 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1337 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1340 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1341 ; checkdoc-params: (REGEXP BOUND NOERROR)
1342 "Like `re-search-forward', but skips over match in comments or strings."
1343 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1345 (re-search-forward REGEXP BOUND NOERROR)
1346 (setq mdata (match-data))
1347 (and (verilog-skip-forward-comment-or-string)
1349 (setq mdata '(nil nil))
1353 (store-match-data mdata)
1356 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1357 ; checkdoc-params: (REGEXP BOUND NOERROR)
1358 "Like `re-search-backward', but skips over match in comments or strings."
1359 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1361 (re-search-backward REGEXP BOUND NOERROR)
1362 (setq mdata (match-data))
1363 (and (verilog-skip-backward-comment-or-string)
1365 (setq mdata '(nil nil))
1369 (store-match-data mdata)
1372 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1373 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1374 but trashes match data and is faster for REGEXP that doesn't match often.
1375 This may at some point use text properties to ignore comments,
1376 so there may be a large up front penalty for the first search."
1378 (while (and (not pt)
1379 (re-search-forward regexp bound noerror))
1380 (if (not (verilog-inside-comment-p))
1381 (setq pt (match-end 0))))
1384 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1385 ; checkdoc-params: (REGEXP BOUND NOERROR)
1386 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1387 but trashes match data and is faster for REGEXP that doesn't match often.
1388 This may at some point use text properties to ignore comments,
1389 so there may be a large up front penalty for the first search."
1391 (while (and (not pt)
1392 (re-search-backward regexp bound noerror))
1393 (if (not (verilog-inside-comment-p))
1394 (setq pt (match-end 0))))
1397 (defsubst verilog-get-beg-of-line (&optional arg)
1399 (beginning-of-line arg)
1402 (defsubst verilog-get-end-of-line (&optional arg)
1407 (defsubst verilog-within-string ()
1409 (nth 3 (parse-partial-sexp (verilog-get-beg-of-line) (point)))))
1411 (defvar compile-command)
1413 ;; compilation program
1414 (defun verilog-set-compile-command ()
1415 "Function to compute shell command to compile Verilog.
1417 This reads `verilog-tool' and sets `compile-command'. This specifies the
1418 program that executes when you type \\[compile] or
1419 \\[verilog-auto-save-compile].
1421 By default `verilog-tool' uses a Makefile if one exists in the current
1422 directory. If not, it is set to the `verilog-linter', `verilog-coverage',
1423 `verilog-simulator', or `verilog-compiler' variables, as selected with the
1424 Verilog -> \"Choose Compilation Action\" menu.
1426 You should set `verilog-tool' or the other variables to the path and
1427 arguments for your Verilog simulator. For example:
1430 \"(cd /tmp; surecov %s)\".
1432 In the former case, the path to the current buffer is concat'ed to the
1433 value of `verilog-tool'; in the later, the path to the current buffer is
1434 substituted for the %s.
1436 Where __FILE__ appears in the string, the `buffer-file-name' of the
1437 current buffer, without the directory portion, will be substituted."
1440 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1441 (file-exists-p "Makefile"))
1442 (make-local-variable 'compile-command)
1443 (setq compile-command "make "))
1445 (make-local-variable 'compile-command)
1446 (setq compile-command
1448 (if (string-match "%s" (eval verilog-tool))
1449 (format (eval verilog-tool) (or buffer-file-name ""))
1450 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1452 (verilog-modify-compile-command))
1454 (defun verilog-modify-compile-command ()
1455 "Replace meta-information in `compile-command'.
1456 Where __FILE__ appears in the string, the current buffer's file-name,
1457 without the directory portion, will be substituted."
1459 (stringp compile-command)
1460 (string-match "\\b__FILE__\\b" compile-command))
1461 (make-local-variable 'compile-command)
1462 (setq compile-command
1463 (verilog-string-replace-matches
1464 "\\b__FILE__\\b" (file-name-nondirectory (buffer-file-name))
1465 t t compile-command))))
1467 (if (featurep 'xemacs)
1468 ;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
1469 (defun verilog-error-regexp-add-xemacs ()
1470 "Teach XEmacs about verilog errors.
1471 Called by `compilation-mode-hook'. This allows \\[next-error] to
1474 (if (boundp 'compilation-error-regexp-systems-alist)
1476 (not (equal compilation-error-regexp-systems-list 'all))
1477 (not (member compilation-error-regexp-systems-list 'verilog)))
1478 (push 'verilog compilation-error-regexp-systems-list)))
1479 (if (boundp 'compilation-error-regexp-alist-alist)
1480 (if (not (assoc 'verilog compilation-error-regexp-alist-alist))
1481 (setcdr compilation-error-regexp-alist-alist
1482 (cons verilog-error-regexp-xemacs-alist
1483 (cdr compilation-error-regexp-alist-alist)))))
1484 (if (boundp 'compilation-font-lock-keywords)
1486 (make-local-variable 'compilation-font-lock-keywords)
1487 (setq compilation-font-lock-keywords verilog-error-font-lock-keywords)
1488 (font-lock-set-defaults)))
1489 ;; Need to re-run compilation-error-regexp builder
1490 (if (fboundp 'compilation-build-compilation-error-regexp-alist)
1491 (compilation-build-compilation-error-regexp-alist))
1494 ;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
1495 (defun verilog-error-regexp-add-emacs ()
1496 "Tell Emacs compile that we are Verilog.
1497 Called by `compilation-mode-hook'. This allows \\[next-error] to
1500 (if (boundp 'compilation-error-regexp-alist-alist)
1502 (if (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
1505 (push (car item) compilation-error-regexp-alist)
1506 (push item compilation-error-regexp-alist-alist)
1508 verilog-error-regexp-emacs-alist)))))
1510 (if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
1511 (if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
1513 (defconst verilog-directive-re
1514 ;; "`case" "`default" "`define" "`define" "`else" "`endfor" "`endif"
1515 ;; "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1516 ;; "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1517 ;; "`time_scale" "`undef" "`while"
1518 "\\<`\\(case\\|def\\(ault\\|ine\\(\\)?\\)\\|e\\(lse\\|nd\\(for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(mat\\)?\\|i\\(f\\(def\\|ndef\\)?\\|nclude\\)\\|let\\|protect\\|switch\\|time\\(_scale\\|scale\\)\\|undef\\|while\\)\\>")
1520 (defconst verilog-directive-re-1
1521 (concat "[ \t]*" verilog-directive-re))
1523 (defconst verilog-directive-begin
1524 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1526 (defconst verilog-directive-middle
1527 "\\<`\\(else\\|default\\|case\\)\\>")
1529 (defconst verilog-directive-end
1530 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1532 (defconst verilog-ovm-begin-re
1536 "`ovm_component_utils_begin"
1537 "`ovm_component_param_utils_begin"
1538 "`ovm_field_utils_begin"
1539 "`ovm_object_utils_begin"
1540 "`ovm_object_param_utils_begin"
1541 "`ovm_sequence_utils_begin"
1542 "`ovm_sequencer_utils_begin"
1545 (defconst verilog-ovm-end-re
1549 "`ovm_component_utils_end"
1550 "`ovm_field_utils_end"
1551 "`ovm_object_utils_end"
1552 "`ovm_sequence_utils_end"
1553 "`ovm_sequencer_utils_end"
1556 (defconst verilog-ovm-statement-re
1565 "`ovm_analysis_imp_decl"
1566 "`ovm_blocking_get_imp_decl"
1567 "`ovm_blocking_get_peek_imp_decl"
1568 "`ovm_blocking_master_imp_decl"
1569 "`ovm_blocking_peek_imp_decl"
1570 "`ovm_blocking_put_imp_decl"
1571 "`ovm_blocking_slave_imp_decl"
1572 "`ovm_blocking_transport_imp_decl"
1573 "`ovm_component_registry"
1574 "`ovm_component_registry_param"
1575 "`ovm_component_utils"
1578 "`ovm_declare_sequence_lib"
1585 "`ovm_field_aa_int_byte"
1586 "`ovm_field_aa_int_byte_unsigned"
1587 "`ovm_field_aa_int_int"
1588 "`ovm_field_aa_int_int_unsigned"
1589 "`ovm_field_aa_int_integer"
1590 "`ovm_field_aa_int_integer_unsigned"
1591 "`ovm_field_aa_int_key"
1592 "`ovm_field_aa_int_longint"
1593 "`ovm_field_aa_int_longint_unsigned"
1594 "`ovm_field_aa_int_shortint"
1595 "`ovm_field_aa_int_shortint_unsigned"
1596 "`ovm_field_aa_int_string"
1597 "`ovm_field_aa_object_int"
1598 "`ovm_field_aa_object_string"
1599 "`ovm_field_aa_string_int"
1600 "`ovm_field_aa_string_string"
1601 "`ovm_field_array_int"
1602 "`ovm_field_array_object"
1603 "`ovm_field_array_string"
1608 "`ovm_field_queue_int"
1609 "`ovm_field_queue_object"
1610 "`ovm_field_queue_string"
1611 "`ovm_field_sarray_int"
1616 "`ovm_get_peek_imp_decl"
1623 "`ovm_master_imp_decl"
1625 "`ovm_non_blocking_transport_imp_decl"
1626 "`ovm_nonblocking_get_imp_decl"
1627 "`ovm_nonblocking_get_peek_imp_decl"
1628 "`ovm_nonblocking_master_imp_decl"
1629 "`ovm_nonblocking_peek_imp_decl"
1630 "`ovm_nonblocking_put_imp_decl"
1631 "`ovm_nonblocking_slave_imp_decl"
1632 "`ovm_object_registry"
1633 "`ovm_object_registry_param"
1635 "`ovm_peek_imp_decl"
1636 "`ovm_phase_func_decl"
1637 "`ovm_phase_task_decl"
1638 "`ovm_print_aa_int_object"
1639 "`ovm_print_aa_string_int"
1640 "`ovm_print_aa_string_object"
1641 "`ovm_print_aa_string_string"
1642 "`ovm_print_array_int"
1643 "`ovm_print_array_object"
1644 "`ovm_print_array_string"
1645 "`ovm_print_object_queue"
1646 "`ovm_print_queue_int"
1647 "`ovm_print_string_queue"
1650 "`ovm_rand_send_with"
1652 "`ovm_sequence_utils"
1653 "`ovm_slave_imp_decl"
1654 "`ovm_transport_imp_decl"
1655 "`ovm_update_sequence_lib"
1656 "`ovm_update_sequence_lib_and_item"
1659 "`static_message") nil )))
1663 ;; Regular expressions used to calculate indent, etc.
1665 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
1673 (defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
1674 (defconst verilog-no-indent-begin-re
1675 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
1677 (defconst verilog-ends-re
1678 ;; Parenthesis indicate type of keyword found
1680 "\\(\\<else\\>\\)\\|" ; 1
1681 "\\(\\<if\\>\\)\\|" ; 2
1682 "\\(\\<end\\>\\)\\|" ; 3
1683 "\\(\\<endcase\\>\\)\\|" ; 4
1684 "\\(\\<endfunction\\>\\)\\|" ; 5
1685 "\\(\\<endtask\\>\\)\\|" ; 6
1686 "\\(\\<endspecify\\>\\)\\|" ; 7
1687 "\\(\\<endtable\\>\\)\\|" ; 8
1688 "\\(\\<endgenerate\\>\\)\\|" ; 9
1689 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
1690 "\\(\\<endclass\\>\\)\\|" ; 11
1691 "\\(\\<endgroup\\>\\)\\|" ; 12
1693 "\\(\\<`ovm_component_utils_end\\>\\)\\|"
1694 "\\(\\<`ovm_field_utils_end\\>\\)\\|"
1695 "\\(\\<`ovm_object_utils_end\\>\\)\\|"
1696 "\\(\\<`ovm_sequence_utils_end\\>\\)\\|"
1697 "\\(\\<`ovm_sequencer_utils_end\\>\\)"
1701 (defconst verilog-auto-end-comment-lines-re
1702 ;; Matches to names in this list cause auto-end-commentation
1704 verilog-directive-re "\\)\\|\\("
1706 (verilog-regexp-words
1734 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
1735 ;;; verilog-end-block-ordered-re matches exactly the same strings.
1736 (defconst verilog-end-block-ordered-re
1737 ;; Parenthesis indicate type of keyword found
1738 (concat "\\(\\<endcase\\>\\)\\|" ; 1
1739 "\\(\\<end\\>\\)\\|" ; 2
1740 "\\(\\<end" ; 3, but not used
1741 "\\(" ; 4, but not used
1742 "\\(function\\)\\|" ; 5
1744 "\\(module\\)\\|" ; 7
1745 "\\(primitive\\)\\|" ; 8
1746 "\\(interface\\)\\|" ; 9
1747 "\\(package\\)\\|" ; 10
1748 "\\(class\\)\\|" ; 11
1749 "\\(group\\)\\|" ; 12
1750 "\\(program\\)\\|" ; 13
1751 "\\(sequence\\)\\|" ; 14
1752 "\\(clocking\\)\\|" ; 15
1754 (defconst verilog-end-block-re
1756 (verilog-regexp-words
1758 `("end" ;; closes begin
1759 "endcase" ;; closes any of case, casex casez or randcase
1760 "join" "join_any" "join_none" ;; closes fork
1775 "`ovm_component_utils_end"
1776 "`ovm_field_utils_end"
1777 "`ovm_object_utils_end"
1778 "`ovm_sequence_utils_end"
1779 "`ovm_sequencer_utils_end"
1784 (defconst verilog-endcomment-reason-re
1785 ;; Parenthesis indicate type of keyword found
1787 "\\(\\<begin\\>\\)\\|" ; 1
1788 "\\(\\<else\\>\\)\\|" ; 2
1789 "\\(\\<end\\>\\s-+\\<else\\>\\)\\|" ; 3
1790 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|" ; 4
1791 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|" ; 5
1792 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|" ; 6
1793 "\\(\\<fork\\>\\)\\|" ; 7
1794 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
1796 "\\(\\<clocking\\>\\)\\|"
1797 "\\(\\<task\\>\\)\\|"
1798 "\\(\\<function\\>\\)\\|"
1799 "\\(\\<initial\\>\\)\\|"
1800 "\\(\\<interface\\>\\)\\|"
1801 "\\(\\<package\\>\\)\\|"
1802 "\\(\\<final\\>\\)\\|"
1804 "\\(\\<while\\>\\)\\|"
1805 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
1806 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
1809 (defconst verilog-named-block-re "begin[ \t]*:")
1811 ;; These words begin a block which can occur inside a module which should be indented,
1812 ;; and closed with the respective word from the end-block list
1814 (defconst verilog-beg-block-re
1816 (verilog-regexp-words
1818 "case" "casex" "casez" "randcase"
1828 "`ovm_component_utils_begin"
1829 "`ovm_component_param_utils_begin"
1830 "`ovm_field_utils_begin"
1831 "`ovm_object_utils_begin"
1832 "`ovm_object_param_utils_begin"
1833 "`ovm_sequence_utils_begin"
1834 "`ovm_sequencer_utils_begin"
1837 ;; These are the same words, in a specific order in the regular
1838 ;; expression so that matching will work nicely for
1839 ;; verilog-forward-sexp and verilog-calc-indent
1840 (defconst verilog-beg-block-re-ordered
1841 ( concat "\\(\\<begin\\>\\)" ;1
1842 "\\|\\(\\<randcase\\>\\|\\(\\<unique\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
1843 "\\|\\(\\(\\<disable\\>\\s-+\\)?fork\\>\\)" ;4,5
1844 "\\|\\(\\<class\\>\\)" ;6
1845 "\\|\\(\\<table\\>\\)" ;7
1846 "\\|\\(\\<specify\\>\\)" ;8
1847 "\\|\\(\\<function\\>\\)" ;9
1848 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<function\\>\\)" ;10
1849 "\\|\\(\\<task\\>\\)" ;14
1850 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;15
1851 "\\|\\(\\<generate\\>\\)" ;18
1852 "\\|\\(\\<covergroup\\>\\)" ;16 20
1853 "\\|\\(\\(\\(\\<cover\\>\\s-+\\)\\|\\(\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;17 21
1854 "\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
1855 "\\|\\(\\<clocking\\>\\)" ;22 27
1856 "\\|\\(\\<`ovm_[a-z_]+_begin\\>\\)" ;28
1861 (defconst verilog-end-block-ordered-rry
1862 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
1863 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
1864 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
1865 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
1866 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
1867 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
1868 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
1869 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
1870 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
1871 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
1872 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
1873 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
1874 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
1877 (defconst verilog-nameable-item-re
1879 (verilog-regexp-words
1882 "join" "join_any" "join_none"
1899 (defconst verilog-declaration-opener
1901 (verilog-regexp-words
1902 `("module" "begin" "task" "function"))))
1904 (defconst verilog-declaration-prefix-re
1906 (verilog-regexp-words
1909 "inout" "input" "output" "ref"
1911 "const" "static" "protected" "local"
1913 "localparam" "parameter" "var"
1917 (defconst verilog-declaration-core-re
1919 (verilog-regexp-words
1921 ;; port direction (by themselves)
1922 "inout" "input" "output"
1923 ;; integer_atom_type
1924 "byte" "shortint" "int" "longint" "integer" "time"
1925 ;; integer_vector_type
1928 "shortreal" "real" "realtime"
1930 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
1932 "string" "event" "chandle" "virtual" "enum" "genvar"
1935 "mailbox" "semaphore"
1937 (defconst verilog-declaration-re
1938 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
1939 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
1940 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
1941 (defconst verilog-optional-signed-range-re
1943 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
1944 (defconst verilog-macroexp-re "`\\sw+")
1946 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
1947 (defconst verilog-declaration-re-2-no-macro
1948 (concat "\\s-*" verilog-declaration-re
1949 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
1951 (defconst verilog-declaration-re-2-macro
1952 (concat "\\s-*" verilog-declaration-re
1953 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
1954 "\\|\\(" verilog-macroexp-re "\\)"
1956 (defconst verilog-declaration-re-1-macro
1957 (concat "^" verilog-declaration-re-2-macro))
1959 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
1961 (defconst verilog-defun-re
1962 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
1963 (defconst verilog-end-defun-re
1964 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
1965 (defconst verilog-zero-indent-re
1966 (concat verilog-defun-re "\\|" verilog-end-defun-re))
1968 (defconst verilog-behavioral-block-beg-re
1969 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
1970 "function" "task"))))
1971 (defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
1972 (defconst verilog-indent-re
1974 (verilog-regexp-words
1977 "always" "always_latch" "always_ff" "always_comb"
1979 ; "unique" "priority"
1980 "case" "casex" "casez" "randcase" "endcase"
1982 "clocking" "endclocking"
1983 "config" "endconfig"
1984 "covergroup" "endgroup"
1985 "fork" "join" "join_any" "join_none"
1986 "function" "endfunction"
1988 "generate" "endgenerate"
1990 "interface" "endinterface"
1991 "module" "macromodule" "endmodule"
1992 "package" "endpackage"
1993 "primitive" "endprimative"
1994 "program" "endprogram"
1995 "property" "endproperty"
1996 "sequence" "randsequence" "endsequence"
1997 "specify" "endspecify"
2004 "`if" "`ifdef" "`ifndef" "`else" "`endif"
2005 "`while" "`endwhile"
2010 "`protect" "`endprotect"
2011 "`switch" "`endswitch"
2015 "`ovm_component_utils_begin"
2016 "`ovm_component_param_utils_begin"
2017 "`ovm_field_utils_begin"
2018 "`ovm_object_utils_begin"
2019 "`ovm_object_param_utils_begin"
2020 "`ovm_sequence_utils_begin"
2021 "`ovm_sequencer_utils_begin"
2023 "`ovm_component_utils_end"
2024 "`ovm_field_utils_end"
2025 "`ovm_object_utils_end"
2026 "`ovm_sequence_utils_end"
2027 "`ovm_sequencer_utils_end"
2030 (defconst verilog-defun-level-not-generate-re
2032 (verilog-regexp-words
2033 `( "module" "macromodule" "primitive" "class" "program"
2034 "interface" "package" "config"))))
2036 (defconst verilog-defun-level-re
2038 (verilog-regexp-words
2040 `( "module" "macromodule" "primitive" "class" "program"
2041 "interface" "package" "config")
2042 `( "initial" "final" "always" "always_comb" "always_ff"
2043 "always_latch" "endtask" "endfunction" )))))
2045 (defconst verilog-defun-level-generate-only-re
2047 (verilog-regexp-words
2048 `( "initial" "final" "always" "always_comb" "always_ff"
2049 "always_latch" "endtask" "endfunction" ))))
2051 (defconst verilog-cpp-level-re
2053 (verilog-regexp-words
2055 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
2057 (defconst verilog-disable-fork-re "disable\\s-+fork")
2058 (defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
2059 (defconst verilog-extended-complete-re
2060 (concat "\\(\\<extern\\s-+\\|\\<virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
2061 "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
2062 "\\|\\(\\<import\\>\\s-+\\)?\"DPI-C\"\\s-+\\(function\\>\\|task\\>\\)"
2063 "\\|" verilog-extended-case-re ))
2064 (defconst verilog-basic-complete-re
2066 (verilog-regexp-words
2068 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
2069 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
2070 "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
2072 (defconst verilog-complete-reg
2074 verilog-extended-complete-re
2076 verilog-basic-complete-re))
2078 (defconst verilog-end-statement-re
2079 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
2080 verilog-end-block-re "\\)"))
2082 (defconst verilog-endcase-re
2083 (concat verilog-extended-case-re "\\|"
2088 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
2089 "String used to mark beginning of excluded text.")
2090 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
2091 "String used to mark end of excluded text.")
2092 (defconst verilog-preprocessor-re
2094 (verilog-regexp-words
2096 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
2099 (defconst verilog-keywords
2100 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
2101 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
2102 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
2103 "`time_scale" "`undef" "`while"
2105 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
2106 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
2107 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
2108 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
2109 "config" "const" "constraint" "context" "continue" "cover"
2110 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
2111 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
2112 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
2113 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
2114 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
2115 "endtask" "enum" "event" "expect" "export" "extends" "extern"
2116 "final" "first_match" "for" "force" "foreach" "forever" "fork"
2117 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
2118 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
2119 "include" "initial" "inout" "input" "inside" "instance" "int"
2120 "integer" "interface" "intersect" "join" "join_any" "join_none"
2121 "large" "liblist" "library" "local" "localparam" "logic"
2122 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
2123 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
2124 "notif0" "notif1" "null" "or" "output" "package" "packed"
2125 "parameter" "pmos" "posedge" "primitive" "priority" "program"
2126 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
2127 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2128 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
2129 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
2130 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
2131 "showcancelled" "signed" "small" "solve" "specify" "specparam"
2132 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
2133 "supply1" "table" "tagged" "task" "this" "throughout" "time"
2134 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
2135 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
2136 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
2137 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
2138 "wire" "with" "within" "wor" "xnor" "xor"
2140 "List of Verilog keywords.")
2142 (defconst verilog-comment-start-regexp "//\\|/\\*"
2143 "Dual comment value for `comment-start-regexp'.")
2145 (defvar verilog-mode-syntax-table
2146 (let ((table (make-syntax-table)))
2147 ;; Populate the syntax TABLE.
2148 (modify-syntax-entry ?\\ "\\" table)
2149 (modify-syntax-entry ?+ "." table)
2150 (modify-syntax-entry ?- "." table)
2151 (modify-syntax-entry ?= "." table)
2152 (modify-syntax-entry ?% "." table)
2153 (modify-syntax-entry ?< "." table)
2154 (modify-syntax-entry ?> "." table)
2155 (modify-syntax-entry ?& "." table)
2156 (modify-syntax-entry ?| "." table)
2157 (modify-syntax-entry ?` "w" table)
2158 (modify-syntax-entry ?_ "w" table)
2159 (modify-syntax-entry ?\' "." table)
2161 ;; Set up TABLE to handle block and line style comments.
2162 (if (featurep 'xemacs)
2164 ;; XEmacs (formerly Lucid) has the best implementation
2165 (modify-syntax-entry ?/ ". 1456" table)
2166 (modify-syntax-entry ?* ". 23" table)
2167 (modify-syntax-entry ?\n "> b" table))
2168 ;; Emacs does things differently, but we can work with it
2169 (modify-syntax-entry ?/ ". 124b" table)
2170 (modify-syntax-entry ?* ". 23" table)
2171 (modify-syntax-entry ?\n "> b" table))
2173 "Syntax table used in Verilog mode buffers.")
2175 (defvar verilog-font-lock-keywords nil
2176 "Default highlighting for Verilog mode.")
2178 (defvar verilog-font-lock-keywords-1 nil
2179 "Subdued level highlighting for Verilog mode.")
2181 (defvar verilog-font-lock-keywords-2 nil
2182 "Medium level highlighting for Verilog mode.
2183 See also `verilog-font-lock-extra-types'.")
2185 (defvar verilog-font-lock-keywords-3 nil
2186 "Gaudy level highlighting for Verilog mode.
2187 See also `verilog-font-lock-extra-types'.")
2188 (defvar verilog-font-lock-translate-off-face
2189 'verilog-font-lock-translate-off-face
2190 "Font to use for translated off regions.")
2191 (defface verilog-font-lock-translate-off-face
2194 (:background "gray90" :italic t ))
2197 (:background "gray10" :italic t ))
2198 (((class grayscale) (background light))
2199 (:foreground "DimGray" :italic t))
2200 (((class grayscale) (background dark))
2201 (:foreground "LightGray" :italic t))
2203 "Font lock mode face used to background highlight translate-off regions."
2204 :group 'font-lock-highlighting-faces)
2206 (defvar verilog-font-lock-p1800-face
2207 'verilog-font-lock-p1800-face
2208 "Font to use for p1800 keywords.")
2209 (defface verilog-font-lock-p1800-face
2212 (:foreground "DarkOrange3" :bold t ))
2215 (:foreground "orange1" :bold t ))
2217 "Font lock mode face used to highlight P1800 keywords."
2218 :group 'font-lock-highlighting-faces)
2220 (defvar verilog-font-lock-ams-face
2221 'verilog-font-lock-ams-face
2222 "Font to use for Analog/Mixed Signal keywords.")
2223 (defface verilog-font-lock-ams-face
2226 (:foreground "Purple" :bold t ))
2229 (:foreground "orange1" :bold t ))
2231 "Font lock mode face used to highlight AMS keywords."
2232 :group 'font-lock-highlighting-faces)
2234 (defvar verilog-font-grouping-keywords-face
2235 'verilog-font-lock-grouping-keywords-face
2236 "Font to use for Verilog Grouping Keywords (such as begin..end).")
2237 (defface verilog-font-lock-grouping-keywords-face
2240 (:foreground "red4" :bold t ))
2243 (:foreground "red4" :bold t ))
2245 "Font lock mode face used to highlight verilog grouping keywords."
2246 :group 'font-lock-highlighting-faces)
2248 (let* ((verilog-type-font-keywords
2252 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
2253 "event" "genvar" "inout" "input" "integer" "localparam"
2254 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
2255 "output" "parameter" "pmos" "pull0" "pull1" "pullup"
2256 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
2257 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
2258 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
2259 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
2260 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
2263 (verilog-pragma-keywords
2266 '("surefire" "synopsys" "rtl_synthesis" "verilint" "leda" "0in") nil
2269 (verilog-p1800-keywords
2272 '("alias" "assert" "assume" "automatic" "before" "bind"
2273 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
2274 "clocking" "config" "const" "constraint" "context" "continue"
2275 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
2276 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
2277 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
2278 "expect" "export" "extends" "extern" "first_match" "foreach"
2279 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
2280 "illegal_bins" "import" "incdir" "include" "inside" "instance"
2281 "int" "intersect" "large" "liblist" "library" "local" "longint"
2282 "matches" "medium" "modport" "new" "noshowcancelled" "null"
2283 "packed" "program" "property" "protected" "pull0" "pull1"
2284 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2285 "randcase" "randsequence" "ref" "release" "return" "scalared"
2286 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
2287 "specparam" "static" "string" "strong0" "strong1" "struct"
2288 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
2289 "type" "union" "unsigned" "use" "var" "virtual" "void"
2290 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
2293 (verilog-ams-keywords
2296 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
2297 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
2298 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
2299 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
2300 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
2301 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
2302 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
2303 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
2304 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
2305 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
2306 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
2308 (verilog-font-keywords
2312 "assign" "case" "casex" "casez" "randcase" "deassign"
2313 "default" "disable" "else" "endcase" "endfunction"
2314 "endgenerate" "endinterface" "endmodule" "endprimitive"
2315 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
2316 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
2317 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
2318 "package" "endpackage" "always" "always_comb" "always_ff"
2319 "always_latch" "posedge" "primitive" "priority" "release"
2320 "repeat" "specify" "table" "task" "unique" "wait" "while"
2321 "class" "program" "endclass" "endprogram"
2324 (verilog-font-grouping-keywords
2327 '( "begin" "end" ) nil ))))
2329 (setq verilog-font-lock-keywords
2331 ;; Fontify all builtin keywords
2332 (concat "\\<\\(" verilog-font-keywords "\\|"
2333 ;; And user/system tasks and functions
2334 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
2336 ;; Fontify all types
2337 (if verilog-highlight-grouping-keywords
2338 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2339 'verilog-font-lock-ams-face)
2340 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2341 'font-lock-type-face))
2342 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
2343 'font-lock-type-face)
2344 ;; Fontify IEEE-P1800 keywords appropriately
2345 (if verilog-highlight-p1800-keywords
2346 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
2347 'verilog-font-lock-p1800-face)
2348 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
2349 'font-lock-type-face))
2350 ;; Fontify Verilog-AMS keywords
2351 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
2352 'verilog-font-lock-ams-face)))
2354 (setq verilog-font-lock-keywords-1
2355 (append verilog-font-lock-keywords
2357 ;; Fontify module definitions
2359 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
2360 '(1 font-lock-keyword-face)
2361 '(3 font-lock-function-name-face 'prepend))
2362 ;; Fontify function definitions
2364 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
2365 '(1 font-lock-keyword-face)
2366 '(3 font-lock-reference-face prepend))
2367 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
2368 (1 font-lock-keyword-face)
2369 (2 font-lock-reference-face append))
2370 '("\\<function\\>\\s-+\\(\\sw+\\)"
2371 1 'font-lock-reference-face append))))
2373 (setq verilog-font-lock-keywords-2
2374 (append verilog-font-lock-keywords-1
2377 (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)")
2378 ;; Fontify escaped names
2379 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
2380 ;; Fontify macro definitions/ uses
2381 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
2382 'font-lock-preprocessor-face
2383 'font-lock-type-face))
2384 ;; Fontify delays/numbers
2385 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
2386 0 font-lock-type-face append)
2387 ;; Fontify instantiation names
2388 '("\\([A-Za-z][A-Za-z0-9_]+\\)\\s-*(" 1 font-lock-function-name-face)
2391 (setq verilog-font-lock-keywords-3
2392 (append verilog-font-lock-keywords-2
2393 (when verilog-highlight-translate-off
2395 ;; Fontify things in translate off regions
2396 '(verilog-match-translate-off
2397 (0 'verilog-font-lock-translate-off-face prepend))
2401 (defun verilog-inside-comment-p ()
2402 "Check if point inside a nested comment."
2404 (let ((st-point (point)) hitbeg)
2405 (or (search-backward "//" (verilog-get-beg-of-line) t)
2407 ;; This is for tricky case //*, we keep searching if /*
2408 ;; is proceeded by // on same line.
2410 (and (setq hitbeg (search-backward "/*" nil t))
2413 (search-backward "//" (verilog-get-beg-of-line) t))))
2415 (not (search-forward "*/" st-point t)))))))
2417 (defun verilog-declaration-end ()
2418 (search-forward ";"))
2420 (defun verilog-point-text (&optional pointnum)
2421 "Return text describing where POINTNUM or current point is (for errors).
2422 Use filename, if current buffer being edited shorten to just buffer name."
2423 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
2427 ":" (int-to-string (count-lines (point-min) (or pointnum (point))))))
2429 (defun electric-verilog-backward-sexp ()
2430 "Move backward over one balanced expression."
2432 ;; before that see if we are in a comment
2433 (verilog-backward-sexp))
2435 (defun electric-verilog-forward-sexp ()
2436 "Move forward over one balanced expression."
2438 ;; before that see if we are in a comment
2439 (verilog-forward-sexp))
2441 ;;;used by hs-minor-mode
2442 (defun verilog-forward-sexp-function (arg)
2444 (verilog-backward-sexp)
2445 (verilog-forward-sexp)))
2448 (defun verilog-backward-sexp ()
2453 (if (not (looking-at "\\<"))
2456 ((verilog-skip-backward-comment-or-string))
2457 ((looking-at "\\<else\\>")
2459 verilog-end-block-re
2460 "\\|\\(\\<else\\>\\)"
2461 "\\|\\(\\<if\\>\\)"))
2462 (while (and (not found)
2463 (verilog-re-search-backward reg nil 'move))
2465 ((match-end 1) ; matched verilog-end-block-re
2466 ; try to leap back to matching outward block by striding across
2467 ; indent level changing tokens then immediately
2468 ; previous line governs indentation.
2469 (verilog-leap-to-head))
2470 ((match-end 2) ; else, we're in deep
2471 (setq elsec (1+ elsec)))
2472 ((match-end 3) ; found it
2473 (setq elsec (1- elsec))
2475 ;; Now previous line describes syntax
2476 (setq found 't))))))
2477 ((looking-at verilog-end-block-re)
2478 (verilog-leap-to-head))
2479 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
2482 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
2484 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
2486 (verilog-re-search-backward "\\<class\\>" nil 'move))
2488 (verilog-re-search-backward "\\<program\\>" nil 'move))
2490 (verilog-re-search-backward "\\<interface\\>" nil 'move))
2492 (verilog-re-search-backward "\\<package\\>" nil 'move))
2495 (backward-sexp 1))))
2500 (defun verilog-forward-sexp ()
2505 (if (not (looking-at "\\<"))
2508 ((verilog-skip-forward-comment-or-string)
2509 (verilog-forward-syntactic-ws))
2510 ((looking-at verilog-beg-block-re-ordered)
2513 ;; Search forward for matching end
2514 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
2516 ;; Search forward for matching endcase
2517 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
2518 (setq md 3) ;; ender is third item in regexp
2521 ;; might be "disable fork"
2523 (looking-at verilog-disable-fork-re)
2524 (and (looking-at "fork")
2527 (looking-at verilog-disable-fork-re))))
2529 (goto-char (match-end 0))
2533 ;; Search forward for matching join
2534 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))))
2536 ;; Search forward for matching endclass
2537 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
2540 ;; Search forward for matching endtable
2541 (setq reg "\\<endtable\\>" )
2544 ;; Search forward for matching endspecify
2545 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
2547 ;; Search forward for matching endfunction
2548 (setq reg "\\<endfunction\\>" )
2551 ;; Search forward for matching endfunction
2552 (setq reg "\\<endfunction\\>" )
2555 ;; Search forward for matching endtask
2556 (setq reg "\\<endtask\\>" )
2559 ;; Search forward for matching endtask
2560 (setq reg "\\<endtask\\>" )
2563 ;; Search forward for matching endgenerate
2564 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
2566 ;; Search forward for matching endgroup
2567 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
2569 ;; Search forward for matching endproperty
2570 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
2572 ;; Search forward for matching endsequence
2573 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
2574 (setq md 3)) ; 3 to get to endsequence in the reg above
2576 ;; Search forward for matching endclocking
2577 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
2583 (while (verilog-re-search-forward reg nil 'move)
2585 ((match-end md) ; the closer in reg, so we are climbing out
2586 (setq depth (1- depth))
2587 (if (= 0 depth) ; we are out!
2589 ((match-end 1) ; the opener in reg, so we are deeper now
2590 (setq depth (1+ depth))))))
2591 (if (verilog-re-search-forward reg nil 'move)
2592 (throw 'skip 1))))))
2594 ((looking-at (concat
2595 "\\(\\<\\(macro\\)?module\\>\\)\\|"
2596 "\\(\\<primitive\\>\\)\\|"
2597 "\\(\\<class\\>\\)\\|"
2598 "\\(\\<program\\>\\)\\|"
2599 "\\(\\<interface\\>\\)\\|"
2600 "\\(\\<package\\>\\)"))
2603 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
2605 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
2607 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
2609 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
2611 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
2613 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
2616 (if (= (following-char) ?\) )
2618 (forward-sexp 1)))))
2621 (if (= (following-char) ?\) )
2623 (forward-sexp 1))))))
2625 (defun verilog-declaration-beg ()
2626 (verilog-re-search-backward verilog-declaration-re (bobp) t))
2632 (defvar verilog-which-tool 1)
2634 (defun verilog-mode ()
2635 "Major mode for editing Verilog code.
2636 \\<verilog-mode-map>
2637 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
2638 AUTOs can improve coding efficiency.
2640 Use \\[verilog-faq] for a pointer to frequently asked questions.
2642 NEWLINE, TAB indents for Verilog code.
2643 Delete converts tabs to spaces as it moves back.
2645 Supports highlighting.
2647 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
2648 with no args, if that value is non-nil.
2650 Variables controlling indentation/edit style:
2652 variable `verilog-indent-level' (default 3)
2653 Indentation of Verilog statements with respect to containing block.
2654 `verilog-indent-level-module' (default 3)
2655 Absolute indentation of Module level Verilog statements.
2656 Set to 0 to get initial and always statements lined up
2657 on the left side of your screen.
2658 `verilog-indent-level-declaration' (default 3)
2659 Indentation of declarations with respect to containing block.
2660 Set to 0 to get them list right under containing block.
2661 `verilog-indent-level-behavioral' (default 3)
2662 Indentation of first begin in a task or function block
2663 Set to 0 to get such code to lined up underneath the task or
2665 `verilog-indent-level-directive' (default 1)
2666 Indentation of `ifdef/`endif blocks.
2667 `verilog-cexp-indent' (default 1)
2668 Indentation of Verilog statements broken across lines i.e.:
2671 `verilog-case-indent' (default 2)
2672 Indentation for case statements.
2673 `verilog-auto-newline' (default nil)
2674 Non-nil means automatically newline after semicolons and the punctuation
2676 `verilog-auto-indent-on-newline' (default t)
2677 Non-nil means automatically indent line after newline.
2678 `verilog-tab-always-indent' (default t)
2679 Non-nil means TAB in Verilog mode should always reindent the current line,
2680 regardless of where in the line point is when the TAB command is used.
2681 `verilog-indent-begin-after-if' (default t)
2682 Non-nil means to indent begin statements following a preceding
2683 if, else, while, for and repeat statements, if any. Otherwise,
2684 the begin is lined up with the preceding token. If t, you get:
2686 begin // amount of indent based on `verilog-cexp-indent'
2690 `verilog-auto-endcomments' (default t)
2691 Non-nil means a comment /* ... */ is set after the ends which ends
2692 cases, tasks, functions and modules.
2693 The type and name of the object will be set between the braces.
2694 `verilog-minimum-comment-distance' (default 10)
2695 Minimum distance (in lines) between begin and end required before a comment
2696 will be inserted. Setting this variable to zero results in every
2697 end acquiring a comment; the default avoids too many redundant
2698 comments in tight quarters.
2699 `verilog-auto-lineup' (default 'declarations)
2700 List of contexts where auto lineup of code should be done.
2702 Variables controlling other actions:
2704 `verilog-linter' (default surelint)
2705 Unix program to call to run the lint checker. This is the default
2706 command for \\[compile-command] and \\[verilog-auto-save-compile].
2708 See \\[customize] for the complete list of variables.
2710 AUTO expansion functions are, in part:
2712 \\[verilog-auto] Expand AUTO statements.
2713 \\[verilog-delete-auto] Remove the AUTOs.
2714 \\[verilog-inject-auto] Insert AUTOs for the first time.
2716 Some other functions are:
2718 \\[verilog-complete-word] Complete word with appropriate possibilities.
2719 \\[verilog-mark-defun] Mark function.
2720 \\[verilog-beg-of-defun] Move to beginning of current function.
2721 \\[verilog-end-of-defun] Move to end of current function.
2722 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
2724 \\[verilog-comment-region] Put marked area in a comment.
2725 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
2726 \\[verilog-insert-block] Insert begin ... end.
2727 \\[verilog-star-comment] Insert /* ... */.
2729 \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
2730 \\[verilog-sk-begin] Insert a begin .. end block.
2731 \\[verilog-sk-case] Insert a case block, prompting for details.
2732 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
2733 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
2734 \\[verilog-sk-header] Insert a header block at the top of file.
2735 \\[verilog-sk-initial] Insert an initial begin .. end block.
2736 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
2737 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
2738 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
2739 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
2740 \\[verilog-sk-specify] Insert a specify .. endspecify block.
2741 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
2742 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
2743 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
2744 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
2745 \\[verilog-sk-if] Insert an if (..) begin .. end block.
2746 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
2747 \\[verilog-sk-comment] Insert a comment block.
2748 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
2749 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
2750 \\[verilog-sk-input] Insert an input declaration, prompting for details.
2751 \\[verilog-sk-output] Insert an output declaration, prompting for details.
2752 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
2753 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
2754 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
2755 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
2756 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
2758 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
2759 Key bindings specific to `verilog-mode-map' are:
2761 \\{verilog-mode-map}"
2763 (kill-all-local-variables)
2764 (use-local-map verilog-mode-map)
2765 (setq major-mode 'verilog-mode)
2766 (setq mode-name "Verilog")
2767 (setq local-abbrev-table verilog-mode-abbrev-table)
2768 (set (make-local-variable 'beginning-of-defun-function)
2769 'verilog-beg-of-defun)
2770 (set (make-local-variable 'end-of-defun-function)
2771 'verilog-end-of-defun)
2772 (set-syntax-table verilog-mode-syntax-table)
2773 (make-local-variable 'indent-line-function)
2774 (setq indent-line-function 'verilog-indent-line-relative)
2775 (setq comment-indent-function 'verilog-comment-indent)
2776 (make-local-variable 'parse-sexp-ignore-comments)
2777 (setq parse-sexp-ignore-comments nil)
2778 (make-local-variable 'comment-start)
2779 (make-local-variable 'comment-end)
2780 (make-local-variable 'comment-multi-line)
2781 (make-local-variable 'comment-start-skip)
2782 (setq comment-start "// "
2784 comment-start-skip "/\\*+ *\\|// *"
2785 comment-multi-line nil)
2786 ;; Set up for compilation
2787 (setq verilog-which-tool 1)
2788 (setq verilog-tool 'verilog-linter)
2789 (verilog-set-compile-command)
2790 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
2791 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
2794 (when (featurep 'xemacs)
2795 (easy-menu-add verilog-stmt-menu)
2796 (easy-menu-add verilog-menu)
2797 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
2799 ;; Stuff for GNU Emacs
2800 (set (make-local-variable 'font-lock-defaults)
2801 `((verilog-font-lock-keywords verilog-font-lock-keywords-1
2802 verilog-font-lock-keywords-2
2803 verilog-font-lock-keywords-3)
2805 ,(if (functionp 'syntax-ppss)
2806 ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
2807 ;; font-lock-beginning-of-syntax-function, so
2808 ;; font-lock-beginning-of-syntax-function, can't use
2809 ;; verilog-beg-of-defun.
2811 'verilog-beg-of-defun)))
2812 ;;------------------------------------------------------------
2813 ;; now hook in 'verilog-colorize-include-files (eldo-mode.el&spice-mode.el)
2814 ;; all buffer local:
2815 (when (featurep 'xemacs)
2816 (make-local-hook 'font-lock-mode-hook)
2817 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
2818 (make-local-hook 'after-change-functions))
2819 (add-hook 'font-lock-mode-hook 'verilog-colorize-include-files-buffer t t)
2820 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-colorize-include-files-buffer t t) ; not in Emacs
2821 (add-hook 'after-change-functions 'verilog-colorize-include-files t t)
2823 ;; Tell imenu how to handle Verilog.
2824 (make-local-variable 'imenu-generic-expression)
2825 (setq imenu-generic-expression verilog-imenu-generic-expression)
2826 ;; Tell which-func-modes that imenu knows about verilog
2827 (when (boundp 'which-function-modes)
2828 (add-to-list 'which-func-modes 'verilog-mode))
2830 (when (boundp 'hs-special-modes-alist)
2831 (unless (assq 'verilog-mode hs-special-modes-alist)
2832 (setq hs-special-modes-alist
2833 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
2834 verilog-forward-sexp-function)
2835 hs-special-modes-alist))))
2838 (add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local
2839 (run-hooks 'verilog-mode-hook))
2843 ;; Electric functions
2845 (defun electric-verilog-terminate-line (&optional arg)
2846 "Terminate line and indent next line.
2847 With optional ARG, remove existing end of line comments."
2849 ;; before that see if we are in a comment
2850 (let ((state (save-excursion (verilog-syntax-ppss))))
2852 ((nth 7 state) ; Inside // comment
2855 (delete-horizontal-space)
2860 (beginning-of-line)))
2861 (verilog-indent-line))
2862 ((nth 4 state) ; Inside any comment (hence /**/)
2864 (verilog-more-comment))
2866 ;; First, check if current line should be indented
2868 (delete-horizontal-space)
2870 (skip-chars-forward " \t")
2871 (if (looking-at verilog-auto-end-comment-lines-re)
2872 (let ((indent-str (verilog-indent-line)))
2873 ;; Maybe we should set some endcomments
2874 (if verilog-auto-endcomments
2875 (verilog-set-auto-endcomments indent-str arg))
2877 (delete-horizontal-space)
2884 (delete-horizontal-space)
2886 ;; see if we should line up assignments
2888 (if (or (eq 'all verilog-auto-lineup)
2889 (eq 'assignments verilog-auto-lineup))
2890 (verilog-pretty-expr t "\\(<\\|:\\)?=" ))
2894 (if verilog-auto-indent-on-newline
2895 (verilog-indent-line)))
2899 (defun electric-verilog-terminate-and-indent ()
2900 "Insert a newline and indent for the next statement."
2902 (electric-verilog-terminate-line 1))
2904 (defun electric-verilog-semi ()
2905 "Insert `;' character and reindent the line."
2907 (verilog-insert-last-command-event)
2909 (if (or (verilog-in-comment-or-string-p)
2910 (verilog-in-escaped-name-p))
2914 (verilog-forward-ws&directives)
2915 (verilog-indent-line))
2916 (if (and verilog-auto-newline
2917 (not (verilog-parenthesis-depth)))
2918 (electric-verilog-terminate-line))))
2920 (defun electric-verilog-semi-with-comment ()
2921 "Insert `;' character, reindent the line and indent for comment."
2926 (verilog-indent-line))
2927 (indent-for-comment))
2929 (defun electric-verilog-colon ()
2930 "Insert `:' and do all indentations except line indent on this line."
2932 (verilog-insert-last-command-event)
2933 ;; Do nothing if within string.
2935 (verilog-within-string)
2936 (not (verilog-in-case-region-p)))
2940 (lim (progn (verilog-beg-of-statement) (point))))
2942 (verilog-backward-case-item lim)
2943 (verilog-indent-line)))
2944 ;; (let ((verilog-tab-always-indent nil))
2945 ;; (verilog-indent-line))
2948 ;;(defun electric-verilog-equal ()
2949 ;; "Insert `=', and do indentation if within block."
2951 ;; (verilog-insert-last-command-event)
2952 ;; Could auto line up expressions, but not yet
2953 ;; (if (eq (car (verilog-calculate-indent)) 'block)
2954 ;; (let ((verilog-tab-always-indent nil))
2955 ;; (verilog-indent-command)))
2958 (defun electric-verilog-tick ()
2959 "Insert back-tick, and indent to column 0 if this is a CPP directive."
2961 (verilog-insert-last-command-event)
2963 (if (verilog-in-directive-p)
2964 (verilog-indent-line))))
2966 (defun electric-verilog-tab ()
2967 "Function called when TAB is pressed in Verilog mode."
2969 ;; If verilog-tab-always-indent, indent the beginning of the line.
2971 ;; The region is active, indent it.
2972 ((and (region-active-p)
2973 (not (eq (region-beginning) (region-end))))
2974 (indent-region (region-beginning) (region-end) nil))
2975 ((or verilog-tab-always-indent
2977 (skip-chars-backward " \t")
2979 (let* ((oldpnt (point))
2983 (skip-chars-forward " \t")
2984 (verilog-indent-line)
2985 (back-to-indentation)
2987 (if (< (point) boi-point)
2988 (back-to-indentation)
2989 (cond ((not verilog-tab-to-comment))
2993 (indent-for-comment)
2994 (when (and (eolp) (= oldpnt (point)))
2995 ; kill existing comment
2997 (re-search-forward comment-start-skip oldpnt 'move)
2998 (goto-char (match-beginning 0))
2999 (skip-chars-backward " \t")
3000 (kill-region (point) oldpnt)))))))
3001 (t (progn (insert "\t")))))
3006 ;; Interactive functions
3009 (defun verilog-indent-buffer ()
3010 "Indent-region the entire buffer as Verilog code.
3011 To call this from the command line, see \\[verilog-batch-indent]."
3014 (indent-region (point-min) (point-max) nil))
3016 (defun verilog-insert-block ()
3017 "Insert Verilog begin ... end; block in the code with right indentation."
3019 (verilog-indent-line)
3021 (electric-verilog-terminate-line)
3023 (electric-verilog-terminate-line)
3026 (verilog-indent-line)))
3028 (defun verilog-star-comment ()
3029 "Insert Verilog star comment at point."
3031 (verilog-indent-line)
3039 (defun verilog-insert-1 (fmt max)
3040 "Use format string FMT to insert integers 0 to MAX - 1.
3041 Inserts one integer per line, at the current column. Stops early
3042 if it reaches the end of the buffer."
3043 (let ((col (current-column))
3047 (insert (format fmt n))
3049 ;; Note that this function does not bother to check for lines
3050 ;; shorter than col.
3054 (move-to-column col))))))
3056 (defun verilog-insert-indices (max)
3057 "Insert a set of indices into a rectangle.
3058 The upper left corner is defined by point. Indices begin with 0
3059 and extend to the MAX - 1. If no prefix arg is given, the user
3060 is prompted for a value. The indices are surrounded by square
3061 brackets \[]. For example, the following code with the point
3062 located after the first 'a' gives:
3068 a = b ==> insert-indices ==> a[ 4] = b
3074 (interactive "NMAX: ")
3075 (verilog-insert-1 "[%3d]" max))
3077 (defun verilog-generate-numbers (max)
3078 "Insert a set of generated numbers into a rectangle.
3079 The upper left corner is defined by point. The numbers are padded to three
3080 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
3081 is supplied, then the user is prompted for the MAX number. Consider the
3082 following code fragment:
3088 buf buf ==> generate-numbers ==> buf buf004
3094 (interactive "NMAX: ")
3095 (verilog-insert-1 "%3.3d" max))
3097 (defun verilog-mark-defun ()
3098 "Mark the current Verilog function (or procedure).
3099 This puts the mark at the end, and point at the beginning."
3101 (if (featurep 'xemacs)
3104 (verilog-end-of-defun)
3106 (verilog-beg-of-defun)
3107 (if (fboundp 'zmacs-activate-region)
3108 (zmacs-activate-region)))
3111 (defun verilog-comment-region (start end)
3112 ; checkdoc-params: (start end)
3113 "Put the region into a Verilog comment.
3114 The comments that are in this area are \"deformed\":
3115 `*)' becomes `!(*' and `}' becomes `!{'.
3116 These deformed comments are returned to normal if you use
3117 \\[verilog-uncomment-region] to undo the commenting.
3119 The commented area starts with `verilog-exclude-str-start', and ends with
3120 `verilog-exclude-str-end'. But if you change these variables,
3121 \\[verilog-uncomment-region] won't recognize the comments."
3124 ;; Insert start and endcomments
3126 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
3127 (not (save-excursion (skip-chars-backward " \t") (bolp))))
3129 (beginning-of-line))
3130 (insert verilog-exclude-str-end)
3135 (insert verilog-exclude-str-start)
3137 ;; Replace end-comments within commented area
3140 (while (re-search-backward "\\*/" start t)
3141 (replace-match "*-/" t t)))
3143 (let ((s+1 (1+ start)))
3144 (while (re-search-backward "/\\*" s+1 t)
3145 (replace-match "/-*" t t))))))
3147 (defun verilog-uncomment-region ()
3148 "Uncomment a commented area; change deformed comments back to normal.
3149 This command does nothing if the pointer is not in a commented
3150 area. See also `verilog-comment-region'."
3153 (let ((start (point))
3155 ;; Find the boundaries of the comment
3157 (setq start (progn (search-backward verilog-exclude-str-start nil t)
3159 (setq end (progn (search-forward verilog-exclude-str-end nil t)
3161 ;; Check if we're really inside a comment
3162 (if (or (equal start (point)) (<= end (point)))
3163 (message "Not standing within commented area.")
3165 ;; Remove endcomment
3168 (let ((pos (point)))
3170 (delete-region pos (1+ (point))))
3171 ;; Change comments back to normal
3173 (while (re-search-backward "\\*-/" start t)
3174 (replace-match "*/" t t)))
3176 (while (re-search-backward "/-\\*" start t)
3177 (replace-match "/*" t t)))
3178 ;; Remove start comment
3181 (let ((pos (point)))
3183 (delete-region pos (1+ (point)))))))))
3185 (defun verilog-beg-of-defun ()
3186 "Move backward to the beginning of the current function or procedure."
3188 (verilog-re-search-backward verilog-defun-re nil 'move))
3190 (defun verilog-end-of-defun ()
3191 "Move forward to the end of the current function or procedure."
3193 (verilog-re-search-forward verilog-end-defun-re nil 'move))
3195 (defun verilog-get-beg-of-defun (&optional warn)
3197 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
3200 (error "%s: Can't find module beginning" (verilog-point-text))
3202 (defun verilog-get-end-of-defun (&optional warn)
3204 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
3207 (error "%s: Can't find endmodule" (verilog-point-text))
3210 (defun verilog-label-be (&optional arg)
3211 "Label matching begin ... end, fork ... join and case ... endcase statements.
3212 With ARG, first kill any existing labels."
3217 (verilog-beg-of-defun)
3220 (verilog-end-of-defun)
3222 (goto-char (marker-position b))
3224 (message "Relabeling module..."))
3226 (> (marker-position e) (point))
3227 (verilog-re-search-forward
3229 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
3230 "\\|\\(`endif\\)\\|\\(`else\\)")
3232 (goto-char (match-beginning 0))
3233 (let ((indent-str (verilog-indent-line)))
3234 (verilog-set-auto-endcomments indent-str 't)
3236 (delete-horizontal-space))
3238 (if (= 9 (% cnt 10))
3239 (message "%d..." cnt)))
3244 (message "%d lines auto commented" cnt))))
3246 (defun verilog-beg-of-statement ()
3247 "Move backward to beginning of statement."
3249 ;; Move back token by token until we see the end
3250 ;; of some ealier line.
3252 ;; If the current point does not begin a new
3253 ;; statement, as in the character ahead of us is a ';', or SOF
3254 ;; or the string after us unambiguosly starts a statement,
3255 ;; or the token before us unambiguously ends a statement,
3256 ;; then move back a token and test again.
3259 (= (preceding-char) ?\;)
3260 (looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
3265 (looking-at verilog-complete-reg)
3266 (not (save-excursion
3267 (verilog-backward-token)
3268 (looking-at verilog-extended-complete-re))))
3269 (looking-at verilog-basic-complete-re)
3271 (verilog-backward-token)
3273 (looking-at verilog-end-block-re)
3274 (looking-at verilog-preprocessor-re)))))
3275 (verilog-backward-syntactic-ws)
3276 (verilog-backward-token))
3277 ;; Now point is where the previous line ended.
3278 (verilog-forward-syntactic-ws))
3280 (defun verilog-beg-of-statement-1 ()
3281 "Move backward to beginning of statement."
3283 (if (verilog-in-comment-p)
3284 (verilog-backward-syntactic-ws))
3287 (while (not (looking-at verilog-complete-reg))
3289 (verilog-backward-syntactic-ws)
3291 (= (preceding-char) ?\;))
3295 (verilog-backward-token))))
3296 (verilog-forward-syntactic-ws)))
3299 ; (not (looking-at verilog-complete-reg))
3301 ; (not (= (preceding-char) ?\;)))
3302 ; (verilog-backward-token)
3303 ; (verilog-backward-syntactic-ws)
3304 ; (setq pt (point)))
3306 ; ;(verilog-forward-syntactic-ws)
3308 (defun verilog-end-of-statement ()
3309 "Move forward to end of current statement."
3313 ((verilog-in-directive-p)
3317 ((looking-at verilog-beg-block-re)
3318 (verilog-forward-sexp))
3320 ((equal (char-after) ?\})
3323 ;; Skip to end of statement
3324 ((condition-case nil
3329 (verilog-skip-forward-comment-or-string)
3332 (cond ((looking-at "[ \t]*;")
3333 (skip-chars-forward "^;")
3335 (throw 'found (point)))
3338 (looking-at verilog-beg-block-re))
3339 (goto-char (match-beginning 0))
3341 ((looking-at "[ \t]*)")
3342 (throw 'found (point)))
3344 (throw 'found (point)))
3350 ;; Skip a whole block
3353 (verilog-re-search-forward verilog-end-statement-re nil 'move)
3354 (setq nest (if (match-end 1)
3358 (throw 'found (point)))
3360 (throw 'found (verilog-end-of-statement))))))
3363 (defun verilog-in-case-region-p ()
3364 "Return true if in a case region.
3365 More specifically, point @ in the line foo : @ begin"
3369 (progn (verilog-forward-syntactic-ws)
3370 (looking-at "\\<begin\\>"))
3371 (progn (verilog-backward-syntactic-ws)
3372 (= (preceding-char) ?\:)))
3376 (verilog-re-search-backward
3377 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
3378 "\\(\\<endcase\\>\\)\\>")
3382 (setq nest (1+ nest)))
3386 (setq nest (1- nest)))
3388 (throw 'found (= nest 0)))))))
3390 (defun verilog-in-struct-region-p ()
3391 "Return true if in a struct region.
3392 More specifically, in a list after a struct|union keyword."
3395 (let* ((state (verilog-syntax-ppss))
3396 (depth (nth 0 state)))
3398 (progn (backward-up-list depth)
3399 (verilog-beg-of-statement)
3400 (looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>"))))))
3402 (defun verilog-in-generate-region-p ()
3403 "Return true if in a generate region.
3404 More specifically, after a generate and before an endgenerate."
3411 (verilog-re-search-backward
3412 "\\<\\(module\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move)
3414 ((match-end 1) ; module - we have crawled out
3416 ((match-end 2) ; generate
3417 (setq nest (1- nest)))
3418 ((match-end 3) ; endgenerate
3419 (setq nest (1+ nest))))))))
3420 (= nest 0) )) ; return nest
3422 (defun verilog-in-fork-region-p ()
3423 "Return true if between a fork and join."
3425 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
3430 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
3432 ((match-end 1) ; fork
3433 (setq nest (1- nest)))
3434 ((match-end 2) ; join
3435 (setq nest (1+ nest)))))))
3436 (= nest 0) )) ; return nest
3438 (defun verilog-backward-case-item (lim)
3439 "Skip backward to nearest enclosing case item.
3440 Limit search to point LIM."
3446 (verilog-re-search-backward verilog-endcomment-reason-re
3449 ;; Try to find the real :
3450 (if (save-excursion (search-backward ":" lim1 t))
3456 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
3460 (setq colon (1+ colon))
3462 (error "%s: unbalanced [" (verilog-point-text))))
3464 (setq colon (1- colon)))
3467 (setq colon (1+ colon)))))
3468 ;; Skip back to beginning of case item
3469 (skip-chars-backward "\t ")
3470 (verilog-skip-backward-comment-or-string)
3475 (verilog-re-search-backward
3476 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
3480 (goto-char (match-end 1))
3481 (verilog-forward-ws&directives)
3482 (if (looking-at "(")
3485 (verilog-forward-ws&directives)))
3488 (goto-char (match-end 0))
3489 (verilog-forward-ws&directives)
3491 (error "Malformed case item"))))
3492 (setq str (buffer-substring b e))
3496 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
3497 (setq str (concat (substring str 0 e) "...")))
3506 (defun verilog-kill-existing-comment ()
3507 "Kill auto comment on this line."
3515 (search-forward "//" e t))))
3517 (delete-region (- b 2) e)))))
3519 (defconst verilog-directive-nest-re
3520 (concat "\\(`else\\>\\)\\|"
3521 "\\(`endif\\>\\)\\|"
3523 "\\(`ifdef\\>\\)\\|"
3524 "\\(`ifndef\\>\\)"))
3525 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
3526 "Add ending comment with given INDENT-STR.
3527 With KILL-EXISTING-COMMENT, remove what was there before.
3528 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
3529 Insert `// case expr ' if this line ends a case block.
3530 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
3531 Insert `// NAME ' if this line ends a function, task, module,
3532 primitive or interface named NAME."
3535 (; Comment close preprocessor directives
3537 (looking-at "\\(`endif\\)\\|\\(`else\\)")
3538 (or kill-existing-comment
3539 (not (save-excursion
3541 (search-backward "//" (verilog-get-beg-of-line) t)))))
3544 (else (if (match-end 2) "!" " ")))
3546 (if kill-existing-comment
3547 (verilog-kill-existing-comment))
3548 (delete-horizontal-space)
3551 (while (and (/= nest 0)
3552 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
3554 ((match-end 1) ; `else
3557 ((match-end 2) ; `endif
3558 (setq nest (1+ nest)))
3559 ((match-end 3) ; `if
3560 (setq nest (1- nest)))
3561 ((match-end 4) ; `ifdef
3562 (setq nest (1- nest)))
3563 ((match-end 5) ; `ifndef
3564 (setq nest (1- nest)))))
3571 (skip-chars-forward "^ \t")
3572 (verilog-forward-syntactic-ws)
3575 (skip-chars-forward "a-zA-Z0-9_")
3578 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
3579 (insert (concat " // " else m " " (buffer-substring b e))))
3581 (insert " // unmatched `else or `endif")
3584 (; Comment close case/class/function/task/module and named block
3585 (and (looking-at "\\<end")
3586 (or kill-existing-comment
3587 (not (save-excursion
3589 (search-backward "//" (verilog-get-beg-of-line) t)))))
3590 (let ((type (car indent-str)))
3591 (unless (eq type 'declaration)
3592 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
3593 (if (looking-at verilog-end-block-ordered-re)
3595 (;- This is a case block; search back for the start of this case
3596 (match-end 1) ;; of verilog-end-block-ordered-re
3599 (str "UNMATCHED!!"))
3601 (verilog-leap-to-head)
3603 ((looking-at "\\<randcase\\>")
3604 (setq str "randcase")
3606 ((looking-at "\\(\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
3607 (goto-char (match-end 0))
3608 (setq str (concat (match-string 0) " " (verilog-get-expr)))
3612 (if kill-existing-comment
3613 (verilog-kill-existing-comment))
3614 (delete-horizontal-space)
3615 (insert (concat " // " str ))
3616 (if err (ding 't))))
3618 (;- This is a begin..end block
3619 (match-end 2) ;; of verilog-end-block-ordered-re
3620 (let ((str " // UNMATCHED !!")
3626 (verilog-leap-to-head)
3627 (setq there (point))
3628 (if (not (match-end 0))
3632 (if kill-existing-comment
3633 (verilog-kill-existing-comment))
3634 (delete-horizontal-space)
3638 (save-excursion (verilog-beg-of-defun) (point)))
3641 (;-- handle named block differently
3642 (looking-at verilog-named-block-re)
3643 (search-forward ":")
3644 (setq there (point))
3645 (setq str (verilog-get-expr))
3647 (setq str (concat " // block: " str )))
3649 ((verilog-in-case-region-p) ;-- handle case item differently
3651 (setq str (verilog-backward-case-item lim))
3652 (setq there (point))
3654 (setq str (concat " // case: " str )))
3656 (;- try to find "reason" for this begin
3660 (verilog-backward-token)
3661 (verilog-beg-of-statement-1)
3665 ((looking-at verilog-endcomment-reason-re)
3666 (setq there (match-end 0))
3667 (setq cntx (concat (match-string 0) " "))
3673 (if (and (verilog-continued-line)
3674 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
3676 (goto-char (match-end 0))
3677 (setq there (point))
3679 (concat " // " (match-string 0) " " (verilog-get-expr))))
3685 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)"))
3687 (while (verilog-re-search-backward reg nil 'move)
3689 ((match-end 1) ; begin
3690 (setq nest (1- nest)))
3691 ((match-end 2) ; end
3692 (setq nest (1+ nest)))
3696 (goto-char (match-end 0))
3697 (setq there (point))
3699 (setq str (verilog-get-expr))
3700 (setq str (concat " // else: !if" str ))
3701 (throw 'skip 1)))))))))
3707 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)"))
3709 (while (verilog-re-search-backward reg nil 'move)
3711 ((match-end 1) ; begin
3712 (setq nest (1- nest)))
3713 ((match-end 2) ; end
3714 (setq nest (1+ nest)))
3718 (goto-char (match-end 0))
3719 (setq there (point))
3721 (setq str (verilog-get-expr))
3722 (setq str (concat " // else: !if" str ))
3723 (throw 'skip 1)))))))))
3724 (; always_comb, always_ff, always_latch
3725 (or (match-end 4) (match-end 5) (match-end 6))
3726 (goto-char (match-end 0))
3727 (setq there (point))
3729 (setq str (concat " // " cntx )))
3731 (;- task/function/initial et cetera
3734 (goto-char (match-end 0))
3735 (setq there (point))
3737 (setq str (concat " // " cntx (verilog-get-expr))))
3740 (setq str " // auto-endcomment confused "))))
3743 (verilog-in-case-region-p) ;-- handle case item differently
3745 (setq there (point))
3747 (setq str (verilog-backward-case-item lim))))
3749 (setq str (concat " // case: " str )))
3751 ((verilog-in-fork-region-p)
3753 (setq str " // fork branch" ))
3755 ((looking-at "\\<end\\>")
3758 (verilog-forward-syntactic-ws)
3760 (setq str (verilog-get-expr))
3761 (setq str (concat " // " cntx str )))
3766 (if kill-existing-comment
3767 (verilog-kill-existing-comment))
3768 (delete-horizontal-space)
3770 (> (count-lines here there) verilog-minimum-comment-distance))
3774 (;- this is endclass, which can be nested
3775 (match-end 11) ;; of verilog-end-block-ordered-re
3778 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
3782 (while (verilog-re-search-backward reg nil 'move)
3784 ((match-end 3) ; endclass
3786 (setq string "unmatched endclass")
3789 ((match-end 2) ; endclass
3790 (setq nest (1+ nest)))
3792 ((match-end 1) ; class
3793 (setq nest (1- nest))
3796 (goto-char (match-end 0))
3799 (skip-chars-forward "^ \t")
3800 (verilog-forward-ws&directives)
3803 (skip-chars-forward "a-zA-Z0-9_")
3805 (setq string (buffer-substring b e)))
3809 (insert (concat " // " string ))))
3811 (;- this is end{function,generate,task,module,primitive,table,generate}
3812 ;- which can not be nested.
3814 (let (string reg (name-re nil))
3816 (if kill-existing-comment
3818 (verilog-kill-existing-comment)))
3819 (delete-horizontal-space)
3822 ((match-end 5) ;; of verilog-end-block-ordered-re
3823 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
3824 (setq name-re "\\w+\\s-*(")
3826 ((match-end 6) ;; of verilog-end-block-ordered-re
3827 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
3828 ((match-end 7) ;; of verilog-end-block-ordered-re
3829 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
3830 ((match-end 8) ;; of verilog-end-block-ordered-re
3831 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3832 ((match-end 9) ;; of verilog-end-block-ordered-re
3833 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
3834 ((match-end 10) ;; of verilog-end-block-ordered-re
3835 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3836 ((match-end 11) ;; of verilog-end-block-ordered-re
3837 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3838 ((match-end 12) ;; of verilog-end-block-ordered-re
3839 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3840 ((match-end 13) ;; of verilog-end-block-ordered-re
3841 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3842 ((match-end 14) ;; of verilog-end-block-ordered-re
3843 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3844 ((match-end 15) ;; of verilog-end-block-ordered-re
3845 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
3847 (t (error "Problem in verilog-set-auto-endcomments")))
3850 (verilog-re-search-backward reg nil 'move)
3854 (skip-chars-forward "^ \t")
3855 (verilog-forward-ws&directives)
3856 (if (and name-re (verilog-re-search-forward name-re nil 'move))
3858 (goto-char (match-beginning 0))
3859 (verilog-forward-ws&directives)))
3862 (skip-chars-forward "a-zA-Z0-9_")
3864 (setq string (buffer-substring b e)))
3867 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
3869 (insert (concat " // " string )))
3872 (defun verilog-get-expr()
3873 "Grab expression at point, e.g, case ( a | b & (c ^d))."
3875 (verilog-forward-syntactic-ws)
3876 (skip-chars-forward " \t")
3882 (verilog-forward-syntactic-ws)
3883 (if (looking-at "(")
3886 (while (and (/= par 0)
3887 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
3890 (setq par (1+ par)))
3892 (setq par (1- par)))))))
3896 (while (and (/= par 0)
3897 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
3900 (setq par (1+ par)))
3902 (setq par (1- par)))))
3906 (while (and (/= par 0)
3907 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
3910 (setq par (1+ par)))
3912 (setq par (1- par)))))
3913 (verilog-forward-syntactic-ws)
3914 (skip-chars-forward "^ \t\n\f")
3916 ((looking-at "/[/\\*]")
3919 (skip-chars-forward "^: \t\n\f")
3921 (str (buffer-substring b e)))
3922 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
3923 (setq str (concat (substring str 0 e) "...")))
3926 (defun verilog-expand-vector ()
3927 "Take a signal vector on the current line and expand it to multiple lines.
3928 Useful for creating tri's and other expanded fields."
3930 (verilog-expand-vector-internal "[" "]"))
3932 (defun verilog-expand-vector-internal (bra ket)
3933 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
3936 (let ((signal-string (buffer-substring (point)
3938 (end-of-line) (point)))))
3942 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
3944 "\\(.*\\)$") signal-string)
3945 (let* ((sig-head (match-string 1 signal-string))
3946 (vec-start (string-to-number (match-string 2 signal-string)))
3947 (vec-end (if (= (match-beginning 3) (match-end 3))
3950 (substring signal-string (1+ (match-beginning 3))
3953 (if (= (match-beginning 4) (match-end 4))
3956 (substring signal-string (+ 2 (match-beginning 4))
3958 (sig-tail (match-string 5 signal-string))
3963 (let ((tmp vec-start))
3964 (setq vec-start vec-end
3966 vec-range (- vec-range))))
3967 (if (< vec-end vec-start)
3968 (while (<= vec-end vec-start)
3969 (setq vec (append vec (list vec-start)))
3970 (setq vec-start (- vec-start vec-range)))
3971 (while (<= vec-start vec-end)
3972 (setq vec (append vec (list vec-start)))
3973 (setq vec-start (+ vec-start vec-range))))
3975 ;; Delete current line
3976 (delete-region (point) (progn (forward-line 0) (point)))
3980 (insert (concat sig-head bra
3981 (int-to-string (car vec)) ket sig-tail "\n"))
3982 (setq vec (cdr vec)))
3987 (defun verilog-strip-comments ()
3988 "Strip all comments from the Verilog code."
3990 (goto-char (point-min))
3991 (while (re-search-forward "//" nil t)
3992 (if (verilog-within-string)
3993 (re-search-forward "\"" nil t)
3994 (if (verilog-in-star-comment-p)
3995 (re-search-forward "\*/" nil t)
3996 (let ((bpt (- (point) 2)))
3998 (delete-region bpt (point))))))
4000 (goto-char (point-min))
4001 (while (re-search-forward "/\\*" nil t)
4002 (if (verilog-within-string)
4003 (re-search-forward "\"" nil t)
4004 (let ((bpt (- (point) 2)))
4005 (re-search-forward "\\*/")
4006 (delete-region bpt (point))))))
4008 (defun verilog-one-line ()
4009 "Convert structural Verilog instances to occupy one line."
4011 (goto-char (point-min))
4012 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
4013 (replace-match "\\1 " nil nil)))
4015 (defun verilog-linter-name ()
4016 "Return name of linter, either surelint or verilint."
4017 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4019 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4021 (cond ((equal compile-word1 "surelint") `surelint)
4022 ((equal compile-word1 "verilint") `verilint)
4023 ((equal lint-word1 "surelint") `surelint)
4024 ((equal lint-word1 "verilint") `verilint)
4025 (t `surelint)))) ;; back compatibility
4027 (defun verilog-lint-off ()
4028 "Convert a Verilog linter warning line into a disable statement.
4030 pci_bfm_null.v, line 46: Unused input: pci_rst_
4031 becomes a comment for the appropriate tool.
4033 The first word of the `compile-command' or `verilog-linter'
4034 variables is used to determine which product is being used.
4036 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
4038 (let ((linter (verilog-linter-name)))
4039 (cond ((equal linter `surelint)
4040 (verilog-surelint-off))
4041 ((equal linter `verilint)
4042 (verilog-verilint-off))
4043 (t (error "Linter name not set")))))
4045 (defvar compilation-last-buffer)
4046 (defvar next-error-last-buffer)
4048 (defun verilog-surelint-off ()
4049 "Convert a SureLint warning line into a disable statement.
4050 Run from Verilog source window; assumes there is a *compile* buffer
4051 with point set appropriately.
4054 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
4056 // surefire lint_line_off UDDONX"
4058 (let ((buff (if (boundp 'next-error-last-buffer)
4059 next-error-last-buffer
4060 compilation-last-buffer)))
4061 (when (buffer-live-p buff)
4062 ;; FIXME with-current-buffer?
4064 (switch-to-buffer buff)
4067 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
4068 (let* ((code (match-string 2))
4069 (file (match-string 3))
4070 (line (match-string 4))
4071 (buffer (get-file-buffer file))
4076 (and (file-exists-p file)
4077 (find-file-noselect file)))
4079 (let* ((pop-up-windows t))
4080 (let ((name (expand-file-name
4082 (format "Find this error in: (default %s) "
4085 (if (file-directory-p name)
4086 (setq name (expand-file-name filename name)))
4088 (and (file-exists-p name)
4089 (find-file-noselect name))))))))
4090 (switch-to-buffer buffer)
4091 (goto-char (point-min))
4092 (forward-line (- (string-to-number line)))
4096 ((verilog-in-slash-comment-p)
4097 (re-search-backward "//")
4099 ((looking-at "// surefire lint_off_line ")
4100 (goto-char (match-end 0))
4101 (let ((lim (save-excursion (end-of-line) (point))))
4102 (if (re-search-forward code lim 'move)
4104 (insert (concat " " code)))))
4107 ((verilog-in-star-comment-p)
4108 (re-search-backward "/\*")
4109 (insert (format " // surefire lint_off_line %6s" code )))
4111 (insert (format " // surefire lint_off_line %6s" code ))
4114 (defun verilog-verilint-off ()
4115 "Convert a Verilint warning line into a disable statement.
4118 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
4120 //Verilint 240 off // WARNING: Unused input"
4124 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
4125 (replace-match (format
4126 ;; %3s makes numbers 1-999 line up nicely
4127 "\\1//Verilint %3s off // WARNING: \\3"
4130 (verilog-indent-line))))
4132 (defun verilog-auto-save-compile ()
4133 "Update automatics with \\[verilog-auto], save the buffer, and compile."
4135 (verilog-auto) ; Always do it for safety
4137 (compile compile-command))
4145 (defmacro verilog-batch-error-wrapper (&rest body)
4146 "Execute BODY and add error prefix to any errors found.
4147 This lets programs calling batch mode to easily extract error messages."
4148 `(condition-case err
4151 (error "%%Error: %s%s" (error-message-string err)
4152 (if (featurep 'xemacs) "\n" ""))))) ;; XEmacs forgets to add a newline
4154 (defun verilog-batch-execute-func (funref)
4155 "Internal processing of a batch command, running FUNREF on all command arguments."
4156 (verilog-batch-error-wrapper
4157 ;; Setting global variables like that is *VERY NASTY* !!! --Stef
4158 ;; However, this function is called only when Emacs is being used as
4159 ;; a standalone language instead of as an editor, so we'll live.
4161 ;; General globals needed
4162 (setq make-backup-files nil)
4163 (setq-default make-backup-files nil)
4164 (setq enable-local-variables t)
4165 (setq enable-local-eval t)
4166 ;; Make sure any sub-files we read get proper mode
4167 (setq-default major-mode 'verilog-mode)
4168 ;; Ditto files already read in
4170 (when (buffer-file-name buf)
4171 (with-current-buffer buf
4174 ;; Process the files
4175 (mapcar '(lambda (buf)
4176 (when (buffer-file-name buf)
4178 (if (not (file-exists-p (buffer-file-name buf)))
4180 (concat "File not found: " (buffer-file-name buf))))
4181 (message (concat "Processing " (buffer-file-name buf)))
4187 (defun verilog-batch-auto ()
4188 "For use with --batch, perform automatic expansions as a stand-alone tool.
4189 This sets up the appropriate Verilog mode environment, updates automatics
4190 with \\[verilog-auto] on all command-line files, and saves the buffers.
4191 For proper results, multiple filenames need to be passed on the command
4192 line in bottom-up order."
4193 (unless noninteractive
4194 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
4195 (verilog-batch-execute-func `verilog-auto))
4197 (defun verilog-batch-delete-auto ()
4198 "For use with --batch, perform automatic deletion as a stand-alone tool.
4199 This sets up the appropriate Verilog mode environment, deletes automatics
4200 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
4201 (unless noninteractive
4202 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
4203 (verilog-batch-execute-func `verilog-delete-auto))
4205 (defun verilog-batch-inject-auto ()
4206 "For use with --batch, perform automatic injection as a stand-alone tool.
4207 This sets up the appropriate Verilog mode environment, injects new automatics
4208 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
4209 For proper results, multiple filenames need to be passed on the command
4210 line in bottom-up order."
4211 (unless noninteractive
4212 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
4213 (verilog-batch-execute-func `verilog-inject-auto))
4215 (defun verilog-batch-indent ()
4216 "For use with --batch, reindent an a entire file as a stand-alone tool.
4217 This sets up the appropriate Verilog mode environment, calls
4218 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
4219 (unless noninteractive
4220 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
4221 (verilog-batch-execute-func `verilog-indent-buffer))
4227 (defconst verilog-indent-alist
4228 '((block . (+ ind verilog-indent-level))
4229 (case . (+ ind verilog-case-indent))
4230 (cparenexp . (+ ind verilog-indent-level))
4231 (cexp . (+ ind verilog-cexp-indent))
4232 (defun . verilog-indent-level-module)
4233 (declaration . verilog-indent-level-declaration)
4234 (directive . (verilog-calculate-indent-directive))
4235 (tf . verilog-indent-level)
4236 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
4239 (comment . (verilog-comment-indent))
4243 (defun verilog-continued-line-1 (lim)
4244 "Return true if this is a continued line.
4245 Set point to where line starts. Limit search to point LIM."
4246 (let ((continued 't))
4247 (if (eq 0 (forward-line -1))
4250 (verilog-backward-ws&directives lim)
4252 (setq continued nil)
4253 (setq continued (verilog-backward-token))))
4254 (setq continued nil))
4257 (defun verilog-calculate-indent ()
4258 "Calculate the indent of the current Verilog line.
4259 Examine previous lines. Once a line is found that is definitive as to the
4260 type of the current line, return that lines' indent level and its type.
4261 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
4263 (let* ((starting_position (point))
4265 (begin (looking-at "[ \t]*begin\\>"))
4266 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
4267 (type (catch 'nesting
4268 ;; Keep working backwards until we can figure out
4269 ;; what type of statement this is.
4270 ;; Basically we need to figure out
4271 ;; 1) if this is a continuation of the previous line;
4272 ;; 2) are we in a block scope (begin..end)
4274 ;; if we are in a comment, done.
4275 (if (verilog-in-star-comment-p)
4276 (throw 'nesting 'comment))
4278 ;; if we have a directive, done.
4279 (if (save-excursion (beginning-of-line)
4280 (and (looking-at verilog-directive-re-1)
4281 (not (looking-at "[ \t]*`ovm_"))))
4282 (throw 'nesting 'directive))
4283 ;; indent structs as if there were module level
4284 (if (verilog-in-struct-p)
4285 (throw 'nesting 'block))
4287 ;; unless we are in the newfangled coverpoint or constraint blocks
4288 ;; if we are in a parenthesized list, and the user likes to indent these, return.
4290 verilog-indent-lists
4292 (not (verilog-in-coverage-p))
4295 (throw 'nesting 'block)))
4297 ;; See if we are continuing a previous line
4299 ;; trap out if we crawl off the top of the buffer
4300 (if (bobp) (throw 'nesting 'cpp))
4302 (if (verilog-continued-line-1 lim)
4305 (not (looking-at verilog-complete-reg))
4306 (verilog-continued-line-1 lim))
4307 (progn (goto-char sp)
4308 (throw 'nesting 'cexp))
4313 (not verilog-indent-begin-after-if)
4314 (looking-at verilog-no-indent-begin-re))
4317 (skip-chars-forward " \t")
4318 (throw 'nesting 'statement))
4320 (throw 'nesting 'cexp))))
4321 ;; not a continued line
4322 (goto-char starting_position))
4324 (if (looking-at "\\<else\\>")
4325 ;; search back for governing if, striding across begin..end pairs
4328 (while (verilog-re-search-backward verilog-ends-re nil 'move)
4330 ((match-end 1) ; else, we're in deep
4331 (setq elsec (1+ elsec)))
4333 (setq elsec (1- elsec))
4335 (if verilog-align-ifelse
4336 (throw 'nesting 'statement)
4337 (progn ;; back up to first word on this line
4339 (verilog-forward-syntactic-ws)
4340 (throw 'nesting 'statement)))))
4342 ; try to leap back to matching outward block by striding across
4343 ; indent level changing tokens then immediately
4344 ; previous line governs indentation.
4345 (let (( reg) (nest 1))
4346 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
4348 ((match-end 3) ; end
4349 ;; Search back for matching begin
4350 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
4351 ((match-end 4) ; endcase
4352 ;; Search back for matching case
4353 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
4354 ((match-end 5) ; endfunction
4355 ;; Search back for matching function
4356 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
4357 ((match-end 6) ; endtask
4358 ;; Search back for matching task
4359 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
4360 ((match-end 7) ; endspecify
4361 ;; Search back for matching specify
4362 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
4363 ((match-end 8) ; endtable
4364 ;; Search back for matching table
4365 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
4366 ((match-end 9) ; endgenerate
4367 ;; Search back for matching generate
4368 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
4369 ((match-end 10) ; joins
4370 ;; Search back for matching fork
4371 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
4372 ((match-end 11) ; class
4373 ;; Search back for matching class
4374 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
4375 ((match-end 12) ; covergroup
4376 ;; Search back for matching covergroup
4377 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
4379 (while (verilog-re-search-backward reg nil 'move)
4381 ((match-end 1) ; begin
4382 (setq nest (1- nest))
4385 ((match-end 2) ; end
4386 (setq nest (1+ nest)))))
4388 (throw 'nesting (verilog-calc-1)))
4392 ;; Return type of block and indent level.
4395 (if (> par 0) ; Unclosed Parenthesis
4396 (list 'cparenexp par)
4399 (list type (verilog-case-indent-level)))
4400 ((eq type 'statement)
4401 (list type (current-column)))
4405 (list type (verilog-current-indent-level))))))))
4407 (defun verilog-wai ()
4408 "Show matching nesting block for debugging."
4411 (let* ((type (verilog-calc-1))
4413 ;; Return type of block and indent level.
4417 verilog-indent-lists
4418 (not(or (verilog-in-coverage-p)
4419 (verilog-in-struct-p)))
4424 (setq depth (verilog-case-indent-level)))
4425 ((eq type 'statement)
4426 (setq depth (current-column)))
4430 (setq depth (verilog-current-indent-level)))))
4431 (message "You are at nesting %s depth %d" type depth))))
4433 (defun verilog-calc-1 ()
4435 (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)")))
4436 (while (verilog-re-search-backward re nil 'move)
4439 ((equal (char-after) ?\{)
4440 (if (verilog-at-constraint-p)
4441 (throw 'nesting 'block)))
4443 ((equal (char-after) ?\})
4444 (let ((there (verilog-at-close-constraint-p)))
4445 (if there ;; we are at the } that closes a constraing. Find the { that opens it
4449 (verilog-beg-of-statement)))))
4451 ((looking-at verilog-beg-block-re-ordered)
4453 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
4454 (let ((here (point)))
4455 (verilog-beg-of-statement)
4456 (if (looking-at verilog-extended-case-re)
4457 (throw 'nesting 'case)
4459 (throw 'nesting 'case))
4461 ((match-end 4) ; *sigh* could be "disable fork"
4462 (let ((here (point)))
4463 (verilog-beg-of-statement)
4464 (if (looking-at verilog-disable-fork-re)
4465 t ; is disable fork, this is a normal statement
4466 (progn ; or is fork, starts a new block
4468 (throw 'nesting 'block)))))
4471 ;; need to consider typedef struct here...
4472 ((looking-at "\\<class\\|struct\\|function\\|task\\>")
4473 ; *sigh* These words have an optional prefix:
4474 ; extern {virtual|protected}? function a();
4475 ; typedef class foo;
4476 ; and we don't want to confuse this with
4481 (verilog-beg-of-statement)
4482 (if (looking-at verilog-beg-block-re-ordered)
4483 (throw 'nesting 'block)
4484 (throw 'nesting 'defun)))
4486 ((looking-at "\\<property\\>")
4488 ; {assert|assume|cover} property (); are complete
4489 ; and could also be labeled: - foo: assert property
4491 ; property ID () ... needs end_property
4492 (verilog-beg-of-statement)
4493 (if (looking-at (concat "\\(" verilog-label-re "\\)?"
4494 "\\(assert\\|assume\\|cover\\)\\s-+property\\>"))
4495 (throw 'continue 'statement) ; We don't need an endproperty for these
4496 (throw 'nesting 'block) ;We still need a endproperty
4499 (t (throw 'nesting 'block))))
4501 ((looking-at verilog-end-block-re)
4502 (verilog-leap-to-head)
4503 (if (verilog-in-case-region-p)
4505 (verilog-leap-to-case-head)
4506 (if (looking-at verilog-extended-case-re)
4507 (throw 'nesting 'case)))))
4509 ((looking-at verilog-defun-level-re)
4510 (if (looking-at verilog-defun-level-generate-only-re)
4511 (if (verilog-in-generate-region-p)
4512 (throw 'continue 'foo) ; always block in a generate - keep looking
4513 (throw 'nesting 'defun))
4514 (throw 'nesting 'defun)))
4516 ((looking-at verilog-cpp-level-re)
4517 (throw 'nesting 'cpp))
4520 (throw 'nesting 'cpp)))))
4522 (throw 'nesting 'cpp))))
4524 (defun verilog-calculate-indent-directive ()
4525 "Return indentation level for directive.
4526 For speed, the searcher looks at the last directive, not the indent
4527 of the appropriate enclosing block."
4528 (let ((base -1) ;; Indent of the line that determines our indentation
4529 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else)
4530 ;; Start at current location, scan back for another directive
4534 (while (and (< base 0)
4535 (verilog-re-search-backward verilog-directive-re nil t))
4536 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
4537 (setq base (current-indentation))))
4538 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
4539 (setq ind (- ind verilog-indent-level-directive)))
4540 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
4541 (setq ind (+ ind verilog-indent-level-directive)))
4542 ((looking-at verilog-directive-begin)
4543 (setq ind (+ ind verilog-indent-level-directive)))))
4544 ;; Adjust indent to starting indent of critical line
4545 (setq ind (max 0 (+ ind base))))
4549 (skip-chars-forward " \t")
4550 (cond ((or (looking-at verilog-directive-middle)
4551 (looking-at verilog-directive-end))
4552 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
4555 (defun verilog-leap-to-case-head ()
4558 (verilog-re-search-backward
4560 "\\(\\<randcase\\>\\|\\(\\<unique\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
4561 "\\|\\(\\<endcase\\>\\)" )
4565 (let ((here (point)))
4566 (verilog-beg-of-statement)
4567 (unless (looking-at verilog-extended-case-re)
4569 (setq nest (1- nest)))
4571 (setq nest (1+ nest)))
4576 (defun verilog-leap-to-head ()
4577 "Move point to the head of this block.
4578 Jump from end to matching begin, from endcase to matching case, and so on."
4584 ((looking-at "\\<end\\>")
4585 ;; 1: Search back for matching begin
4586 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
4587 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
4588 ((looking-at "\\<endtask\\>")
4589 ;; 2: Search back for matching task
4590 (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
4592 ((looking-at "\\<endcase\\>")
4594 (verilog-leap-to-case-head) )
4595 (setq reg nil) ; to force skip
4598 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
4599 ;; 4: Search back for matching fork
4600 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
4601 ((looking-at "\\<endclass\\>")
4602 ;; 5: Search back for matching class
4603 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
4604 ((looking-at "\\<endtable\\>")
4605 ;; 6: Search back for matching table
4606 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
4607 ((looking-at "\\<endspecify\\>")
4608 ;; 7: Search back for matching specify
4609 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
4610 ((looking-at "\\<endfunction\\>")
4611 ;; 8: Search back for matching function
4612 (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
4614 ;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
4615 ((looking-at "\\<endgenerate\\>")
4616 ;; 8: Search back for matching generate
4617 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
4618 ((looking-at "\\<endgroup\\>")
4619 ;; 10: Search back for matching covergroup
4620 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
4621 ((looking-at "\\<endproperty\\>")
4622 ;; 11: Search back for matching property
4623 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
4624 ((looking-at verilog-ovm-end-re)
4625 ;; 12: Search back for matching sequence
4626 (setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
4627 ((looking-at "\\<endinterface\\>")
4628 ;; 12: Search back for matching interface
4629 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
4630 ((looking-at "\\<endsequence\\>")
4631 ;; 12: Search back for matching sequence
4632 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
4633 ((looking-at "\\<endclocking\\>")
4634 ;; 12: Search back for matching clocking
4635 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
4638 (if (eq nesting 'yes)
4640 (while (verilog-re-search-backward reg nil 'move)
4642 ((match-end 1) ; begin
4643 (if (looking-at "fork")
4644 (let ((here (point)))
4645 (verilog-beg-of-statement)
4646 (unless (looking-at verilog-disable-fork-re)
4648 (setq nest (1- nest))))
4649 (setq nest (1- nest)))
4651 ;; Now previous line describes syntax
4656 ((match-end 2) ; end
4657 (setq nest (1+ nest)))
4659 ;; endcase, jump to case
4661 (setq nest (1+ nest))
4663 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
4665 ;; join, jump to fork
4667 (setq nest (1+ nest))
4669 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
4673 (verilog-re-search-backward reg nil 'move)
4674 (match-end 1)) ; task -> could be virtual and/or protected
4676 (verilog-beg-of-statement)
4678 (throw 'skip 1)))))))
4680 (defun verilog-continued-line ()
4681 "Return true if this is a continued line.
4682 Set point to where line starts."
4683 (let ((continued 't))
4684 (if (eq 0 (forward-line -1))
4687 (verilog-backward-ws&directives)
4689 (setq continued nil)
4690 (while (and continued
4692 (skip-chars-backward " \t")
4694 (setq continued (verilog-backward-token)))))
4695 (setq continued nil))
4698 (defun verilog-backward-token ()
4699 "Step backward token, returing true if this is a continued line."
4701 (verilog-backward-syntactic-ws)
4705 (;-- Anything ending in a ; is complete
4706 (= (preceding-char) ?\;)
4708 (; If a "}" is prefixed by a ";", then this is a complete statement
4709 ; i.e.: constraint foo { a = b; }
4710 (= (preceding-char) ?\})
4713 (not(verilog-at-close-constraint-p))))
4714 (;-- constraint foo { a = b }
4715 ; is a complete statement. *sigh*
4716 (= (preceding-char) ?\{)
4719 (not (verilog-at-constraint-p))))
4721 (= (preceding-char) ?\")
4723 (verilog-skip-backward-comment-or-string)
4727 (= (preceding-char) ?\])
4729 (verilog-backward-open-bracket)
4732 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
4733 ; also could be simply '@(foo)'
4735 ; (b, ... which ISN'T complete
4736 ;;;; Do we need this???
4737 (= (preceding-char) ?\))
4740 (backward-up-list 1)
4741 (verilog-backward-syntactic-ws)
4742 (let ((back (point)))
4746 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
4747 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
4748 ((looking-at verilog-ovm-statement-re)
4750 ((looking-at verilog-ovm-begin-re)
4752 ((looking-at verilog-ovm-end-re)
4757 ((= (preceding-char) ?\@)
4760 (verilog-backward-token)
4761 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
4762 ((= (preceding-char) ?\#)
4766 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
4769 (while (= (preceding-char) ?\_)
4772 ((looking-at "\\<else\\>")
4774 ((looking-at verilog-behavioral-block-beg-re)
4776 ((looking-at verilog-indent-re)
4781 (verilog-backward-syntactic-ws)
4783 ((= (preceding-char) ?\:)
4785 (verilog-backward-syntactic-ws)
4787 (if (looking-at verilog-nameable-item-re )
4790 ((= (preceding-char) ?\#)
4793 ((= (preceding-char) ?\`)
4801 (defun verilog-backward-syntactic-ws (&optional bound)
4802 "Backward skip over syntactic whitespace for Emacs 19.
4803 Optional BOUND limits search."
4805 (let* ((bound (or bound (point-min))) (here bound) )
4806 (if (< bound (point))
4808 (narrow-to-region bound (point))
4809 (while (/= here (point))
4811 (verilog-skip-backward-comments))))))
4814 (defun verilog-forward-syntactic-ws (&optional bound)
4815 "Forward skip over syntactic whitespace for Emacs 19.
4816 Optional BOUND limits search."
4818 (let* ((bound (or bound (point-max)))
4820 (if (> bound (point))
4822 (narrow-to-region (point) bound)
4823 (while (/= here (point))
4825 (forward-comment (buffer-size))))))))
4827 (defun verilog-backward-ws&directives (&optional bound)
4828 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
4829 Optional BOUND limits search."
4831 (let* ((bound (or bound (point-min)))
4834 (if (< bound (point))
4836 (let ((state (save-excursion (verilog-syntax-ppss))))
4838 ((nth 7 state) ;; in // comment
4839 (verilog-re-search-backward "//" nil 'move)
4840 (skip-chars-backward "/"))
4841 ((nth 4 state) ;; in /* */ comment
4842 (verilog-re-search-backward "/\*" nil 'move))))
4843 (narrow-to-region bound (point))
4844 (while (/= here (point))
4846 (verilog-skip-backward-comments)
4851 ((and verilog-highlight-translate-off
4852 (verilog-within-translate-off))
4853 (verilog-back-to-start-translate-off (point-min)))
4854 ((looking-at verilog-directive-re-1)
4858 (if p (goto-char p))))))))
4860 (defun verilog-forward-ws&directives (&optional bound)
4861 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
4862 Optional BOUND limits search."
4864 (let* ((bound (or bound (point-max)))
4867 (if (> bound (point))
4869 (let ((state (save-excursion (verilog-syntax-ppss))))
4871 ((nth 7 state) ;; in // comment
4872 (verilog-re-search-forward "//" nil 'move))
4873 ((nth 4 state) ;; in /* */ comment
4874 (verilog-re-search-forward "/\*" nil 'move))))
4875 (narrow-to-region (point) bound)
4876 (while (/= here (point))
4879 (forward-comment (buffer-size))
4882 (if (looking-at verilog-directive-re-1)
4885 (beginning-of-line 2))))))))
4887 (defun verilog-in-comment-p ()
4888 "Return true if in a star or // comment."
4889 (let ((state (save-excursion (verilog-syntax-ppss))))
4890 (or (nth 4 state) (nth 7 state))))
4892 (defun verilog-in-star-comment-p ()
4893 "Return true if in a star comment."
4894 (let ((state (save-excursion (verilog-syntax-ppss))))
4896 (nth 4 state) ; t if in a comment of style a // or b /**/
4898 (nth 7 state) ; t if in a comment of style b /**/
4901 (defun verilog-in-slash-comment-p ()
4902 "Return true if in a slash comment."
4903 (let ((state (save-excursion (verilog-syntax-ppss))))
4906 (defun verilog-in-comment-or-string-p ()
4907 "Return true if in a string or comment."
4908 (let ((state (save-excursion (verilog-syntax-ppss))))
4909 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
4911 (defun verilog-in-escaped-name-p ()
4912 "Return true if in an escaped name."
4915 (skip-chars-backward "^ \t\n\f")
4916 (if (equal (char-after (point) ) ?\\ )
4919 (defun verilog-in-directive-p ()
4920 "Return true if in a star or // comment."
4923 (looking-at verilog-directive-re-1)))
4925 (defun verilog-in-paren ()
4926 "Return true if in a parenthetical expression."
4927 (let ((state (save-excursion (verilog-syntax-ppss))))
4928 (> (nth 0 state) 0 )))
4930 (defun verilog-in-struct-p ()
4931 "Return true if in a struct declaration."
4934 (if (verilog-in-paren)
4936 (backward-up-list 1)
4937 (verilog-at-struct-p)
4941 (defun verilog-in-coverage-p ()
4942 "Return true if in a constraint or coverpoint expression."
4945 (if (verilog-in-paren)
4947 (backward-up-list 1)
4948 (verilog-at-constraint-p)
4951 (defun verilog-at-close-constraint-p ()
4952 "If at the } that closes a constraint or covergroup, return true."
4954 (equal (char-after) ?\})
4958 (verilog-backward-ws&directives)
4959 (if (equal (char-before) ?\;)
4963 (defun verilog-at-constraint-p ()
4964 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
4967 (equal (char-after) ?\{)
4969 (progn (backward-char 1)
4970 (verilog-backward-ws&directives)
4971 (equal (char-before) ?\;))))
4973 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move)
4977 (defun verilog-at-struct-p ()
4978 "If at the { of a struct, return true, moving point to struct."
4980 (if (and (equal (char-after) ?\{)
4981 (verilog-backward-token))
4982 (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
4985 (defun verilog-parenthesis-depth ()
4986 "Return non zero if in parenthetical-expression."
4987 (save-excursion (nth 1 (verilog-syntax-ppss))))
4990 (defun verilog-skip-forward-comment-or-string ()
4991 "Return true if in a string or comment."
4992 (let ((state (save-excursion (verilog-syntax-ppss))))
4994 ((nth 3 state) ;Inside string
4995 (search-forward "\"")
4997 ((nth 7 state) ;Inside // comment
5000 ((nth 4 state) ;Inside any comment (hence /**/)
5001 (search-forward "*/"))
5005 (defun verilog-skip-backward-comment-or-string ()
5006 "Return true if in a string or comment."
5007 (let ((state (save-excursion (verilog-syntax-ppss))))
5009 ((nth 3 state) ;Inside string
5010 (search-backward "\"")
5012 ((nth 7 state) ;Inside // comment
5013 (search-backward "//")
5014 (skip-chars-backward "/")
5016 ((nth 4 state) ;Inside /* */ comment
5017 (search-backward "/*")
5022 (defun verilog-skip-backward-comments ()
5023 "Return true if a comment was skipped."
5027 (let ((state (save-excursion (verilog-syntax-ppss))))
5029 ((nth 7 state) ;Inside // comment
5030 (search-backward "//")
5031 (skip-chars-backward "/")
5032 (skip-chars-backward " \t\n\f")
5034 ((nth 4 state) ;Inside /* */ comment
5035 (search-backward "/*")
5036 (skip-chars-backward " \t\n\f")
5039 (= (char-before) ?\/)
5040 (= (char-before (1- (point))) ?\*))
5041 (goto-char (- (point) 2))
5044 (skip-chars-backward " \t\n\f")
5047 (defun verilog-skip-forward-comment-p ()
5048 "If in comment, move to end and return true."
5051 (setq state (save-excursion (verilog-syntax-ppss)))
5055 ((nth 7 state) ;Inside // comment
5059 ((nth 4 state) ;Inside any comment
5064 (defun verilog-indent-line-relative ()
5065 "Cheap version of indent line.
5066 Only look at a few lines to determine indent level."
5070 (if (looking-at "^[ \t]*$")
5071 (cond ;- A blank line; No need to be too smart.
5073 (setq indent-str (list 'cpp 0)))
5074 ((verilog-continued-line)
5075 (let ((sp1 (point)))
5076 (if (verilog-continued-line)
5080 (list 'statement (verilog-current-indent-level))))
5082 (setq indent-str (list 'block (verilog-current-indent-level)))))
5085 (setq indent-str (verilog-calculate-indent))))
5086 (progn (skip-chars-forward " \t")
5087 (setq indent-str (verilog-calculate-indent))))
5088 (verilog-do-indent indent-str)))
5090 (defun verilog-indent-line ()
5091 "Indent for special part of code."
5092 (verilog-do-indent (verilog-calculate-indent)))
5094 (defun verilog-do-indent (indent-str)
5095 (let ((type (car indent-str))
5096 (ind (car (cdr indent-str))))
5098 (; handle continued exp
5100 (let ((here (point)))
5101 (verilog-backward-syntactic-ws)
5104 (= (preceding-char) ?\,)
5105 (= (preceding-char) ?\])
5107 (verilog-beg-of-statement-1)
5108 (looking-at verilog-declaration-re)))
5113 (verilog-beg-of-statement-1)
5115 (if (looking-at verilog-declaration-re)
5116 (progn ;; we have multiple words
5117 (goto-char (match-end 0))
5118 (skip-chars-forward " \t")
5120 ((and verilog-indent-declaration-macros
5121 (= (following-char) ?\`))
5125 (skip-chars-forward " \t")))
5126 ((= (following-char) ?\[)
5129 (backward-up-list -1)
5130 (skip-chars-forward " \t"))))
5134 (+ (current-column) verilog-cexp-indent))))))
5136 (indent-line-to val)))
5137 ((= (preceding-char) ?\) )
5139 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
5140 (indent-line-to val)))
5144 (verilog-beg-of-statement-1)
5145 (if (and (< (point) here)
5146 (verilog-re-search-forward "=[ \\t]*" here 'move))
5147 (setq val (current-column))
5148 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
5150 (indent-line-to val))))))
5152 (; handle inside parenthetical expressions
5153 (eq type 'cparenexp)
5154 (let ((val (save-excursion
5155 (backward-up-list 1)
5157 (skip-chars-forward " \t")
5159 (indent-line-to val)
5162 (;-- Handle the ends
5164 (looking-at verilog-end-block-re )
5165 (verilog-at-close-constraint-p))
5166 (let ((val (if (eq type 'statement)
5167 (- ind verilog-indent-level)
5169 (indent-line-to val)))
5171 (;-- Case -- maybe line 'em up
5172 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
5175 ((looking-at "\\<endcase\\>")
5176 (indent-line-to ind))
5178 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
5179 (indent-line-to val))))))
5182 (and (eq type 'defun)
5183 (looking-at verilog-zero-indent-re))
5190 (looking-at verilog-declaration-re))
5191 (verilog-indent-declaration ind))
5193 (;-- Everything else
5195 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
5196 (indent-line-to val))))
5198 (if (looking-at "[ \t]+$")
5199 (skip-chars-forward " \t"))
5200 indent-str ; Return indent data
5203 (defun verilog-current-indent-level ()
5204 "Return the indent-level of the current statement."
5208 (setq par-pos (verilog-parenthesis-depth))
5212 (setq par-pos (verilog-parenthesis-depth)))
5213 (skip-chars-forward " \t")
5216 (defun verilog-case-indent-level ()
5217 "Return the indent-level of the current statement.
5218 Do not count named blocks or case-statements."
5220 (skip-chars-forward " \t")
5222 ((looking-at verilog-named-block-re)
5224 ((and (not (looking-at verilog-extended-case-re))
5225 (looking-at "^[^:;]+[ \t]*:"))
5226 (verilog-re-search-forward ":" nil t)
5227 (skip-chars-forward " \t")
5230 (current-column)))))
5232 (defun verilog-indent-comment ()
5233 "Indent current line as comment."
5236 ((verilog-in-star-comment-p)
5238 (re-search-backward "/\\*" nil t)
5239 (1+(current-column))))
5244 (re-search-backward "//" nil t)
5245 (current-column))))))
5246 (indent-line-to stcol)
5249 (defun verilog-more-comment ()
5250 "Make more comment lines like the previous."
5254 ((verilog-in-star-comment-p)
5257 (re-search-backward "/\\*" nil t)
5258 (1+(current-column))))
5263 (re-search-backward "//" nil t)
5264 (current-column))))))
5270 (skip-chars-forward " \t")
5274 (defun verilog-comment-indent (&optional arg)
5275 "Return the column number the line should be indented to.
5276 ARG is ignored, for `comment-indent-function' compatibility."
5278 ((verilog-in-star-comment-p)
5280 (re-search-backward "/\\*" nil t)
5281 (1+(current-column))))
5286 (re-search-backward "//" nil t)
5287 (current-column)))))
5291 (defun verilog-pretty-declarations (&optional quiet)
5292 "Line up declarations around point.
5293 Be verbose about progress unless optional QUIET set."
5297 (verilog-beg-of-statement-1)
5298 (and (not (verilog-in-directive-p)) ;; could have `define input foo
5299 (not (verilog-parenthesis-depth)) ;; could be in a #(param block )
5300 (looking-at verilog-declaration-re)))
5301 (let* ((m1 (make-marker))
5305 ;; Start of declaration range
5308 (verilog-beg-of-statement-1)
5309 (while (and (looking-at verilog-declaration-re)
5311 (skip-chars-backward " \t")
5314 (verilog-backward-syntactic-ws)
5316 (verilog-beg-of-statement-1))
5318 ;; End of declaration range
5322 (verilog-end-of-statement)
5323 (setq e (point)) ;Might be on last line
5324 (verilog-forward-syntactic-ws)
5325 (while (looking-at verilog-declaration-re)
5326 ;;(beginning-of-line)
5327 (verilog-end-of-statement)
5329 (verilog-forward-syntactic-ws))
5331 (edpos (set-marker (make-marker) end))
5336 (verilog-do-indent (verilog-calculate-indent))
5337 (verilog-forward-ws&directives)
5340 (if (and (not quiet)
5341 (> (- end start) 100))
5342 (message "Lining up declarations..(please stand by)"))
5343 ;; Get the beginning of line indent first
5344 (while (progn (setq e (marker-position edpos))
5347 ( (save-excursion (skip-chars-backward " \t")
5349 (verilog-forward-ws&directives)
5350 (indent-line-to base-ind)
5351 (verilog-forward-ws&directives)
5352 (verilog-re-search-forward "[ \t\n\f]" e 'move))
5355 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
5358 ;; Now find biggest prefix
5359 (setq ind (verilog-get-lineup-indent start edpos))
5360 ;; Now indent each line.
5362 (while (progn (setq e (marker-position edpos))
5363 (setq r (- e (point)))
5366 (unless quiet (message "%d" r))
5367 (verilog-indent-line)
5369 ((or (and verilog-indent-declaration-macros
5370 (looking-at verilog-declaration-re-2-macro))
5371 (looking-at verilog-declaration-re-2-no-macro))
5372 (let ((p (match-end 0)))
5374 (if (verilog-re-search-forward "[[#`]" p 'move)
5378 (goto-char (marker-position m1))
5384 ((verilog-continued-line-1 start)
5386 (indent-line-to ind))
5387 ((verilog-in-struct-p)
5388 ;; could have a declaration of a user defined item
5390 (verilog-end-of-statement))
5391 (t ; Must be comment or white space
5393 (verilog-forward-ws&directives)
5396 (unless quiet (message ""))))))
5398 (defun verilog-pretty-expr (&optional quiet myre)
5399 "Line up expressions around point, optionally QUIET with regexp MYRE."
5400 (interactive "sRegular Expression: ((<|:)?=) ")
5402 (if (or (eq myre nil)
5403 (string-equal myre ""))
5404 (setq myre "\\(<\\|:\\)?="))
5405 (setq myre (concat "\\(^[^;#:<=>]*\\)\\(" myre "\\)"))
5406 (let ((rexp(concat "^\\s-*" verilog-complete-reg)))
5408 (if (and (not (looking-at rexp ))
5411 (goto-char (match-beginning 2))
5412 (not (verilog-in-comment-or-string-p))))
5413 (let* ((here (point))
5419 (verilog-backward-syntactic-ws)
5421 (while (and (not (looking-at rexp ))
5426 (verilog-backward-syntactic-ws)
5428 ) ;Ack, need to grok `define
5434 (setq e (point)) ;Might be on last line
5435 (verilog-forward-syntactic-ws)
5438 (not (looking-at rexp ))
5442 (not (eq e (point)))))
5444 (verilog-forward-syntactic-ws)
5448 (edpos (set-marker (make-marker) end))
5452 (verilog-do-indent (verilog-calculate-indent))
5453 (if (and (not quiet)
5454 (> (- end start) 100))
5455 (message "Lining up expressions..(please stand by)"))
5457 ;; Set indent to minimum throughout region
5458 (while (< (point) (marker-position edpos))
5460 (verilog-just-one-space myre)
5462 (verilog-forward-syntactic-ws)
5465 ;; Now find biggest prefix
5466 (setq ind (verilog-get-lineup-indent-2 myre start edpos))
5468 ;; Now indent each line.
5470 (while (progn (setq e (marker-position edpos))
5471 (setq r (- e (point)))
5474 (if (not quiet) (message "%d" r))
5477 (goto-char (match-beginning 2))
5478 (if (not (verilog-parenthesis-depth)) ;; ignore parenthsized exprs
5479 (if (eq (char-after) ?=)
5480 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
5483 ((verilog-continued-line-1 start)
5485 (indent-line-to ind))
5486 (t ; Must be comment or white space
5488 (verilog-forward-ws&directives)
5492 (unless quiet (message ""))
5495 (defun verilog-just-one-space (myre)
5496 "Remove extra spaces around regular expression MYRE."
5498 (if (and (not(looking-at verilog-complete-reg))
5500 (let ((p1 (match-end 1))
5504 (if (looking-at "\\s-") (just-one-space))
5507 (if (looking-at "\\s-") (just-one-space))
5510 (defun verilog-indent-declaration (baseind)
5511 "Indent current lines as declaration.
5512 Line up the variable names based on previous declaration's indentation.
5513 BASEIND is the base indent to offset everything."
5515 (let ((pos (point-marker))
5516 (lim (save-excursion
5517 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
5518 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
5524 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
5525 (indent-line-to val)
5527 ;; Use previous declaration (in this module) as template.
5528 (if (or (eq 'all verilog-auto-lineup)
5529 (eq 'declarations verilog-auto-lineup))
5530 (if (verilog-re-search-backward
5531 (or (and verilog-indent-declaration-macros
5532 verilog-declaration-re-1-macro)
5533 verilog-declaration-re-1-no-macro) lim t)
5535 (goto-char (match-end 0))
5536 (skip-chars-forward " \t")
5537 (setq ind (current-column))
5541 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
5542 (indent-line-to val)
5543 (if (and verilog-indent-declaration-macros
5544 (looking-at verilog-declaration-re-2-macro))
5545 (let ((p (match-end 0)))
5547 (if (verilog-re-search-forward "[[#`]" p 'move)
5551 (goto-char (marker-position m1))
5554 (if (/= (current-column) ind)
5558 (if (looking-at verilog-declaration-re-2-no-macro)
5559 (let ((p (match-end 0)))
5561 (if (verilog-re-search-forward "[[`#]" p 'move)
5565 (goto-char (marker-position m1))
5568 (if (/= (current-column) ind)
5571 (indent-to ind))))))))))
5574 (defun verilog-get-lineup-indent (b edpos)
5575 "Return the indent level that will line up several lines within the region.
5576 Region is defined by B and EDPOS."
5580 ;; Get rightmost position
5581 (while (progn (setq e (marker-position edpos))
5583 (if (verilog-re-search-forward
5584 (or (and verilog-indent-declaration-macros
5585 verilog-declaration-re-1-macro)
5586 verilog-declaration-re-1-no-macro) e 'move)
5588 (goto-char (match-end 0))
5589 (verilog-backward-syntactic-ws)
5590 (if (> (current-column) ind)
5591 (setq ind (current-column)))
5592 (goto-char (match-end 0)))))
5595 ;; No lineup-string found
5598 (skip-chars-backward " \t")
5599 (1+ (current-column))))))
5601 (defun verilog-get-lineup-indent-2 (myre b edpos)
5602 "Return the indent level that will line up several lines within the region."
5606 ;; Get rightmost position
5607 (while (progn (setq e (marker-position edpos))
5609 (if (and (verilog-re-search-forward myre e 'move)
5610 (not (verilog-parenthesis-depth))) ;; skip parenthsized exprs
5612 (goto-char (match-beginning 2))
5613 (verilog-backward-syntactic-ws)
5614 (if (> (current-column) ind)
5615 (setq ind (current-column)))
5616 (goto-char (match-end 0)))
5620 ;; No lineup-string found
5623 (skip-chars-backward " \t")
5624 (1+ (current-column))))))
5626 (defun verilog-comment-depth (type val)
5627 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
5635 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
5637 (replace-match " /* -# ## */")
5641 (insert " /* ## ## */"))))
5644 (format "%s %d" type val))))
5650 (defvar verilog-str nil)
5651 (defvar verilog-all nil)
5652 (defvar verilog-pred nil)
5653 (defvar verilog-buffer-to-use nil)
5654 (defvar verilog-flag nil)
5655 (defvar verilog-toggle-completions nil
5656 "*True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
5657 Repeated use of \\[verilog-complete-word] will show you all of them.
5658 Normally, when there is more than one possible completion,
5659 it displays a list of all possible completions.")
5662 (defvar verilog-type-keywords
5664 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
5665 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
5666 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pullup"
5667 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
5668 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
5669 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
5671 "*Keywords for types used when completing a word in a declaration or parmlist.
5672 \(integer, real, reg...)")
5674 (defvar verilog-cpp-keywords
5675 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
5677 "*Keywords to complete when at first word of a line in declarative scope.
5678 \(initial, always, begin, assign...)
5679 The procedures and variables defined within the Verilog program
5680 will be completed at runtime and should not be added to this list.")
5682 (defvar verilog-defun-keywords
5685 "always" "always_comb" "always_ff" "always_latch" "assign"
5686 "begin" "end" "generate" "endgenerate" "module" "endmodule"
5687 "specify" "endspecify" "function" "endfunction" "initial" "final"
5688 "task" "endtask" "primitive" "endprimitive"
5690 verilog-type-keywords)
5691 "*Keywords to complete when at first word of a line in declarative scope.
5692 \(initial, always, begin, assign...)
5693 The procedures and variables defined within the Verilog program
5694 will be completed at runtime and should not be added to this list.")
5696 (defvar verilog-block-keywords
5698 "begin" "break" "case" "continue" "else" "end" "endfunction"
5699 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
5700 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
5702 "*Keywords to complete when at first word of a line in behavioral scope.
5703 \(begin, if, then, else, for, fork...)
5704 The procedures and variables defined within the Verilog program
5705 will be completed at runtime and should not be added to this list.")
5707 (defvar verilog-tf-keywords
5708 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
5709 "*Keywords to complete when at first word of a line in a task or function.
5710 \(begin, if, then, else, for, fork.)
5711 The procedures and variables defined within the Verilog program
5712 will be completed at runtime and should not be added to this list.")
5714 (defvar verilog-case-keywords
5715 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
5716 "*Keywords to complete when at first word of a line in case scope.
5717 \(begin, if, then, else, for, fork...)
5718 The procedures and variables defined within the Verilog program
5719 will be completed at runtime and should not be added to this list.")
5721 (defvar verilog-separator-keywords
5722 '("else" "then" "begin")
5723 "*Keywords to complete when NOT standing at the first word of a statement.
5724 \(else, then, begin...)
5725 Variables and function names defined within the Verilog program
5726 will be completed at runtime and should not be added to this list.")
5728 (defun verilog-string-diff (str1 str2)
5729 "Return index of first letter where STR1 and STR2 differs."
5733 (if (or (> (1+ diff) (length str1))
5734 (> (1+ diff) (length str2)))
5736 (or (equal (aref str1 diff) (aref str2 diff))
5738 (setq diff (1+ diff))))))
5740 ;; Calculate all possible completions for functions if argument is `function',
5741 ;; completions for procedures if argument is `procedure' or both functions and
5742 ;; procedures otherwise.
5744 (defun verilog-func-completion (type)
5745 "Build regular expression for module/task/function names.
5746 TYPE is 'module, 'tf for task or function, or t if unknown."
5747 (if (string= verilog-str "")
5748 (setq verilog-str "[a-zA-Z_]"))
5749 (let ((verilog-str (concat (cond
5750 ((eq type 'module) "\\<\\(module\\)\\s +")
5751 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
5752 (t "\\<\\(task\\|function\\|module\\)\\s +"))
5753 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
5756 (if (not (looking-at verilog-defun-re))
5757 (verilog-re-search-backward verilog-defun-re nil t))
5760 ;; Search through all reachable functions
5761 (goto-char (point-min))
5762 (while (verilog-re-search-forward verilog-str (point-max) t)
5763 (progn (setq match (buffer-substring (match-beginning 2)
5765 (if (or (null verilog-pred)
5766 (funcall verilog-pred match))
5767 (setq verilog-all (cons match verilog-all)))))
5768 (if (match-beginning 0)
5769 (goto-char (match-beginning 0)))))
5771 (defun verilog-get-completion-decl (end)
5772 "Macro for searching through current declaration (var, type or const)
5773 for matches of `str' and adding the occurrence tp `all' through point END."
5774 (let ((re (or (and verilog-indent-declaration-macros
5775 verilog-declaration-re-2-macro)
5776 verilog-declaration-re-2-no-macro))
5779 (while (and (< (point) end)
5780 (verilog-re-search-forward re end t))
5781 ;; Traverse current line
5782 (setq decl-end (save-excursion (verilog-declaration-end)))
5783 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
5784 (not (match-end 1)))
5785 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
5786 (if (string-match (concat "\\<" verilog-str) match)
5787 (if (or (null verilog-pred)
5788 (funcall verilog-pred match))
5789 (setq verilog-all (cons match verilog-all)))))
5793 (defun verilog-type-completion ()
5794 "Calculate all possible completions for types."
5795 (let ((start (point))
5797 ;; Search for all reachable type declarations
5798 (while (or (verilog-beg-of-defun)
5799 (setq goon (not goon)))
5801 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
5804 (verilog-re-search-forward
5805 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>"
5807 (not (match-end 1)))
5808 ;; Check current type declaration
5809 (verilog-get-completion-decl start))))))
5811 (defun verilog-var-completion ()
5812 "Calculate all possible completions for variables (or constants)."
5813 (let ((start (point)))
5814 ;; Search for all reachable var declarations
5815 (verilog-beg-of-defun)
5817 ;; Check var declarations
5818 (verilog-get-completion-decl start))))
5820 (defun verilog-keyword-completion (keyword-list)
5821 "Give list of all possible completions of keywords in KEYWORD-LIST."
5822 (mapcar '(lambda (s)
5823 (if (string-match (concat "\\<" verilog-str) s)
5824 (if (or (null verilog-pred)
5825 (funcall verilog-pred s))
5826 (setq verilog-all (cons s verilog-all)))))
5830 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
5831 "Function passed to `completing-read', `try-completion' or `all-completions'.
5832 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
5833 must be a function to be called for every match to check if this should
5834 really be a match. If VERILOG-FLAG is t, the function returns a list of
5835 all possible completions. If VERILOG-FLAG is nil it returns a string,
5836 the longest possible completion, or t if VERILOG-STR is an exact match.
5837 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an
5838 exact match, nil otherwise."
5840 (let ((verilog-all nil))
5841 ;; Set buffer to use for searching labels. This should be set
5842 ;; within functions which use verilog-completions
5843 (set-buffer verilog-buffer-to-use)
5845 ;; Determine what should be completed
5846 (let ((state (car (verilog-calculate-indent))))
5847 (cond ((eq state 'defun)
5848 (save-excursion (verilog-var-completion))
5849 (verilog-func-completion 'module)
5850 (verilog-keyword-completion verilog-defun-keywords))
5852 ((eq state 'behavioral)
5853 (save-excursion (verilog-var-completion))
5854 (verilog-func-completion 'module)
5855 (verilog-keyword-completion verilog-defun-keywords))
5858 (save-excursion (verilog-var-completion))
5859 (verilog-func-completion 'tf)
5860 (verilog-keyword-completion verilog-block-keywords))
5863 (save-excursion (verilog-var-completion))
5864 (verilog-func-completion 'tf)
5865 (verilog-keyword-completion verilog-case-keywords))
5868 (save-excursion (verilog-var-completion))
5869 (verilog-func-completion 'tf)
5870 (verilog-keyword-completion verilog-tf-keywords))
5873 (save-excursion (verilog-var-completion))
5874 (verilog-keyword-completion verilog-cpp-keywords))
5876 ((eq state 'cparenexp)
5877 (save-excursion (verilog-var-completion)))
5880 (save-excursion (verilog-var-completion))
5881 (verilog-func-completion 'both)
5882 (verilog-keyword-completion verilog-separator-keywords))))
5884 ;; Now we have built a list of all matches. Give response to caller
5885 (verilog-completion-response))))
5887 (defun verilog-completion-response ()
5888 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
5889 ;; This was not called by all-completions
5890 (if (null verilog-all)
5891 ;; Return nil if there was no matching label
5893 ;; Get longest string common in the labels
5894 (let* ((elm (cdr verilog-all))
5895 (match (car verilog-all))
5896 (min (length match))
5898 (if (string= match verilog-str)
5899 ;; Return t if first match was an exact match
5901 (while (not (null elm))
5902 ;; Find longest common string
5903 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
5906 (setq match (substring match 0 min))))
5907 ;; Terminate with match=t if this is an exact match
5908 (if (string= (car elm) verilog-str)
5912 (setq elm (cdr elm)))))
5913 ;; If this is a test just for exact match, return nil ot t
5914 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
5917 ;; If flag is t, this was called by all-completions. Return
5918 ;; list of all possible completions
5922 (defvar verilog-last-word-numb 0)
5923 (defvar verilog-last-word-shown nil)
5924 (defvar verilog-last-completions nil)
5926 (defun verilog-complete-word ()
5927 "Complete word at current point.
5928 \(See also `verilog-toggle-completions', `verilog-type-keywords',
5929 and `verilog-separator-keywords'.)"
5931 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
5932 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
5933 (verilog-str (buffer-substring b e))
5934 ;; The following variable is used in verilog-completion
5935 (verilog-buffer-to-use (current-buffer))
5936 (allcomp (if (and verilog-toggle-completions
5937 (string= verilog-last-word-shown verilog-str))
5938 verilog-last-completions
5939 (all-completions verilog-str 'verilog-completion)))
5940 (match (if verilog-toggle-completions
5942 verilog-str (mapcar '(lambda (elm)
5943 (cons elm 0)) allcomp)))))
5944 ;; Delete old string
5947 ;; Toggle-completions inserts whole labels
5948 (if verilog-toggle-completions
5950 ;; Update entry number in list
5951 (setq verilog-last-completions allcomp
5952 verilog-last-word-numb
5953 (if (>= verilog-last-word-numb (1- (length allcomp)))
5955 (1+ verilog-last-word-numb)))
5956 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
5957 ;; Display next match or same string if no match was found
5958 (if (not (null allcomp))
5959 (insert "" verilog-last-word-shown)
5960 (insert "" verilog-str)
5961 (message "(No match)")))
5962 ;; The other form of completion does not necessarily do that.
5964 ;; Insert match if found, or the original string if no match
5965 (if (or (null match) (equal match 't))
5966 (progn (insert "" verilog-str)
5967 (message "(No match)"))
5969 ;; Give message about current status of completion
5970 (cond ((equal match 't)
5971 (if (not (null (cdr allcomp)))
5972 (message "(Complete but not unique)")
5973 (message "(Sole completion)")))
5974 ;; Display buffer if the current completion didn't help
5975 ;; on completing the label.
5976 ((and (not (null (cdr allcomp))) (= (length verilog-str)
5978 (with-output-to-temp-buffer "*Completions*"
5979 (display-completion-list allcomp))
5980 ;; Wait for a key press. Then delete *Completion* window
5981 (momentary-string-display "" (point))
5982 (delete-window (get-buffer-window (get-buffer "*Completions*")))
5985 (defun verilog-show-completions ()
5986 "Show all possible completions at current point."
5988 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
5989 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
5990 (verilog-str (buffer-substring b e))
5991 ;; The following variable is used in verilog-completion
5992 (verilog-buffer-to-use (current-buffer))
5993 (allcomp (if (and verilog-toggle-completions
5994 (string= verilog-last-word-shown verilog-str))
5995 verilog-last-completions
5996 (all-completions verilog-str 'verilog-completion))))
5997 ;; Show possible completions in a temporary buffer.
5998 (with-output-to-temp-buffer "*Completions*"
5999 (display-completion-list allcomp))
6000 ;; Wait for a key press. Then delete *Completion* window
6001 (momentary-string-display "" (point))
6002 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
6005 (defun verilog-get-default-symbol ()
6006 "Return symbol around current point as a string."
6008 (buffer-substring (progn
6009 (skip-chars-backward " \t")
6010 (skip-chars-backward "a-zA-Z0-9_")
6013 (skip-chars-forward "a-zA-Z0-9_")
6016 (defun verilog-build-defun-re (str &optional arg)
6017 "Return function/task/module starting with STR as regular expression.
6018 With optional second ARG non-nil, STR is the complete name of the instruction."
6020 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
6021 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
6023 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
6024 "Function passed to `completing-read', `try-completion' or `all-completions'.
6025 Returns a completion on any function name based on VERILOG-STR prefix. If
6026 VERILOG-PRED is non-nil, it must be a function to be called for every match
6027 to check if this should really be a match. If VERILOG-FLAG is t, the
6028 function returns a list of all possible completions. If it is nil it
6029 returns a string, the longest possible completion, or t if VERILOG-STR is
6030 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
6031 VERILOG-STR is an exact match, nil otherwise."
6033 (let ((verilog-all nil)
6036 ;; Set buffer to use for searching labels. This should be set
6037 ;; within functions which use verilog-completions
6038 (set-buffer verilog-buffer-to-use)
6040 (let ((verilog-str verilog-str))
6041 ;; Build regular expression for functions
6042 (if (string= verilog-str "")
6043 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
6044 (setq verilog-str (verilog-build-defun-re verilog-str)))
6045 (goto-char (point-min))
6047 ;; Build a list of all possible completions
6048 (while (verilog-re-search-forward verilog-str nil t)
6049 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
6050 (if (or (null verilog-pred)
6051 (funcall verilog-pred match))
6052 (setq verilog-all (cons match verilog-all)))))
6054 ;; Now we have built a list of all matches. Give response to caller
6055 (verilog-completion-response))))
6057 (defun verilog-goto-defun ()
6058 "Move to specified Verilog module/task/function.
6059 The default is a name found in the buffer around point.
6060 If search fails, other files are checked based on
6061 `verilog-library-flags'."
6063 (let* ((default (verilog-get-default-symbol))
6064 ;; The following variable is used in verilog-comp-function
6065 (verilog-buffer-to-use (current-buffer))
6066 (label (if (not (string= default ""))
6067 ;; Do completion with default
6068 (completing-read (concat "Goto-Label: (default "
6070 'verilog-comp-defun nil nil "")
6071 ;; There is no default value. Complete without it
6072 (completing-read "Goto-Label: "
6073 'verilog-comp-defun nil nil "")))
6075 ;; Make sure library paths are correct, in case need to resolve module
6076 (verilog-auto-reeval-locals)
6077 (verilog-getopt-flags)
6078 ;; If there was no response on prompt, use default value
6079 (if (string= label "")
6080 (setq label default))
6081 ;; Goto right place in buffer if label is not an empty string
6082 (or (string= label "")
6085 (goto-char (point-min))
6087 (re-search-forward (verilog-build-defun-re label t) nil t)))
6090 (beginning-of-line))
6092 (verilog-goto-defun-file label))))
6094 ;; Eliminate compile warning
6095 (defvar occur-pos-list)
6097 (defun verilog-showscopes ()
6098 "List all scopes in this module."
6100 (let ((buffer (current-buffer))
6104 (prevpos (point-min))
6105 (final-context-start (make-marker))
6106 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
6107 (with-output-to-temp-buffer "*Occur*"
6109 (message (format "Searching for %s ..." regexp))
6110 ;; Find next match, but give up if prev match was at end of buffer.
6111 (while (and (not (= prevpos (point-max)))
6112 (verilog-re-search-forward regexp nil t))
6113 (goto-char (match-beginning 0))
6116 (setq linenum (+ linenum (count-lines prevpos (point)))))
6117 (setq prevpos (point))
6118 (goto-char (match-end 0))
6119 (let* ((start (save-excursion
6120 (goto-char (match-beginning 0))
6121 (forward-line (if (< nlines 0) nlines (- nlines)))
6123 (end (save-excursion
6124 (goto-char (match-end 0))
6126 (forward-line (1+ nlines))
6129 (tag (format "%3d" linenum))
6130 (empty (make-string (length tag) ?\ ))
6133 (setq tem (make-marker))
6134 (set-marker tem (point))
6135 (set-buffer standard-output)
6136 (setq occur-pos-list (cons tem occur-pos-list))
6137 (or first (zerop nlines)
6138 (insert "--------\n"))
6140 (insert-buffer-substring buffer start end)
6141 (backward-char (- end start))
6142 (setq tem (if (< nlines 0) (- nlines) nlines))
6146 (setq tem (1- tem)))
6147 (let ((this-linenum linenum))
6148 (set-marker final-context-start
6149 (+ (point) (- (match-end 0) (match-beginning 0))))
6150 (while (< (point) final-context-start)
6152 (setq tag (format "%3d" this-linenum)))
6153 (insert tag ?:)))))))
6154 (set-buffer-modified-p nil))))
6157 ;; Highlight helper functions
6158 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
6159 (defun verilog-within-translate-off ()
6160 "Return point if within translate-off region, else nil."
6161 (and (save-excursion
6163 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
6165 (equal "off" (match-string 2))
6168 (defun verilog-start-translate-off (limit)
6169 "Return point before translate-off directive if before LIMIT, else nil."
6170 (when (re-search-forward
6171 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
6173 (match-beginning 0)))
6175 (defun verilog-back-to-start-translate-off (limit)
6176 "Return point before translate-off directive if before LIMIT, else nil."
6177 (when (re-search-backward
6178 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
6180 (match-beginning 0)))
6182 (defun verilog-end-translate-off (limit)
6183 "Return point after translate-on directive if before LIMIT, else nil."
6185 (re-search-forward (concat
6186 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
6188 (defun verilog-match-translate-off (limit)
6189 "Match a translate-off block, setting `match-data' and returning t, else nil.
6190 Bound search by LIMIT."
6191 (when (< (point) limit)
6192 (let ((start (or (verilog-within-translate-off)
6193 (verilog-start-translate-off limit)))
6194 (case-fold-search t))
6196 (let ((end (or (verilog-end-translate-off limit) limit)))
6197 (set-match-data (list start end))
6198 (goto-char end))))))
6200 (defun verilog-font-lock-match-item (limit)
6201 "Match, and move over, any declaration item after point.
6202 Bound search by LIMIT. Adapted from
6203 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
6206 (narrow-to-region (point-min) limit)
6208 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
6210 (goto-char (match-end 1))
6211 ;; move to next item
6212 (if (looking-at "\\(\\s-*,\\)")
6213 (goto-char (match-end 1))
6218 ;; Added by Subbu Meiyappan for Header
6220 (defun verilog-header ()
6221 "Insert a standard Verilog file header.
6222 See also `verilog-sk-header' for an alternative format."
6224 (let ((start (point)))
6226 //-----------------------------------------------------------------------------
6228 // Project : <project>
6229 //-----------------------------------------------------------------------------
6230 // File : <filename>
6231 // Author : <author>
6232 // Created : <credate>
6233 // Last modified : <moddate>
6234 //-----------------------------------------------------------------------------
6237 //-----------------------------------------------------------------------------
6238 // Copyright (c) <copydate> by <company> This model is the confidential and
6239 // proprietary property of <company> and the possession or use of this
6240 // file requires a written license from <company>.
6241 //------------------------------------------------------------------------------
6242 // Modification history :
6244 //-----------------------------------------------------------------------------
6248 (search-forward "<filename>")
6249 (replace-match (buffer-name) t t)
6250 (search-forward "<author>") (replace-match "" t t)
6251 (insert (user-full-name))
6252 (insert " <" (user-login-name) "@" (system-name) ">")
6253 (search-forward "<credate>") (replace-match "" t t)
6254 (verilog-insert-date)
6255 (search-forward "<moddate>") (replace-match "" t t)
6256 (verilog-insert-date)
6257 (search-forward "<copydate>") (replace-match "" t t)
6258 (verilog-insert-year)
6259 (search-forward "<modhist>") (replace-match "" t t)
6260 (verilog-insert-date)
6261 (insert " : created")
6264 (setq string (read-string "title: "))
6265 (search-forward "<title>")
6266 (replace-match string t t)
6267 (setq string (read-string "project: " verilog-project))
6268 (setq verilog-project string)
6269 (search-forward "<project>")
6270 (replace-match string t t)
6271 (setq string (read-string "Company: " verilog-company))
6272 (setq verilog-company string)
6273 (search-forward "<company>")
6274 (replace-match string t t)
6275 (search-forward "<company>")
6276 (replace-match string t t)
6277 (search-forward "<company>")
6278 (replace-match string t t)
6279 (search-backward "<description>")
6280 (replace-match "" t t))))
6282 ;; verilog-header Uses the verilog-insert-date function
6284 (defun verilog-insert-date ()
6285 "Insert date from the system."
6287 (if verilog-date-scientific-format
6288 (insert (format-time-string "%Y/%m/%d"))
6289 (insert (format-time-string "%d.%m.%Y"))))
6291 (defun verilog-insert-year ()
6292 "Insert year from the system."
6294 (insert (format-time-string "%Y")))
6298 ;; Signal list parsing
6301 ;; Elements of a signal list
6302 (defsubst verilog-sig-name (sig)
6304 (defsubst verilog-sig-bits (sig)
6306 (defsubst verilog-sig-comment (sig)
6308 (defsubst verilog-sig-memory (sig)
6310 (defsubst verilog-sig-enum (sig)
6312 (defsubst verilog-sig-signed (sig)
6314 (defsubst verilog-sig-type (sig)
6316 (defsubst verilog-sig-multidim (sig)
6318 (defsubst verilog-sig-multidim-string (sig)
6319 (if (verilog-sig-multidim sig)
6320 (let ((str "") (args (verilog-sig-multidim sig)))
6322 (setq str (concat str (car args)))
6323 (setq args (cdr args)))
6325 (defsubst verilog-sig-modport (sig)
6327 (defsubst verilog-sig-width (sig)
6328 (verilog-make-width-expression (verilog-sig-bits sig)))
6330 (defsubst verilog-alw-get-inputs (sigs)
6332 (defsubst verilog-alw-get-outputs (sigs)
6334 (defsubst verilog-alw-get-uses-delayed (sigs)
6337 (defun verilog-signals-not-in (in-list not-list)
6338 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
6339 Also remove any duplicates in IN-LIST.
6340 Signals must be in standard (base vector) form."
6343 (if (not (or (assoc (car (car in-list)) not-list)
6344 (assoc (car (car in-list)) out-list)))
6345 (setq out-list (cons (car in-list) out-list)))
6346 (setq in-list (cdr in-list)))
6347 (nreverse out-list)))
6348 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
6350 (defun verilog-signals-in (in-list other-list)
6351 "Return list of signals in IN-LIST that are also in OTHER-LIST.
6352 Signals must be in standard (base vector) form."
6355 (if (assoc (car (car in-list)) other-list)
6356 (setq out-list (cons (car in-list) out-list)))
6357 (setq in-list (cdr in-list)))
6358 (nreverse out-list)))
6359 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
6361 (defun verilog-signals-memory (in-list)
6362 "Return list of signals in IN-LIST that are memoried (multidimensional)."
6365 (if (nth 3 (car in-list))
6366 (setq out-list (cons (car in-list) out-list)))
6367 (setq in-list (cdr in-list)))
6369 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
6371 (defun verilog-signals-sort-compare (a b)
6372 "Compare signal A and B for sorting."
6373 (string< (car a) (car b)))
6375 (defun verilog-signals-not-params (in-list)
6376 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
6379 (unless (boundp (intern (concat "vh-" (car (car in-list)))))
6380 (setq out-list (cons (car in-list) out-list)))
6381 (setq in-list (cdr in-list)))
6382 (nreverse out-list)))
6384 (defun verilog-signals-combine-bus (in-list)
6385 "Return a list of signals in IN-LIST, with busses combined.
6386 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
6389 sig highbit lowbit ; Temp information about current signal
6390 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
6391 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
6394 ;; Shove signals so duplicated signals will be adjacent
6395 (setq in-list (sort in-list `verilog-signals-sort-compare))
6397 (setq sig (car in-list))
6398 ;; No current signal; form from existing details
6400 (setq sv-name (verilog-sig-name sig)
6403 sv-comment (verilog-sig-comment sig)
6404 sv-memory (verilog-sig-memory sig)
6405 sv-enum (verilog-sig-enum sig)
6406 sv-signed (verilog-sig-signed sig)
6407 sv-type (verilog-sig-type sig)
6408 sv-multidim (verilog-sig-multidim sig)
6409 sv-modport (verilog-sig-modport sig)
6412 ;; Extract bus details
6413 (setq bus (verilog-sig-bits sig))
6415 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
6416 (setq highbit (string-to-number (match-string 1 bus))
6417 lowbit (string-to-number
6418 (match-string 2 bus))))
6419 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
6420 (setq highbit (string-to-number (match-string 1 bus))
6422 ;; Combine bits in bus
6424 (setq sv-highbit (max highbit sv-highbit)
6425 sv-lowbit (min lowbit sv-lowbit))
6426 (setq sv-highbit highbit
6429 ;; String, probably something like `preproc:0
6430 (setq sv-busstring bus)))
6431 ;; Peek ahead to next signal
6432 (setq in-list (cdr in-list))
6433 (setq sig (car in-list))
6434 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
6435 ;; Combine with this signal
6436 (when (and sv-busstring
6437 (not (equal sv-busstring (verilog-sig-bits sig))))
6438 (when nil ;; Debugging
6439 (message (concat "Warning, can't merge into single bus "
6441 ", the AUTOs may be wrong")))
6442 (setq buswarn ", Couldn't Merge"))
6443 (if (verilog-sig-comment sig) (setq combo ", ..."))
6444 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
6445 sv-enum (or sv-enum (verilog-sig-enum sig))
6446 sv-signed (or sv-signed (verilog-sig-signed sig))
6447 sv-type (or sv-type (verilog-sig-type sig))
6448 sv-multidim (or sv-multidim (verilog-sig-multidim sig))
6449 sv-modport (or sv-modport (verilog-sig-modport sig))))
6450 ;; Doesn't match next signal, add to queue, zero in prep for next
6451 ;; Note sig may also be nil for the last signal in the list
6458 (concat "[" (int-to-string sv-highbit) ":"
6459 (int-to-string sv-lowbit) "]")))
6460 (concat sv-comment combo buswarn)
6461 sv-memory sv-enum sv-signed sv-type sv-multidim sv-modport)
6467 (defun verilog-sig-tieoff (sig &optional no-width)
6468 "Return tieoff expression for given SIG, with appropriate width.
6469 Ignore width if optional NO-WIDTH is set."
6470 (let* ((width (if no-width nil (verilog-sig-width sig))))
6472 (if (and verilog-active-low-regexp
6473 (string-match verilog-active-low-regexp (verilog-sig-name sig)))
6477 ((string-match "^[0-9]+$" width)
6478 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
6480 (concat "{" width "{1'b0}}"))))))
6483 ;; Port/Wire/Etc Reading
6486 (defun verilog-read-inst-backward-name ()
6487 "Internal. Move point back to beginning of inst-name."
6488 (verilog-backward-open-paren)
6491 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
6492 (cond ((looking-at ")")
6493 (verilog-backward-open-paren))
6494 (t (setq done t)))))
6495 (while (looking-at "\\]")
6496 (verilog-backward-open-bracket)
6497 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
6498 (skip-chars-backward "a-zA-Z0-9`_$"))
6500 (defun verilog-read-inst-module ()
6501 "Return module_name when point is inside instantiation."
6503 (verilog-read-inst-backward-name)
6504 ;; Skip over instantiation name
6505 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
6506 ;; Check for parameterized instantiations
6507 (when (looking-at ")")
6508 (verilog-backward-open-paren)
6509 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
6510 (skip-chars-backward "a-zA-Z0-9'_$")
6511 (looking-at "[a-zA-Z0-9`_\$]+")
6512 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
6513 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6515 (defun verilog-read-inst-name ()
6516 "Return instance_name when point is inside instantiation."
6518 (verilog-read-inst-backward-name)
6519 (looking-at "[a-zA-Z0-9`_\$]+")
6520 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
6521 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6523 (defun verilog-read-module-name ()
6524 "Return module name when after its ( or ;."
6526 (re-search-backward "[(;]")
6527 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
6528 (skip-chars-backward "a-zA-Z0-9`_$")
6529 (looking-at "[a-zA-Z0-9`_\$]+")
6530 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
6531 (verilog-symbol-detick
6532 (buffer-substring-no-properties (match-beginning 0) (match-end 0)) t)))
6534 (defun verilog-read-inst-param-value ()
6535 "Return list of parameters and values when point is inside instantiation."
6537 (verilog-read-inst-backward-name)
6538 ;; Skip over instantiation name
6539 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
6540 ;; If there are parameterized instantiations
6541 (when (looking-at ")")
6542 (let ((end-pt (point))
6544 param-name paren-beg-pt param-value)
6545 (verilog-backward-open-paren)
6546 (while (verilog-re-search-forward-quick "\\." end-pt t)
6547 (verilog-re-search-forward-quick "\\([a-zA-Z0-9`_\$]\\)" nil nil)
6548 (skip-chars-backward "a-zA-Z0-9'_$")
6549 (looking-at "[a-zA-Z0-9`_\$]+")
6550 (setq param-name (buffer-substring-no-properties
6551 (match-beginning 0) (match-end 0)))
6552 (verilog-re-search-forward-quick "(" nil nil)
6553 (setq paren-beg-pt (point))
6554 (verilog-forward-close-paren)
6555 (setq param-value (verilog-string-remove-spaces
6556 (buffer-substring-no-properties
6557 paren-beg-pt (1- (point)))))
6558 (setq params (cons (list param-name param-value) params)))
6561 (defun verilog-read-auto-params (num-param &optional max-param)
6562 "Return parameter list inside auto.
6563 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
6566 ;; /*AUTOPUNT("parameter", "parameter")*/
6567 (search-backward "(")
6568 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
6569 (setq olist (cons (match-string 1) olist))
6570 (goto-char (match-end 0))))
6571 (or (eq nil num-param)
6572 (<= num-param (length olist))
6573 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
6574 (if (eq max-param nil) (setq max-param num-param))
6575 (or (eq nil max-param)
6576 (>= max-param (length olist))
6577 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
6580 (defun verilog-read-decls ()
6581 "Compute signal declaration information for the current module at point.
6582 Return a array of [outputs inouts inputs wire reg assign const]."
6583 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
6584 (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
6585 sigs-in sigs-out sigs-inout sigs-wire sigs-reg sigs-assign sigs-const
6586 sigs-gparam sigs-intf
6587 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
6590 (verilog-beg-of-defun)
6591 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
6592 (while (< (point) end-mod-point)
6593 ;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg)))
6596 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6597 (setq enum (match-string 1)))
6598 (search-forward "\n"))
6599 ((looking-at "/\\*")
6601 (if (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6602 (setq enum (match-string 1)))
6603 (or (search-forward "*/")
6604 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6605 ((looking-at "(\\*")
6607 (or (looking-at "\\s-*)") ; It's an "always @ (*)"
6608 (search-forward "*)")
6609 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
6610 ((eq ?\" (following-char))
6611 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
6612 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
6613 ((eq ?\; (following-char))
6614 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
6617 ((eq ?= (following-char))
6618 (setq rvalue t newsig nil)
6620 ((and (eq ?, (following-char))
6621 (eq paren sig-paren))
6624 ;; ,'s can occur inside {} & funcs
6625 ((looking-at "[{(]")
6626 (setq paren (1+ paren))
6628 ((looking-at "[})]")
6629 (setq paren (1- paren))
6631 (when (< paren sig-paren)
6632 (setq expect-signal nil))) ; ) that ends variables inside v2k arg list
6633 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
6634 (goto-char (match-end 0))
6635 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
6636 (setcar (cdr (cdr (cdr newsig))) (match-string 1)))
6637 (vec ;; Multidimensional
6638 (setq multidim (cons vec multidim))
6639 (setq vec (verilog-string-replace-matches
6640 "\\s-+" "" nil nil (match-string 1))))
6642 (setq vec (verilog-string-replace-matches
6643 "\\s-+" "" nil nil (match-string 1))))))
6644 ;; Normal or escaped identifier -- note we remember the \ if escaped
6645 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
6646 (goto-char (match-end 0))
6647 (setq keywd (match-string 1))
6648 (when (string-match "^\\\\" keywd)
6649 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
6650 (cond ((equal keywd "input")
6651 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6652 expect-signal 'sigs-in io t modport nil))
6653 ((equal keywd "output")
6654 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6655 expect-signal 'sigs-out io t modport nil))
6656 ((equal keywd "inout")
6657 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6658 expect-signal 'sigs-inout io t modport nil))
6659 ((equal keywd "parameter")
6660 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6661 expect-signal 'sigs-gparam io t modport nil))
6662 ((member keywd '("wire" "tri" "tri0" "tri1" "triand" "trior" "wand" "wor"))
6663 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6664 expect-signal 'sigs-wire modport nil)))
6665 ((member keywd '("reg" "trireg"
6666 "byte" "shortint" "int" "longint" "integer" "time"
6668 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6669 expect-signal 'sigs-reg modport nil)))
6670 ((equal keywd "assign")
6671 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6672 expect-signal 'sigs-assign modport nil))
6673 ((member keywd '("supply0" "supply1" "supply"
6674 "localparam" "genvar"))
6675 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6676 expect-signal 'sigs-const modport nil)))
6677 ((equal keywd "signed")
6678 (setq signed "signed"))
6679 ((member keywd '("class" "clocking" "covergroup" "function"
6680 "property" "randsequence" "sequence" "task"))
6681 (setq functask (1+ functask)))
6682 ((member keywd '("endclass" "endclocking" "endgroup" "endfunction"
6683 "endproperty" "endsequence" "endtask"))
6684 (setq functask (1- functask)))
6685 ;; Ifdef? Ignore name of define
6686 ((member keywd '("`ifdef" "`ifndef"))
6689 ((verilog-typedef-name-p keywd)
6690 (setq typedefed keywd))
6691 ;; Interface with optional modport in v2k arglist?
6692 ;; Skip over parsing modport, and take the interface name as the type
6695 (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z0-9`_$]+\\)\\|\\)\\s-*[a-zA-Z0-9`_$]+"))
6696 (when (match-end 2) (goto-char (match-end 2)))
6697 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed keywd multidim nil sig-paren paren
6698 expect-signal 'sigs-intf io t modport (match-string 2)))
6699 ;; New signal, maybe?
6703 (not (member keywd verilog-keywords)))
6704 ;; Add new signal to expect-signal's variable
6705 (setq newsig (list keywd vec nil nil enum signed typedefed multidim modport))
6706 (set expect-signal (cons newsig
6707 (symbol-value expect-signal))))))
6710 (skip-syntax-forward " "))
6712 (vector (nreverse sigs-out)
6713 (nreverse sigs-inout)
6715 (nreverse sigs-wire)
6717 (nreverse sigs-assign)
6718 (nreverse sigs-const)
6719 (nreverse sigs-gparam)
6720 (nreverse sigs-intf)))))
6723 ;; Prevent compile warnings; these are let's, not globals
6724 ;; Do not remove the eval-when-compile
6725 ;; - we want a error when we are debugging this code if they are refed.
6732 (defsubst verilog-modi-get-decls (modi)
6733 (verilog-modi-cache-results modi 'verilog-read-decls))
6735 (defsubst verilog-modi-get-sub-decls (modi)
6736 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
6739 ;; Signal reading for given module
6740 ;; Note these all take modi's - as returned from the
6741 ;; verilog-modi-current function.
6742 (defsubst verilog-decls-get-outputs (decls)
6744 (defsubst verilog-decls-get-inouts (decls)
6746 (defsubst verilog-decls-get-inputs (decls)
6748 (defsubst verilog-decls-get-wires (decls)
6750 (defsubst verilog-decls-get-regs (decls)
6752 (defsubst verilog-decls-get-assigns (decls)
6754 (defsubst verilog-decls-get-consts (decls)
6756 (defsubst verilog-decls-get-gparams (decls)
6758 (defsubst verilog-decls-get-interfaces (decls)
6760 (defsubst verilog-subdecls-get-outputs (subdecls)
6762 (defsubst verilog-subdecls-get-inouts (subdecls)
6764 (defsubst verilog-subdecls-get-inputs (subdecls)
6766 (defsubst verilog-subdecls-get-interfaces (subdecls)
6770 (defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim)
6771 "For `verilog-read-sub-decls-line', add a signal."
6774 (setq port (verilog-symbol-detick-denumber port))
6775 (setq sig (verilog-symbol-detick-denumber sig))
6776 (if sig (setq sig (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil sig)))
6777 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
6778 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
6779 (unless (or (not sig)
6780 (equal sig "")) ;; Ignore .foo(1'b1) assignments
6781 (cond ((setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
6782 (setq sigs-inout (cons (list sig vec (concat "To/From " comment) nil nil
6783 (verilog-sig-signed portdata)
6784 (verilog-sig-type portdata)
6787 ((setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
6788 (setq sigs-out (cons (list sig vec (concat "From " comment) nil nil
6789 (verilog-sig-signed portdata)
6790 (verilog-sig-type portdata)
6793 ((setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
6794 (setq sigs-in (cons (list sig vec (concat "To " comment) nil nil
6795 (verilog-sig-signed portdata)
6796 (verilog-sig-type portdata)
6799 ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
6800 (setq sigs-intf (cons (list sig vec (concat "To/From " comment) nil nil
6801 (verilog-sig-signed portdata)
6802 (verilog-sig-type portdata)
6805 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
6808 (defun verilog-read-sub-decls-expr (submoddecls comment port expr)
6809 "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
6810 ;;(message "vrsde: '%s'" expr)
6811 ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
6812 (setq expr (verilog-string-replace-matches "/\\*\\(\\[[^*]+\\]\\)\\*/" "\\1" nil nil expr))
6813 ;; Remove front operators
6814 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
6817 ;; {..., a, b} requires us to recurse on a,b
6818 ((string-match "^\\s-*{\\([^{}]*\\)}\\s-*$" expr)
6819 (unless verilog-auto-ignore-concat
6820 (let ((mlst (split-string (match-string 1 expr) ","))
6822 (while (setq mstr (pop mlst))
6823 (verilog-read-sub-decls-expr submoddecls comment port mstr)))))
6825 (let (sig vec multidim)
6826 (cond ;; Find \signal. Final space is part of escaped signal name
6827 ((string-match "^\\s-*\\(\\\\[^ \t\n\f]+\\s-\\)" expr)
6828 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
6829 (setq sig (match-string 1 expr)
6830 expr (substring expr (match-end 0))))
6832 ((string-match "^\\s-*\\([^[({).\\]+\\)" expr)
6833 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
6834 (setq sig (verilog-string-remove-spaces (match-string 1 expr))
6835 expr (substring expr (match-end 0)))))
6836 ;; Find [vector] or [multi][multi][multi][vector]
6837 (while (string-match "^\\s-*\\(\\[[^]]+\\]\\)" expr)
6838 ;;(message "vrsde-v: '%s'" (match-string 1 expr))
6839 (when vec (setq multidim (cons vec multidim)))
6840 (setq vec (match-string 1 expr)
6841 expr (substring expr (match-end 0))))
6842 ;; If found signal, and nothing unrecognized, add the signal
6843 ;;(message "vrsde-rem: '%s'" expr)
6844 (when (and sig (string-match "^\\s-*$" expr))
6845 (verilog-read-sub-decls-sig submoddecls comment port sig vec multidim))))))
6847 (defun verilog-read-sub-decls-line (submoddecls comment)
6848 "For `verilog-read-sub-decls', read lines of port defs until none match anymore.
6849 Return the list of signals found, using submodi to look up each port."
6855 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
6856 (setq port (match-string 1))
6857 (goto-char (match-end 0)))
6858 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
6859 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
6860 (goto-char (match-end 0)))
6861 ((looking-at "\\s-*\\.[^(]*(")
6862 (setq port nil) ;; skip this line
6863 (goto-char (match-end 0)))
6865 (setq port nil done t))) ;; Unknown, ignore rest of line
6866 ;; Get signal name. Point is at the first-non-space after (
6867 ;; We intentionally ignore (non-escaped) signals with .s in them
6868 ;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
6870 (cond ((looking-at "\\([^[({).\\]*\\)\\s-*)")
6871 (verilog-read-sub-decls-sig
6872 submoddecls comment port
6873 (verilog-string-remove-spaces (match-string 1)) ; sig
6874 nil nil)) ; vec multidim
6876 ((looking-at "\\([^[({).\\]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
6877 (verilog-read-sub-decls-sig
6878 submoddecls comment port
6879 (verilog-string-remove-spaces (match-string 1)) ; sig
6880 (match-string 2) nil)) ; vec multidim
6881 ;; Fastpath was above looking-at's.
6882 ;; For something more complicated invoke a parser
6883 ((looking-at "[^)]+")
6884 (verilog-read-sub-decls-expr
6885 submoddecls comment port
6887 (point) (1- (progn (backward-char 1) ; start at (
6888 (forward-sexp 1) (point)))))))) ; expr
6890 (forward-line 1)))))
6892 (defun verilog-read-sub-decls ()
6893 "Internally parse signals going to modules under this module.
6894 Return a array of [ outputs inouts inputs ] signals for modules that are
6895 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
6896 is a output, then SIG will be included in the list.
6898 This only works on instantiations created with /*AUTOINST*/ converted by
6899 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
6900 component library to determine connectivity of the design.
6902 One work around for this problem is to manually create // Inputs and //
6903 Outputs comments above subcell signals, for example:
6911 (let ((end-mod-point (verilog-get-end-of-defun t))
6912 st-point end-inst-point
6913 ;; below 3 modified by verilog-read-sub-decls-line
6914 sigs-out sigs-inout sigs-in sigs-intf)
6915 (verilog-beg-of-defun)
6916 (while (verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
6918 (goto-char (match-beginning 0))
6919 (unless (verilog-inside-comment-p)
6920 ;; Attempt to snarf a comment
6921 (let* ((submod (verilog-read-inst-module))
6922 (inst (verilog-read-inst-name))
6923 (comment (concat inst " of " submod ".v"))
6924 submodi submoddecls)
6925 (when (setq submodi (verilog-modi-lookup submod t))
6926 (setq submoddecls (verilog-modi-get-decls submodi))
6927 ;; This could have used a list created by verilog-auto-inst
6928 ;; However I want it to be runnable even on user's manually added signals
6929 (verilog-backward-open-paren)
6930 (setq end-inst-point (save-excursion (forward-sexp 1) (point))
6932 (while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
6933 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
6934 (goto-char st-point)
6935 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
6936 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
6937 (goto-char st-point)
6938 (while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
6939 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-inout
6940 (goto-char st-point)
6941 (while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
6942 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-in
6944 ;; Combine duplicate bits
6945 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
6946 (vector (verilog-signals-combine-bus (nreverse sigs-out))
6947 (verilog-signals-combine-bus (nreverse sigs-inout))
6948 (verilog-signals-combine-bus (nreverse sigs-in))
6949 (verilog-signals-combine-bus (nreverse sigs-intf))))))
6951 (defun verilog-read-inst-pins ()
6952 "Return an array of [ pins ] for the current instantiation at point.
6953 For example if declare A A (.B(SIG)) then B will be included in the list."
6955 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
6957 (verilog-backward-open-paren)
6958 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
6959 (setq pin (match-string 1))
6960 (unless (verilog-inside-comment-p)
6961 (setq pins (cons (list pin) pins))
6962 (when (looking-at "(")
6966 (defun verilog-read-arg-pins ()
6967 "Return an array of [ pins ] for the current argument declaration at point."
6969 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
6971 (verilog-backward-open-paren)
6972 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
6973 (setq pin (match-string 1))
6974 (unless (verilog-inside-comment-p)
6975 (setq pins (cons (list pin) pins))))
6978 (defun verilog-read-auto-constants (beg end-mod-point)
6979 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
6982 (let (sig-list tpl-end-pt)
6984 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
6985 (if (not (looking-at "\\s *("))
6986 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
6987 (search-forward "(" end-mod-point)
6988 (setq tpl-end-pt (save-excursion
6990 (forward-sexp 1) ;; Moves to paren that closes argdecl's
6993 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
6994 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
6997 (defun verilog-read-auto-lisp (start end)
6998 "Look for and evaluate a AUTO_LISP between START and END."
7001 (while (re-search-forward "\\<AUTO_LISP(" end t)
7003 (let* ((beg-pt (prog1 (point)
7004 (forward-sexp 1))) ;; Closing paren
7006 (eval-region beg-pt end-pt nil)))))
7009 ;; Prevent compile warnings; these are let's, not globals
7010 ;; Do not remove the eval-when-compile
7011 ;; - we want a error when we are debugging this code if they are refed.
7016 (defvar uses-delayed)
7017 (defvar vector-skip-list))
7019 (defun verilog-read-always-signals-recurse
7020 (exit-keywd rvalue ignore-next)
7021 "Recursive routine for parentheses/bracket matching.
7022 EXIT-KEYWD is expression to stop at, nil if top level.
7023 RVALUE is true if at right hand side of equal.
7024 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
7025 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
7026 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-rvalue end-else-check)
7027 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue ignore-next))))
7028 (while (not (or (eobp) gotend))
7031 (search-forward "\n"))
7032 ((looking-at "/\\*")
7033 (or (search-forward "*/")
7034 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
7035 ((looking-at "(\\*")
7036 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
7037 (search-forward "*)")
7038 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
7039 (t (setq keywd (buffer-substring-no-properties
7041 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
7044 sig-last-tolk sig-tolk
7046 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
7049 (or (re-search-forward "[^\\]\"" nil t)
7050 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
7051 ;; else at top level loop, keep parsing
7052 ((and end-else-check (equal keywd "else"))
7053 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
7054 ;; no forward movement, want to see else in lower loop
7055 (setq end-else-check nil))
7056 ;; End at top level loop
7057 ((and end-else-check (looking-at "[^ \t\n\f]"))
7058 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
7061 ((and exit-keywd (equal keywd exit-keywd))
7063 (forward-char (length keywd)))
7064 ;; Standard tokens...
7066 (setq ignore-next nil rvalue semi-rvalue)
7067 ;; Final statement at top level loop?
7068 (when (not exit-keywd)
7069 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
7070 (setq end-else-check t))
7073 (if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
7074 (goto-char (match-end 0))
7076 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
7077 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
7078 (setq ignore-next nil rvalue nil))
7079 ((equal "?" exit-keywd) ;; x?y:z rvalue
7081 ((equal "]" exit-keywd) ;; [x:y] rvalue
7083 (got-sig ;; label: statement
7084 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
7085 ((not rvalue) ;; begin label
7086 (setq ignore-next t rvalue nil)))
7089 (if (and (eq (char-before) ?< )
7091 (setq uses-delayed 1))
7092 (setq ignore-next nil rvalue t)
7096 (verilog-read-always-signals-recurse ":" rvalue nil))
7099 (verilog-read-always-signals-recurse "]" t nil))
7102 (cond (sig-last-tolk ;; Function call; zap last signal
7103 (setq got-sig nil)))
7104 (cond ((equal last-keywd "for")
7105 (verilog-read-always-signals-recurse ";" nil nil)
7106 (verilog-read-always-signals-recurse ";" t nil)
7107 (verilog-read-always-signals-recurse ")" nil nil))
7108 (t (verilog-read-always-signals-recurse ")" t nil))))
7109 ((equal keywd "begin")
7110 (skip-syntax-forward "w_")
7111 (verilog-read-always-signals-recurse "end" nil nil)
7112 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
7113 (setq ignore-next nil rvalue semi-rvalue)
7114 (if (not exit-keywd) (setq end-else-check t)))
7115 ((or (equal keywd "case")
7116 (equal keywd "casex")
7117 (equal keywd "casez"))
7118 (skip-syntax-forward "w_")
7119 (verilog-read-always-signals-recurse "endcase" t nil)
7120 (setq ignore-next nil rvalue semi-rvalue)
7121 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
7122 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
7123 (cond ((or (equal keywd "`ifdef")
7124 (equal keywd "`ifndef"))
7125 (setq ignore-next t))
7127 (member keywd verilog-keywords)
7128 (string-match "^\\$" keywd)) ;; PLI task
7129 (setq ignore-next nil))
7131 (setq keywd (verilog-symbol-detick-denumber keywd))
7133 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
7134 (setq sigs-out (cons got-sig sigs-out)))
7135 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
7137 (setq got-rvalue rvalue
7138 got-sig (if (or (not keywd)
7139 (assoc keywd (if got-rvalue sigs-in sigs-out)))
7140 nil (list keywd nil nil))
7142 (skip-chars-forward "a-zA-Z0-9$_.%`"))
7145 ;; End of non-comment token
7146 (setq last-keywd keywd)))
7147 (skip-syntax-forward " "))
7148 ;; Append the final pending signal
7150 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
7151 (setq sigs-out (cons got-sig sigs-out)))
7152 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
7154 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
7157 (defun verilog-read-always-signals ()
7158 "Parse always block at point and return list of (outputs inout inputs)."
7163 uses-delayed) ;; Found signal/rvalue; push if not function
7164 (search-forward ")")
7165 (verilog-read-always-signals-recurse nil nil nil)
7166 ;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))
7167 ;; Return what was found
7168 (list sigs-out nil sigs-in uses-delayed))))
7170 (defun verilog-read-instants ()
7171 "Parse module at point and return list of ( ( file instance ) ... )."
7172 (verilog-beg-of-defun)
7173 (let* ((end-mod-point (verilog-get-end-of-defun t))
7175 (instants-list nil))
7177 (while (< (point) end-mod-point)
7178 ;; Stay at level 0, no comments
7180 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
7181 (or (> (car state) 0) ; in parens
7182 (nth 5 state) ; comment
7186 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
7187 ;;(if (looking-at "^\\(.+\\)$")
7188 (let ((module (match-string 1))
7189 (instant (match-string 2)))
7190 (if (not (member module verilog-keywords))
7191 (setq instants-list (cons (list module instant) instants-list)))))
7196 (defun verilog-read-auto-template (module)
7197 "Look for a auto_template for the instantiation of the given MODULE.
7198 If found returns the signal name connections. Return REGEXP and
7199 list of ( (signal_name connection_name)... )."
7202 (let ((tpl-regexp "\\([0-9]+\\)")
7205 tpl-sig-list tpl-wild-list tpl-end-pt rep)
7207 (re-search-backward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
7209 (goto-char (point-min))
7210 (re-search-forward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
7211 (goto-char (match-end 0))
7213 ;; We reserve @"..." for future lisp expressions that evaluate once-per-AUTOINST
7214 (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
7215 (setq tpl-regexp (match-string 1))
7216 (goto-char (match-end 0)))
7217 (search-forward "(")
7218 ;; Parse lines in the template
7219 (when verilog-auto-inst-template-numbers
7221 (goto-char (point-min))
7222 (while (search-forward "AUTO_TEMPLATE" nil t)
7223 (setq templateno (1+ templateno)))))
7224 (setq tpl-end-pt (save-excursion
7226 (forward-sexp 1) ;; Moves to paren that closes argdecl's
7230 (while (< (point) tpl-end-pt)
7231 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
7232 (setq tpl-sig-list (cons (list
7233 (match-string-no-properties 1)
7234 (match-string-no-properties 2)
7237 (goto-char (match-end 0)))
7240 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
7241 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
7242 (setq rep (match-string-no-properties 3))
7243 (goto-char (match-end 0))
7247 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
7253 ((looking-at "[ \t\f]+")
7254 (goto-char (match-end 0)))
7256 (setq lineno (1+ lineno))
7257 (goto-char (match-end 0)))
7259 (search-forward "\n"))
7260 ((looking-at "/\\*")
7262 (or (search-forward "*/")
7263 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
7265 (error "%s: AUTO_TEMPLATE parsing error: %s"
7266 (verilog-point-text)
7267 (progn (looking-at ".*$") (match-string 0))))))
7270 (list tpl-sig-list tpl-wild-list)))
7271 ;; If no template found
7272 (t (vector tpl-regexp nil))))))
7273 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
7275 (defun verilog-set-define (defname defvalue &optional buffer enumname)
7276 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
7277 Optionally associate it with the specified enumeration ENUMNAME."
7278 (with-current-buffer (or buffer (current-buffer))
7279 (let ((mac (intern (concat "vh-" defname))))
7280 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
7281 ;; Need to define to a constant if no value given
7282 (set (make-local-variable mac)
7283 (if (equal defvalue "") "1" defvalue)))
7285 (let ((enumvar (intern (concat "venum-" enumname))))
7286 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
7287 (unless (boundp enumvar) (set enumvar nil))
7288 (make-local-variable enumvar)
7289 (add-to-list enumvar defname)))))
7291 (defun verilog-read-defines (&optional filename recurse subcall)
7292 "Read `defines and parameters for the current file, or optional FILENAME.
7293 If the filename is provided, `verilog-library-flags' will be used to
7294 resolve it. If optional RECURSE is non-nil, recurse through `includes.
7296 Parameters must be simple assignments to constants, or have their own
7297 \"parameter\" label rather than a list of parameters. Thus:
7299 parameter X = 5, Y = 10; // Ok
7300 parameter X = {1'b1, 2'h2}; // Ok
7301 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
7303 Defines must be simple text substitutions, one on a line, starting
7304 at the beginning of the line. Any ifdefs or multiline comments around the
7307 Defines are stored inside Emacs variables using the name vh-{definename}.
7309 This function is useful for setting vh-* variables. The file variables
7310 feature can be used to set defines that `verilog-mode' can see; put at the
7311 *END* of your file something like:
7314 // vh-macro:\"macro_definition\"
7317 If macros are defined earlier in the same file and you want their values,
7318 you can read them automatically (provided `enable-local-eval' is on):
7321 // eval:(verilog-read-defines)
7322 // eval:(verilog-read-defines \"group_standard_includes.v\")
7325 Note these are only read when the file is first visited, you must use
7326 \\[find-alternate-file] RET to have these take effect after editing them!
7328 If you want to disable the \"Process `eval' or hook local variables\"
7329 warning message, you need to add to your .emacs file:
7331 (setq enable-local-eval t)"
7332 (let ((origbuf (current-buffer)))
7334 (unless subcall (verilog-getopt-flags))
7336 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
7338 (set-buffer (find-file-noselect (car fns)))
7339 (error (concat (verilog-point-text)
7340 ": Can't find verilog-read-defines file: " filename)))))
7342 (goto-char (point-min))
7343 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
7344 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string-no-properties 1))))
7345 (unless (verilog-inside-comment-p)
7346 (verilog-read-defines inc recurse t)))))
7348 ;; note we don't use verilog-re... it's faster this way, and that
7349 ;; function has problems when comments are at the end of the define
7350 (goto-char (point-min))
7351 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
7352 (let ((defname (match-string-no-properties 1))
7353 (defvalue (match-string-no-properties 2)))
7354 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
7355 (verilog-set-define defname defvalue origbuf)))
7356 ;; Hack: Read parameters
7357 (goto-char (point-min))
7358 (while (re-search-forward
7359 "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-+" nil t)
7361 ;; The primary way of getting defines is verilog-read-decls
7362 ;; However, that isn't called yet for included files, so we'll add another scheme
7363 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
7364 (setq enumname (match-string-no-properties 1)))
7365 (forward-comment 999)
7366 (while (looking-at "\\s-*,?\\s-*\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\s-*")
7367 (verilog-set-define (match-string-no-properties 1) (match-string-no-properties 2) origbuf enumname)
7368 (goto-char (match-end 0))
7369 (forward-comment 999)))))))
7371 (defun verilog-read-includes ()
7372 "Read `includes for the current file.
7373 This will find all of the `includes which are at the beginning of lines,
7374 ignoring any ifdefs or multiline comments around them.
7375 `verilog-read-defines' is then performed on the current and each included
7378 It is often useful put at the *END* of your file something like:
7381 // eval:(verilog-read-defines)
7382 // eval:(verilog-read-includes)
7385 Note includes are only read when the file is first visited, you must use
7386 \\[find-alternate-file] RET to have these take effect after editing them!
7388 It is good to get in the habit of including all needed files in each .v
7389 file that needs it, rather than waiting for compile time. This will aid
7390 this process, Verilint, and readability. To prevent defining the same
7391 variable over and over when many modules are compiled together, put a test
7392 around the inside each include file:
7395 `ifdef _FOO_V // include if not already included
7398 ... contents of file
7400 ;;slow: (verilog-read-defines nil t))
7402 (verilog-getopt-flags)
7403 (goto-char (point-min))
7404 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
7405 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
7406 (verilog-read-defines inc nil t)))))
7408 (defun verilog-read-signals (&optional start end)
7409 "Return a simple list of all possible signals in the file.
7410 Bounded by optional region from START to END. Overly aggressive but fast.
7411 Some macros and such are also found and included. For dinotrace.el."
7412 (let (sigs-all keywd)
7413 (progn;save-excursion
7414 (goto-char (or start (point-min)))
7415 (setq end (or end (point-max)))
7416 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
7420 (search-forward "\n"))
7421 ((looking-at "/\\*")
7422 (search-forward "*/"))
7423 ((looking-at "(\\*")
7424 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
7425 (search-forward "*)")))
7426 ((eq ?\" (following-char))
7427 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
7428 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
7429 (goto-char (match-end 0))
7430 (setq keywd (match-string-no-properties 1))
7431 (or (member keywd verilog-keywords)
7432 (member keywd sigs-all)
7433 (setq sigs-all (cons keywd sigs-all))))
7434 (t (forward-char 1))))
7439 ;; Argument file parsing
7442 (defun verilog-getopt (arglist)
7443 "Parse -f, -v etc arguments in ARGLIST list or string."
7444 (unless (listp arglist) (setq arglist (list arglist)))
7445 (let ((space-args '())
7447 ;; Split on spaces, so users can pass whole command lines
7449 (setq arg (car arglist)
7450 arglist (cdr arglist))
7451 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
7452 (setq space-args (append space-args
7453 (list (match-string-no-properties 1 arg))))
7454 (setq arg (match-string 2 arg))))
7457 (setq arg (car space-args)
7458 space-args (cdr space-args))
7462 (setq next-param arg))
7464 (setq next-param arg))
7466 (setq next-param arg))
7467 ;; +libext+(ext1)+(ext2)...
7468 ((string-match "^\\+libext\\+\\(.*\\)" arg)
7469 (setq arg (match-string 1 arg))
7470 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
7471 (verilog-add-list-unique `verilog-library-extensions
7472 (match-string 1 arg))
7473 (setq arg (match-string 2 arg))))
7475 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
7476 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
7477 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
7478 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
7479 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
7481 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
7482 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
7483 (verilog-add-list-unique `verilog-library-directories
7484 (match-string 1 (substitute-in-file-name arg))))
7486 ((equal "+librescan" arg))
7487 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
7488 ;; Second parameters
7489 ((equal next-param "-f")
7490 (setq next-param nil)
7491 (verilog-getopt-file (substitute-in-file-name arg)))
7492 ((equal next-param "-v")
7493 (setq next-param nil)
7494 (verilog-add-list-unique `verilog-library-files
7495 (substitute-in-file-name arg)))
7496 ((equal next-param "-y")
7497 (setq next-param nil)
7498 (verilog-add-list-unique `verilog-library-directories
7499 (substitute-in-file-name arg)))
7501 ((string-match "^[^-+]" arg)
7502 (verilog-add-list-unique `verilog-library-files
7503 (substitute-in-file-name arg)))
7504 ;; Default - ignore; no warning
7506 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
7508 (defun verilog-getopt-file (filename)
7509 "Read Verilog options from the specified FILENAME."
7511 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
7512 (orig-buffer (current-buffer))
7515 (set-buffer (find-file-noselect (car fns)))
7516 (error (concat (verilog-point-text)
7517 ": Can't find verilog-getopt-file -f file: " filename)))
7518 (goto-char (point-min))
7520 (setq line (buffer-substring (point)
7521 (save-excursion (end-of-line) (point))))
7523 (when (string-match "//" line)
7524 (setq line (substring line 0 (match-beginning 0))))
7525 (with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
7526 (verilog-getopt line))))))
7528 (defun verilog-getopt-flags ()
7529 "Convert `verilog-library-flags' into standard library variables."
7530 ;; If the flags are local, then all the outputs should be local also
7531 (when (local-variable-p `verilog-library-flags (current-buffer))
7532 (mapc 'make-local-variable '(verilog-library-extensions
7533 verilog-library-directories
7534 verilog-library-files
7535 verilog-library-flags)))
7536 ;; Allow user to customize
7537 (run-hooks 'verilog-before-getopt-flags-hook)
7538 ;; Process arguments
7539 (verilog-getopt verilog-library-flags)
7540 ;; Allow user to customize
7541 (run-hooks 'verilog-getopt-flags-hook))
7543 (defun verilog-add-list-unique (varref object)
7544 "Append to VARREF list the given OBJECT,
7545 unless it is already a member of the variable's list."
7546 (unless (member object (symbol-value varref))
7547 (set varref (append (symbol-value varref) (list object))))
7549 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
7553 ;; Cached directory support
7556 (defvar verilog-dir-cache-preserving nil
7557 "If set, the directory cache is enabled, and file system changes are ignored.
7558 See `verilog-dir-exists-p' and `verilog-dir-files'.")
7560 ;; If adding new cached variable, add also to verilog-preserve-dir-cache
7561 (defvar verilog-dir-cache-list nil
7562 "Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.")
7563 (defvar verilog-dir-cache-lib-filenames nil
7564 "Cached data for `verilog-library-filenames'.")
7566 (defmacro verilog-preserve-dir-cache (&rest body)
7567 "Execute the BODY forms, allowing directory cache preservation within BODY.
7568 This means that changes inside BODY made to the file system will not be
7569 seen by the `verilog-dir-files' and related functions."
7570 `(let ((verilog-dir-cache-preserving t)
7571 verilog-dir-cache-list
7572 verilog-dir-cache-lib-filenames)
7575 (defun verilog-dir-files (dirname)
7576 "Return all filenames in the DIRNAME directory.
7577 Relative paths depend on the `default-directory'.
7578 Results are cached if inside `verilog-preserve-dir-cache'."
7579 (unless verilog-dir-cache-preserving
7580 (setq verilog-dir-cache-list nil)) ;; Cache disabled
7581 ;; We don't use expand-file-name on the dirname to make key, as it's slow
7582 (let* ((cache-key (list dirname default-directory))
7583 (fass (assoc cache-key verilog-dir-cache-list))
7585 (cond (fass ;; Return data from cache hit
7588 (setq exp-dirname (expand-file-name dirname)
7589 data (and (file-directory-p exp-dirname)
7590 (directory-files exp-dirname nil nil nil)))
7591 ;; Note we also encache nil for non-existing dirs.
7592 (setq verilog-dir-cache-list (cons (list cache-key data)
7593 verilog-dir-cache-list))
7595 ;; Miss-and-hit test:
7596 ;;(verilog-preserve-dir-cache (prin1 (verilog-dir-files "."))
7597 ;; (prin1 (verilog-dir-files ".")) nil)
7599 (defun verilog-dir-file-exists-p (filename)
7600 "Return true if FILENAME exists.
7601 Like `file-exists-p' but results are cached if inside
7602 `verilog-preserve-dir-cache'."
7603 (let* ((dirname (file-name-directory filename))
7604 ;; Correct for file-name-nondirectory returning same if no slash.
7605 (dirnamed (if (or (not dirname) (equal dirname filename))
7606 default-directory dirname))
7607 (flist (verilog-dir-files dirnamed)))
7609 (member (file-name-nondirectory filename) flist)
7611 ;;(verilog-dir-file-exists-p "verilog-mode.el")
7612 ;;(verilog-dir-file-exists-p "../verilog-mode/verilog-mode.el")
7616 ;; Module name lookup
7619 (defun verilog-module-inside-filename-p (module filename)
7620 "Return point if MODULE is specified inside FILENAME, else nil.
7621 Allows version control to check out the file if need be."
7622 (and (or (file-exists-p filename)
7623 (and (fboundp 'vc-backend)
7624 (vc-backend filename)))
7626 (with-current-buffer (find-file-noselect filename)
7628 (goto-char (point-min))
7630 ;; It may be tempting to look for verilog-defun-re,
7631 ;; don't, it slows things down a lot!
7632 (verilog-re-search-forward-quick "\\<module\\>" nil t)
7633 (verilog-re-search-forward-quick "[(;]" nil t))
7634 (if (equal module (verilog-read-module-name))
7638 (defun verilog-is-number (symbol)
7639 "Return true if SYMBOL is number-like."
7640 (or (string-match "^[0-9 \t:]+$" symbol)
7641 (string-match "^[---]*[0-9]+$" symbol)
7642 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
7644 (defun verilog-symbol-detick (symbol wing-it)
7645 "Return an expanded SYMBOL name without any defines.
7646 If the variable vh-{symbol} is defined, return that value.
7647 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
7648 (while (and symbol (string-match "^`" symbol))
7649 (setq symbol (substring symbol 1))
7651 (if (boundp (intern (concat "vh-" symbol)))
7652 ;; Emacs has a bug where boundp on a buffer-local
7653 ;; variable in only one buffer returns t in another.
7654 ;; This can confuse, so check for nil.
7655 (let ((val (eval (intern (concat "vh-" symbol)))))
7657 (if wing-it symbol nil)
7659 (if wing-it symbol nil))))
7661 ;;(verilog-symbol-detick "`mod" nil)
7663 (defun verilog-symbol-detick-denumber (symbol)
7664 "Return SYMBOL with defines converted and any numbers dropped to nil."
7665 (when (string-match "^`" symbol)
7666 ;; This only will work if the define is a simple signal, not
7667 ;; something like a[b]. Sorry, it should be substituted into the parser
7669 (verilog-string-replace-matches
7670 "\[[^0-9: \t]+\]" "" nil nil
7671 (or (verilog-symbol-detick symbol nil)
7672 (if verilog-auto-sense-defines-constant
7675 (if (verilog-is-number symbol)
7679 (defun verilog-symbol-detick-text (text)
7680 "Return TEXT without any known defines.
7681 If the variable vh-{symbol} is defined, substitute that value."
7682 (let ((ok t) symbol val)
7683 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
7684 (setq symbol (match-string 1 text))
7687 (boundp (intern (concat "vh-" symbol)))
7688 ;; Emacs has a bug where boundp on a buffer-local
7689 ;; variable in only one buffer returns t in another.
7690 ;; This can confuse, so check for nil.
7691 (setq val (eval (intern (concat "vh-" symbol)))))
7692 (setq text (replace-match val nil nil text)))
7693 (t (setq ok nil)))))
7695 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
7697 (defun verilog-expand-dirnames (&optional dirnames)
7698 "Return a list of existing directories given a list of wildcarded DIRNAMES.
7699 Or, just the existing dirnames themselves if there are no wildcards."
7700 ;; Note this function is performance critical.
7701 ;; Do not call anything that requires disk access that cannot be cached.
7703 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
7704 (setq dirnames (reverse dirnames)) ; not nreverse
7706 pattern dirfile dirfiles dirname root filename rest basefile)
7708 (setq dirname (substitute-in-file-name (car dirnames))
7709 dirnames (cdr dirnames))
7710 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
7711 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
7714 (setq root (match-string 1 dirname)
7715 filename (match-string 2 dirname)
7716 rest (match-string 3 dirname)
7718 ;; now replace those * and ? with .+ and .
7719 ;; use ^ and /> to get only whole file names
7720 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
7721 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
7722 pattern (concat "^" pattern "$")
7723 dirfiles (verilog-dir-files root))
7725 (setq basefile (car dirfiles)
7726 dirfile (expand-file-name (concat root basefile rest))
7727 dirfiles (cdr dirfiles))
7728 (if (and (string-match pattern basefile)
7729 ;; Don't allow abc/*/rtl to match abc/rtl via ..
7730 (not (equal basefile "."))
7731 (not (equal basefile ".."))
7732 (file-directory-p dirfile))
7733 (setq dirlist (cons dirfile dirlist)))))
7736 (if (file-directory-p dirname)
7737 (setq dirlist (cons dirname dirlist))))))
7739 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
7741 (defun verilog-library-filenames (filename &optional current check-ext)
7742 "Return a search path to find the given FILENAME or module name.
7743 Uses the optional CURRENT filename or buffer-file-name, plus
7744 `verilog-library-directories' and `verilog-library-extensions'
7745 variables to build the path. With optional CHECK-EXT also check
7746 `verilog-library-extensions'."
7747 (unless current (setq current (buffer-file-name)))
7748 (unless verilog-dir-cache-preserving
7749 (setq verilog-dir-cache-lib-filenames nil))
7750 (let* ((cache-key (list filename current check-ext))
7751 (fass (assoc cache-key verilog-dir-cache-lib-filenames))
7752 chkdirs chkdir chkexts fn outlist)
7753 (cond (fass ;; Return data from cache hit
7756 ;; Note this expand can't be easily cached, as we need to
7757 ;; pick up buffer-local variables for newly read sub-module files
7758 (setq chkdirs (verilog-expand-dirnames verilog-library-directories))
7760 (setq chkdir (expand-file-name (car chkdirs)
7761 (file-name-directory current))
7762 chkexts (if check-ext verilog-library-extensions `("")))
7764 (setq fn (expand-file-name (concat filename (car chkexts))
7766 ;;(message "Check for %s" fn)
7767 (if (verilog-dir-file-exists-p fn)
7768 (setq outlist (cons (expand-file-name
7769 fn (file-name-directory current))
7771 (setq chkexts (cdr chkexts)))
7772 (setq chkdirs (cdr chkdirs)))
7773 (setq outlist (nreverse outlist))
7774 (setq verilog-dir-cache-lib-filenames
7775 (cons (list cache-key outlist)
7776 verilog-dir-cache-lib-filenames))
7779 (defun verilog-module-filenames (module current)
7780 "Return a search path to find the given MODULE name.
7781 Uses the CURRENT filename, `verilog-library-extensions',
7782 `verilog-library-directories' and `verilog-library-files'
7783 variables to build the path."
7784 ;; Return search locations for it
7785 (append (list current) ; first, current buffer
7786 (verilog-library-filenames module current t)
7787 verilog-library-files)) ; finally, any libraries
7790 ;; Module Information
7792 ;; Many of these functions work on "modi" a module information structure
7793 ;; A modi is: [module-name-string file-name begin-point]
7795 (defvar verilog-cache-enabled t
7796 "If true, enable caching of signals, etc. Set to nil for debugging to make things SLOW!")
7798 (defvar verilog-modi-cache-list nil
7799 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
7800 For speeding up verilog-modi-get-* commands.
7803 (make-variable-buffer-local 'verilog-modi-cache-list)
7805 (defvar verilog-modi-cache-preserve-tick nil
7806 "Modification tick after which the cache is still considered valid.
7807 Use `verilog-preserve-modi-cache' to set it.")
7808 (defvar verilog-modi-cache-preserve-buffer nil
7809 "Modification tick after which the cache is still considered valid.
7810 Use `verilog-preserve-modi-cache' to set it.")
7812 (defun verilog-modi-current ()
7813 "Return the modi structure for the module currently at point."
7815 ;; read current module's name
7817 (verilog-re-search-backward-quick verilog-defun-re nil nil)
7818 (verilog-re-search-forward-quick "(" nil nil)
7819 (setq name (verilog-read-module-name))
7822 (vector name (or (buffer-file-name) (current-buffer)) pt)))
7824 (defvar verilog-modi-lookup-last-mod nil "Cache of last module looked up.")
7825 (defvar verilog-modi-lookup-last-modi nil "Cache of last modi returned.")
7826 (defvar verilog-modi-lookup-last-current nil "Cache of last `current-buffer' looked up.")
7827 (defvar verilog-modi-lookup-last-tick nil "Cache of last `buffer-modified-tick' looked up.")
7829 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
7830 "Find the file and point at which MODULE is defined.
7831 If ALLOW-CACHE is set, check and remember cache of previous lookups.
7832 Return modi if successful, else print message unless IGNORE-ERROR is true."
7833 (let* ((current (or (buffer-file-name) (current-buffer))))
7834 (cond ((and verilog-modi-lookup-last-modi
7835 verilog-cache-enabled
7837 (equal verilog-modi-lookup-last-mod module)
7838 (equal verilog-modi-lookup-last-current current)
7839 (equal verilog-modi-lookup-last-tick (buffer-modified-tick)))
7842 (t (let* ((realmod (verilog-symbol-detick module t))
7843 (orig-filenames (verilog-module-filenames realmod current))
7844 (filenames orig-filenames)
7846 (while (and filenames (not pt))
7847 (if (not (setq pt (verilog-module-inside-filename-p realmod (car filenames))))
7848 (setq filenames (cdr filenames))))
7849 (cond (pt (setq verilog-modi-lookup-last-modi
7850 (vector realmod (car filenames) pt)))
7851 (t (setq verilog-modi-lookup-last-modi nil)
7853 (error (concat (verilog-point-text)
7854 ": Can't locate " module " module definition"
7855 (if (not (equal module realmod))
7856 (concat " (Expanded macro to " realmod ")")
7858 "\n Check the verilog-library-directories variable."
7859 "\n I looked in (if not listed, doesn't exist):\n\t"
7860 (mapconcat 'concat orig-filenames "\n\t"))))))
7861 (setq verilog-modi-lookup-last-mod module
7862 verilog-modi-lookup-last-current current
7863 verilog-modi-lookup-last-tick (buffer-modified-tick)))))
7864 verilog-modi-lookup-last-modi))
7866 (defsubst verilog-modi-name (modi)
7868 (defsubst verilog-modi-file-or-buffer (modi)
7870 (defsubst verilog-modi-point (modi)
7873 (defun verilog-modi-filename (modi)
7874 "Filename of MODI, or name of buffer if it's never been saved."
7875 (if (bufferp (verilog-modi-file-or-buffer modi))
7876 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
7877 (buffer-name (verilog-modi-file-or-buffer modi)))
7878 (verilog-modi-file-or-buffer modi)))
7880 (defun verilog-modi-goto (modi)
7881 "Move point/buffer to specified MODI."
7882 (or modi (error "Passed unfound modi to goto, check earlier"))
7883 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
7884 (verilog-modi-file-or-buffer modi)
7885 (find-file-noselect (verilog-modi-file-or-buffer modi))))
7886 (or (equal major-mode `verilog-mode) ;; Put into Verilog mode to get syntax
7888 (goto-char (verilog-modi-point modi)))
7890 (defun verilog-goto-defun-file (module)
7891 "Move point to the file at which a given MODULE is defined."
7892 (interactive "sGoto File for Module: ")
7893 (let* ((modi (verilog-modi-lookup module nil)))
7895 (verilog-modi-goto modi)
7896 (switch-to-buffer (current-buffer)))))
7898 (defun verilog-modi-cache-results (modi function)
7899 "Run on MODI the given FUNCTION. Locate the module in a file.
7900 Cache the output of function so next call may have faster access."
7902 (save-excursion ;; Cache is buffer-local so can't avoid this.
7903 (verilog-modi-goto modi)
7904 (if (and (setq fass (assoc (list modi function)
7905 verilog-modi-cache-list))
7906 ;; Destroy caching when incorrect; Modified or file changed
7907 (not (and verilog-cache-enabled
7908 (or (equal (buffer-modified-tick) (nth 1 fass))
7909 (and verilog-modi-cache-preserve-tick
7910 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
7911 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
7912 (equal (visited-file-modtime) (nth 2 fass)))))
7913 (setq verilog-modi-cache-list nil
7916 ;; Return data from cache hit
7920 ;; Clear then restore any hilighting to make emacs19 happy
7921 (let ((fontlocked (when (and (boundp 'font-lock-mode)
7926 (setq func-returns (funcall function))
7927 (when fontlocked (font-lock-mode t))
7928 ;; Cache for next time
7929 (setq verilog-modi-cache-list
7930 (cons (list (list modi function)
7931 (buffer-modified-tick)
7932 (visited-file-modtime)
7934 verilog-modi-cache-list))
7937 (defun verilog-modi-cache-add (modi function element sig-list)
7938 "Add function return results to the module cache.
7939 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
7940 function now contains the additional SIG-LIST parameters."
7943 (verilog-modi-goto modi)
7944 (if (setq fass (assoc (list modi function)
7945 verilog-modi-cache-list))
7946 (let ((func-returns (nth 3 fass)))
7947 (aset func-returns element
7948 (append sig-list (aref func-returns element))))))))
7950 (defmacro verilog-preserve-modi-cache (&rest body)
7951 "Execute the BODY forms, allowing cache preservation within BODY.
7952 This means that changes to the buffer will not result in the cache being
7953 flushed. If the changes affect the modsig state, they must call the
7954 modsig-cache-add-* function, else the results of later calls may be
7955 incorrect. Without this, changes are assumed to be adding/removing signals
7956 and invalidating the cache."
7957 `(let ((verilog-modi-cache-preserve-tick (buffer-modified-tick))
7958 (verilog-modi-cache-preserve-buffer (current-buffer)))
7962 (defun verilog-signals-matching-enum (in-list enum)
7963 "Return all signals in IN-LIST matching the given ENUM."
7966 (if (equal (verilog-sig-enum (car in-list)) enum)
7967 (setq out-list (cons (car in-list) out-list)))
7968 (setq in-list (cdr in-list)))
7970 (let* ((enumvar (intern (concat "venum-" enum)))
7971 (enumlist (and (boundp enumvar) (eval enumvar))))
7973 (add-to-list 'out-list (list (car enumlist)))
7974 (setq enumlist (cdr enumlist))))
7975 (nreverse out-list)))
7977 (defun verilog-signals-matching-regexp (in-list regexp)
7978 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
7979 (if (or (not regexp) (equal regexp ""))
7983 (if (string-match regexp (verilog-sig-name (car in-list)))
7984 (setq out-list (cons (car in-list) out-list)))
7985 (setq in-list (cdr in-list)))
7986 (nreverse out-list))))
7988 (defun verilog-signals-not-matching-regexp (in-list regexp)
7989 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
7990 (if (or (not regexp) (equal regexp ""))
7994 (if (not (string-match regexp (verilog-sig-name (car in-list))))
7995 (setq out-list (cons (car in-list) out-list)))
7996 (setq in-list (cdr in-list)))
7997 (nreverse out-list))))
7999 (defun verilog-signals-matching-dir-re (in-list decl-type regexp)
8000 "Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
8002 (if (or (not regexp) (equal regexp ""))
8004 (let (out-list to-match)
8006 ;; Note verilog-insert-one-definition matches on this order
8007 (setq to-match (concat
8009 " " (verilog-sig-signed (car in-list))
8010 " " (verilog-sig-multidim (car in-list))
8011 (verilog-sig-bits (car in-list))))
8012 (if (string-match regexp to-match)
8013 (setq out-list (cons (car in-list) out-list)))
8014 (setq in-list (cdr in-list)))
8015 (nreverse out-list))))
8018 (defun verilog-decls-get-signals (decls)
8020 (verilog-decls-get-outputs decls)
8021 (verilog-decls-get-inouts decls)
8022 (verilog-decls-get-inputs decls)
8023 (verilog-decls-get-wires decls)
8024 (verilog-decls-get-regs decls)
8025 (verilog-decls-get-assigns decls)
8026 (verilog-decls-get-consts decls)
8027 (verilog-decls-get-gparams decls)))
8029 (defun verilog-decls-get-ports (decls)
8031 (verilog-decls-get-outputs decls)
8032 (verilog-decls-get-inouts decls)
8033 (verilog-decls-get-inputs decls)))
8035 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
8036 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
8037 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
8038 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
8039 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
8040 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
8041 (defsubst verilog-modi-cache-add-wires (modi sig-list)
8042 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
8043 (defsubst verilog-modi-cache-add-regs (modi sig-list)
8044 (verilog-modi-cache-add modi 'verilog-read-decls 4 sig-list))
8046 (defun verilog-signals-from-signame (signame-list)
8047 "Return signals in standard form from SIGNAME-LIST, a simple list of signal names."
8048 (mapcar (function (lambda (name) (list name nil nil)))
8052 ;; Auto creation utilities
8055 (defun verilog-auto-re-search-do (search-for func)
8056 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
8057 (goto-char (point-min))
8058 (while (verilog-re-search-forward search-for nil t)
8061 (defun verilog-insert-one-definition (sig type indent-pt)
8062 "Print out a definition for SIG of the given TYPE,
8063 with appropriate INDENT-PT indentation."
8064 (indent-to indent-pt)
8065 ;; Note verilog-signals-matching-dir-re matches on this order
8067 (when (verilog-sig-modport sig)
8068 (insert "." (verilog-sig-modport sig)))
8069 (when (verilog-sig-signed sig)
8070 (insert " " (verilog-sig-signed sig)))
8071 (when (verilog-sig-multidim sig)
8072 (insert " " (verilog-sig-multidim-string sig)))
8073 (when (verilog-sig-bits sig)
8074 (insert " " (verilog-sig-bits sig)))
8075 (indent-to (max 24 (+ indent-pt 16)))
8076 (unless (= (char-syntax (preceding-char)) ?\ )
8077 (insert " ")) ; Need space between "]name" if indent-to did nothing
8078 (insert (verilog-sig-name sig)))
8080 (defun verilog-insert-definition (sigs direction indent-pt v2k &optional dont-sort)
8081 "Print out a definition for a list of SIGS of the given DIRECTION,
8082 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
8083 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output."
8085 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
8087 (let ((sig (car sigs)))
8088 (verilog-insert-one-definition
8090 ;; Want "type x" or "output type x", not "wire type x"
8091 (cond ((verilog-sig-type sig)
8093 (if (not (member direction '("wire" "interface")))
8094 (concat direction " "))
8095 (verilog-sig-type sig)))
8098 (insert (if v2k "," ";"))
8099 (if (or (not (verilog-sig-comment sig))
8100 (equal "" (verilog-sig-comment sig)))
8102 (indent-to (max 48 (+ indent-pt 40)))
8103 (insert (concat "// " (verilog-sig-comment sig) "\n")))
8104 (setq sigs (cdr sigs)))))
8107 (if (not (boundp 'indent-pt))
8108 (defvar indent-pt nil "Local used by insert-indent")))
8110 (defun verilog-insert-indent (&rest stuff)
8111 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
8112 Presumes that any newlines end a list element."
8113 (let ((need-indent t))
8115 (if need-indent (indent-to indent-pt))
8116 (setq need-indent nil)
8117 (insert (car stuff))
8118 (setq need-indent (string-match "\n$" (car stuff))
8119 stuff (cdr stuff)))))
8120 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
8122 (defun verilog-repair-open-comma ()
8123 "Insert comma if previous argument is other than a open parenthesis or endif."
8124 ;; We can't just search backward for ) as it might be inside another expression.
8125 ;; Also want "`ifdef X input foo `endif" to just leave things to the human to deal with
8127 (verilog-backward-syntactic-ws)
8128 (when (and (not (save-excursion ;; Not beginning (, or existing ,
8130 (looking-at "[(,]")))
8131 (not (save-excursion ;; Not `endif, or user define
8133 (skip-chars-backward "[a-zA-Z0-9_`]")
8137 (defun verilog-repair-close-comma ()
8138 "If point is at a comma followed by a close parenthesis, fix it.
8139 This repairs those mis-inserted by a AUTOARG."
8140 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
8142 (verilog-forward-close-paren)
8144 (verilog-backward-syntactic-ws)
8146 (when (looking-at ",")
8149 (defun verilog-get-list (start end)
8150 "Return the elements of a comma separated list between START and END."
8152 (let ((my-list (list))
8155 (while (< (point) end)
8156 (when (re-search-forward "\\([^,{]+\\)" end t)
8157 (setq my-string (verilog-string-remove-spaces (match-string 1)))
8158 (setq my-list (nconc my-list (list my-string) ))
8159 (goto-char (match-end 0))))
8162 (defun verilog-make-width-expression (range-exp)
8163 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
8165 (cond ((not range-exp)
8168 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
8169 (setq range-exp (match-string 1 range-exp)))
8170 (cond ((not range-exp)
8172 ;; [#:#] We can compute a numeric result
8173 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
8176 (1+ (abs (- (string-to-number (match-string 1 range-exp))
8177 (string-to-number (match-string 2 range-exp)))))))
8178 ;; [PARAM-1:0] can just return PARAM
8179 ((string-match "^\\s *\\([a-zA-Z_][a-zA-Z0-9_]*\\)\\s *-\\s *1\\s *:\\s *0\\s *$" range-exp)
8180 (match-string 1 range-exp))
8181 ;; [arbitrary] need math
8182 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
8183 (concat "(1+(" (match-string 1 range-exp) ")"
8184 (if (equal "0" (match-string 2 range-exp))
8185 "" ;; Don't bother with -(0)
8186 (concat "-(" (match-string 2 range-exp) ")"))
8189 ;;(verilog-make-width-expression "`A:`B")
8191 (defun verilog-simplify-range-expression (range-exp)
8192 "Return a simplified range expression with constants eliminated from RANGE-EXP."
8193 (let ((out range-exp)
8195 (while (not (equal last-pass out))
8196 (setq last-pass out)
8197 (while (string-match "(\\<\\([0-9A-Z-az_]+\\)\\>)" out)
8198 (setq out (replace-match "\\1" nil nil out)))
8199 (while (string-match "\\<\\([0-9]+\\)\\>\\s *\\+\\s *\\<\\([0-9]+\\)\\>" out)
8200 (setq out (replace-match
8201 (int-to-string (+ (string-to-number (match-string 1 out))
8202 (string-to-number (match-string 2 out))))
8204 (while (string-match "\\<\\([0-9]+\\)\\>\\s *\\-\\s *\\<\\([0-9]+\\)\\>" out)
8205 (setq out (replace-match
8206 (int-to-string (- (string-to-number (match-string 1 out))
8207 (string-to-number (match-string 2 out))))
8210 ;;(verilog-simplify-range-expression "1")
8211 ;;(verilog-simplify-range-expression "(((16)+1)-3)")
8213 (defun verilog-typedef-name-p (variable-name)
8214 "Return true if the VARIABLE-NAME is a type definition."
8215 (when verilog-typedef-regexp
8216 (string-match verilog-typedef-regexp variable-name)))
8222 (defun verilog-delete-autos-lined ()
8223 "Delete autos that occupy multiple lines, between begin and end comments."
8227 (looking-at "\\s-*// Beginning")
8228 (search-forward "// End of automatic" nil t))
8231 (delete-region pt (point))
8234 (defun verilog-delete-empty-auto-pair ()
8235 "Delete begin/end auto pair at point, if empty."
8237 (when (looking-at (concat "\\s-*// Beginning of automatic.*\n"
8238 "\\s-*// End of automatics\n"))
8239 (delete-region (point) (save-excursion (forward-line 2) (point)))))
8241 (defun verilog-forward-close-paren ()
8242 "Find the close parenthesis that match the current point.
8243 Ignore other close parenthesis with matching open parens."
8246 (unless (verilog-re-search-forward-quick "[()]" nil t)
8247 (error "%s: Mismatching ()" (verilog-point-text)))
8248 (cond ((= (preceding-char) ?\( )
8249 (setq parens (1+ parens)))
8250 ((= (preceding-char) ?\) )
8251 (setq parens (1- parens)))))))
8253 (defun verilog-backward-open-paren ()
8254 "Find the open parenthesis that match the current point.
8255 Ignore other open parenthesis with matching close parens."
8258 (unless (verilog-re-search-backward-quick "[()]" nil t)
8259 (error "%s: Mismatching ()" (verilog-point-text)))
8260 (cond ((= (following-char) ?\) )
8261 (setq parens (1+ parens)))
8262 ((= (following-char) ?\( )
8263 (setq parens (1- parens)))))))
8265 (defun verilog-backward-open-bracket ()
8266 "Find the open bracket that match the current point.
8267 Ignore other open bracket with matching close bracket."
8270 (unless (verilog-re-search-backward-quick "[][]" nil t)
8271 (error "%s: Mismatching []" (verilog-point-text)))
8272 (cond ((= (following-char) ?\] )
8273 (setq parens (1+ parens)))
8274 ((= (following-char) ?\[ )
8275 (setq parens (1- parens)))))))
8277 (defun verilog-delete-to-paren ()
8278 "Delete the automatic inst/sense/arg created by autos.
8279 Deletion stops at the matching end parenthesis."
8280 (delete-region (point)
8282 (verilog-backward-open-paren)
8283 (forward-sexp 1) ;; Moves to paren that closes argdecl's
8287 (defun verilog-auto-star-safe ()
8288 "Return if a .* AUTOINST is safe to delete or expand.
8289 It was created by the AUTOS themselves, or by the user."
8290 (and verilog-auto-star-expand
8291 (looking-at "[ \t\n\f,]*\\([)]\\|// \\(Outputs\\|Inouts\\|Inputs\\|Interfaces\\)\\)")))
8293 (defun verilog-delete-auto-star-all ()
8294 "Delete a .* AUTOINST, if it is safe."
8295 (when (verilog-auto-star-safe)
8296 (verilog-delete-to-paren)))
8298 (defun verilog-delete-auto-star-implicit ()
8299 "Delete all .* implicit connections created by `verilog-auto-star'.
8300 This function will be called automatically at save unless
8301 `verilog-auto-star-save' is set, any non-templated expanded pins will be
8304 (let (paren-pt indent have-close-paren)
8306 (goto-char (point-min))
8307 ;; We need to match these even outside of comments.
8308 ;; For reasonable performance, we don't check if inside comments, sorry.
8309 (while (re-search-forward "// Implicit \\.\\*" nil t)
8310 (setq paren-pt (point))
8312 (setq have-close-paren
8314 (when (search-forward ");" paren-pt t)
8315 (setq indent (current-indentation))
8317 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
8318 (when have-close-paren
8319 ;; Delete extra commentary
8323 (looking-at "\\s *//\\s *\\(Outputs\\|Inouts\\|Inputs\\|Interfaces\\)\n"))
8324 (delete-region (match-beginning 0) (match-end 0))))
8325 ;; If it is simple, we can put the ); on the same line as the last text
8326 (let ((rtn-pt (point)))
8328 (while (progn (backward-char 1)
8329 (looking-at "[ \t\n\f]")))
8330 (when (looking-at ",")
8331 (delete-region (+ 1 (point)) rtn-pt))))
8335 ;; Still need to kill final comma - always is one as we put one after the .*
8336 (re-search-backward ",")
8337 (delete-char 1))))))
8339 (defun verilog-delete-auto ()
8340 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
8341 Use \\[verilog-auto] to re-insert the updated AUTOs.
8343 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
8344 called before and after this function, respectively."
8347 (if (buffer-file-name)
8348 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
8349 ;; Allow user to customize
8350 (run-hooks 'verilog-before-delete-auto-hook)
8352 ;; Remove those that have multi-line insertions, possibly with parameters
8353 (verilog-auto-re-search-do
8356 (verilog-regexp-words
8357 `("AUTOASCIIENUM" "AUTOCONCATCOMMENT" "AUTODEFINEVALUE"
8358 "AUTOINOUT" "AUTOINOUTCOMP" "AUTOINOUTMODULE"
8359 "AUTOINPUT" "AUTOINSERTLISP" "AUTOOUTPUT" "AUTOOUTPUTEVERY"
8360 "AUTOREG" "AUTOREGINPUT" "AUTORESET" "AUTOTIEOFF"
8361 "AUTOUNUSED" "AUTOWIRE")))
8362 ;; Optional parens or quoted parameter or .* for (((...)))
8363 "\\(\\|([^)]*)\\|(\"[^\"]*\")\\).*?"
8365 'verilog-delete-autos-lined)
8366 ;; Remove those that are in parenthesis
8367 (verilog-auto-re-search-do
8370 (verilog-regexp-words
8371 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
8374 'verilog-delete-to-paren)
8375 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
8376 (verilog-auto-re-search-do "\\.\\*"
8377 'verilog-delete-auto-star-all)
8378 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
8379 (goto-char (point-min))
8380 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)[ \tLT0-9]*$" nil t)
8384 (run-hooks 'verilog-delete-auto-hook)))
8390 (defun verilog-inject-auto ()
8391 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
8393 Any always @ blocks with sensitivity lists that match computed lists will
8394 be replaced with /*AS*/ comments.
8396 Any cells will get /*AUTOINST*/ added to the end of the pin list.
8397 Pins with have identical names will be deleted.
8399 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
8400 support adding new ports. You may wish to delete older ports yourself.
8404 module ExampInject (i, o);
8415 Typing \\[verilog-inject-auto] will make this into:
8417 module ExampInject (i, o/*AUTOARG*/
8422 always @ (/*AS*/i or j)
8433 (defun verilog-inject-arg ()
8434 "Inject AUTOARG into new code. See `verilog-inject-auto'."
8435 ;; Presume one module per file.
8437 (goto-char (point-min))
8438 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
8439 (let ((endmodp (save-excursion
8440 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
8442 ;; See if there's already a comment .. inside a comment so not verilog-re-search
8443 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
8444 (verilog-re-search-forward-quick ";" nil t)
8446 (verilog-backward-syntactic-ws)
8447 (backward-char 1) ; Moves to paren that closes argdecl's
8448 (when (looking-at ")")
8449 (insert "/*AUTOARG*/")))))))
8451 (defun verilog-inject-sense ()
8452 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
8454 (goto-char (point-min))
8455 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
8456 (let* ((start-pt (point))
8457 (modi (verilog-modi-current))
8458 (moddecls (verilog-modi-get-decls modi))
8463 (backward-char 1) ;; End )
8464 (when (not (verilog-re-search-backward "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
8465 (setq pre-sigs (verilog-signals-from-signame
8466 (verilog-read-signals start-pt (point)))
8467 got-sigs (verilog-auto-sense-sigs moddecls nil))
8468 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
8469 (verilog-signals-not-in got-sigs pre-sigs)))
8470 (delete-region start-pt (point))
8471 (insert "/*AS*/")))))))
8473 (defun verilog-inject-inst ()
8474 "Inject AUTOINST into new code. See `verilog-inject-auto'."
8476 (goto-char (point-min))
8477 ;; It's hard to distinguish modules; we'll instead search for pins.
8478 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
8479 (verilog-backward-open-paren) ;; Inst start
8481 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
8483 (verilog-forward-close-paren)) ;; Parameters done
8486 (let ((indent-pt (+ (current-column)))
8487 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
8488 (cond ((verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
8489 (goto-char end-pt)) ;; Already there, continue search with next instance
8491 ;; Delete identical interconnect
8492 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
8493 (while (verilog-re-search-forward "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
8494 (delete-region (match-beginning 0) (match-end 0))
8495 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
8496 (while (or (looking-at "[ \t\n\f,]+")
8497 (looking-at "//[^\n]*"))
8498 (delete-region (match-beginning 0) (match-end 0))
8499 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
8500 (verilog-forward-close-paren)
8502 ;; Not verilog-re-search, as we don't want to strip comments
8503 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
8504 (delete-region (match-beginning 0) (match-end 0)))
8506 (indent-to indent-pt)
8507 (insert "/*AUTOINST*/")))))))))
8513 (defun verilog-auto-save-check ()
8514 "On saving see if we need auto update."
8515 (cond ((not verilog-auto-save-policy)) ; disabled
8516 ((not (save-excursion
8518 (let ((case-fold-search nil))
8519 (goto-char (point-min))
8520 (re-search-forward "AUTO" nil t))))))
8521 ((eq verilog-auto-save-policy 'force)
8523 ((not (buffer-modified-p)))
8524 ((eq verilog-auto-update-tick (buffer-modified-tick))) ; up-to-date
8525 ((eq verilog-auto-save-policy 'detect)
8528 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
8530 ;; Don't ask again if didn't update
8531 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))))
8532 (when (not verilog-auto-star-save)
8533 (verilog-delete-auto-star-implicit))
8534 nil) ;; Always return nil -- we don't write the file ourselves
8536 (defun verilog-auto-read-locals ()
8537 "Return file local variable segment at bottom of file."
8539 (goto-char (point-max))
8540 (if (re-search-backward "Local Variables:" nil t)
8541 (buffer-substring-no-properties (point) (point-max))
8544 (defun verilog-auto-reeval-locals (&optional force)
8545 "Read file local variable segment at bottom of file if it has changed.
8546 If FORCE, always reread it."
8547 (make-local-variable 'verilog-auto-last-file-locals)
8548 (let ((curlocal (verilog-auto-read-locals)))
8549 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
8550 (setq verilog-auto-last-file-locals curlocal)
8551 ;; Note this may cause this function to be recursively invoked,
8552 ;; because hack-local-variables may call (verilog-mode)
8553 ;; The above when statement will prevent it from recursing forever.
8554 (hack-local-variables)
8561 (defun verilog-auto-arg-ports (sigs message indent-pt)
8562 "Print a list of ports for a AUTOINST.
8563 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
8565 (when verilog-auto-arg-sort
8566 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
8568 (indent-to indent-pt)
8572 (indent-to indent-pt)
8574 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
8576 (indent-to indent-pt))
8578 (insert (verilog-sig-name (car sigs)) ",")
8579 (setq sigs (cdr sigs)
8582 (defun verilog-auto-arg ()
8583 "Expand AUTOARG statements.
8584 Replace the argument declarations at the beginning of the
8585 module with ones automatically derived from input and output
8586 statements. This can be dangerous if the module is instantiated
8587 using position-based connections, so use only name-based when
8588 instantiating the resulting module. Long lines are split based
8589 on the `fill-column', see \\[set-fill-column].
8592 Concatenation and outputting partial busses is not supported.
8594 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8598 module ExampArg (/*AUTOARG*/);
8603 Typing \\[verilog-auto] will make this into:
8605 module ExampArg (/*AUTOARG*/
8615 The argument declarations may be printed in declaration order to best suit
8616 order based instantiations, or alphabetically, based on the
8617 `verilog-auto-arg-sort' variable.
8619 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
8620 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
8621 conservative guess on adding a comma for the first signal, if you have
8622 any ifdefs or complicated expressions before the AUTOARG you will need
8623 to choose the comma yourself.
8625 Avoid declaring ports manually, as it makes code harder to maintain."
8627 (let* ((modi (verilog-modi-current))
8628 (moddecls (verilog-modi-get-decls modi))
8629 (skip-pins (aref (verilog-read-arg-pins) 0)))
8630 (verilog-repair-open-comma)
8631 (verilog-auto-arg-ports (verilog-signals-not-in
8632 (verilog-decls-get-outputs moddecls)
8635 verilog-indent-level-declaration)
8636 (verilog-auto-arg-ports (verilog-signals-not-in
8637 (verilog-decls-get-inouts moddecls)
8640 verilog-indent-level-declaration)
8641 (verilog-auto-arg-ports (verilog-signals-not-in
8642 (verilog-decls-get-inputs moddecls)
8645 verilog-indent-level-declaration)
8646 (verilog-repair-close-comma)
8647 (unless (eq (char-before) ?/ )
8649 (indent-to verilog-indent-level-declaration))))
8651 (defun verilog-auto-inst-port-map (port-st)
8654 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
8655 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
8656 (defvar vl-modport nil "See `verilog-auto-inst'.") ; Prevent compile warning
8657 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
8658 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
8659 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
8661 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star par-values)
8662 "Print out a instantiation connection for this PORT-ST.
8663 Insert to INDENT-PT, use template TPL-LIST.
8664 @ are instantiation numbers, replaced with TPL-NUM.
8665 @\"(expression @)\" are evaluated, with @ as a variable.
8666 If FOR-STAR add comment it is a .* expansion.
8667 If PAR-VALUES replace final strings with these parameter values."
8668 (let* ((port (verilog-sig-name port-st))
8669 (tpl-ass (or (assoc port (car tpl-list))
8670 (verilog-auto-inst-port-map port-st)))
8671 ;; vl-* are documented for user use
8672 (vl-name (verilog-sig-name port-st))
8673 (vl-width (verilog-sig-width port-st))
8674 (vl-modport (verilog-sig-modport port-st))
8675 (vl-bits (if (or verilog-auto-inst-vector
8676 (not (assoc port vector-skip-list))
8677 (not (equal (verilog-sig-bits port-st)
8678 (verilog-sig-bits (assoc port vector-skip-list)))))
8679 (or (verilog-sig-bits port-st) "")
8681 (case-fold-search nil)
8682 (check-values par-values)
8684 ;; Replace parameters in bit-width
8685 (when (and check-values
8686 (not (equal vl-bits "")))
8688 (setq vl-bits (verilog-string-replace-matches
8689 (concat "\\<" (nth 0 (car check-values)) "\\>")
8690 (concat "(" (nth 1 (car check-values)) ")")
8692 check-values (cdr check-values)))
8693 (setq vl-bits (verilog-simplify-range-expression vl-bits))) ; Not in the loop for speed
8694 ;; Default net value if not found
8695 (setq tpl-net (concat port
8696 (if vl-modport (concat "." vl-modport) "")
8697 (if (verilog-sig-multidim port-st)
8698 (concat "/*" (verilog-sig-multidim-string port-st)
8702 (cond (tpl-ass ; Template of exact port name
8703 (setq tpl-net (nth 1 tpl-ass)))
8704 ((nth 1 tpl-list) ; Wildcards in template, search them
8705 (let ((wildcards (nth 1 tpl-list)))
8707 (when (string-match (nth 0 (car wildcards)) port)
8708 (setq tpl-ass (car wildcards) ; so allow @ parsing
8709 tpl-net (replace-match (nth 1 (car wildcards))
8711 (setq wildcards (cdr wildcards))))))
8712 ;; Parse Templated variable
8714 ;; Evaluate @"(lispcode)"
8715 (when (string-match "@\".*[^\\]\"" tpl-net)
8716 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
8719 (substring tpl-net 0 (match-beginning 0))
8721 (let* ((expr (match-string 1 tpl-net))
8724 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
8725 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
8726 (prin1 (eval (car (read-from-string expr)))
8727 (lambda (ch) ())))))
8728 (if (numberp value) (setq value (number-to-string value)))
8730 (substring tpl-net (match-end 0))))))
8731 ;; Replace @ and [] magic variables in final output
8732 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
8733 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
8735 (indent-to indent-pt)
8737 (indent-to verilog-auto-inst-column)
8738 (insert "(" tpl-net "),")
8740 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
8741 verilog-auto-inst-column))
8742 (insert " // Templated")
8743 (when verilog-auto-inst-template-numbers
8744 (insert " T" (int-to-string (nth 2 tpl-ass))
8745 " L" (int-to-string (nth 3 tpl-ass)))))
8747 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
8748 verilog-auto-inst-column))
8749 (insert " // Implicit .\*"))) ;For some reason the . or * must be escaped...
8751 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
8752 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
8753 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
8755 (defun verilog-auto-inst-first ()
8756 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
8757 ;; Do we need a trailing comma?
8758 ;; There maybe a ifdef or something similar before us. What a mess. Thus
8759 ;; to avoid trouble we only insert on preceeding ) or *.
8760 ;; Insert first port on new line
8761 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
8763 (verilog-re-search-backward "[^ \t\n\f]" nil nil)
8764 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
8768 (defun verilog-auto-star ()
8769 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
8771 If `verilog-auto-star-expand' is set, .* pins are treated if they were
8772 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
8773 will also ignore any .* that are not last in your pin list (this prevents
8774 it from deleting pins following the .* when it expands the AUTOINST.)
8776 On writing your file, unless `verilog-auto-star-save' is set, any
8777 non-templated expanded pins will be removed. You may do this at any time
8778 with \\[verilog-delete-auto-star-implicit].
8780 If you are converting a module to use .* for the first time, you may wish
8781 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
8783 See `verilog-auto-inst' for examples, templates, and more information."
8784 (when (verilog-auto-star-safe)
8785 (verilog-auto-inst)))
8787 (defun verilog-auto-inst ()
8788 "Expand AUTOINST statements, as part of \\[verilog-auto].
8789 Replace the pin connections to an instantiation with ones
8790 automatically derived from the module header of the instantiated netlist.
8792 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
8793 and delete them before saving unless `verilog-auto-star-save' is set.
8794 See `verilog-auto-star' for more information.
8797 Module names must be resolvable to filenames by adding a
8798 `verilog-library-extensions', and being found in the same directory, or
8799 by changing the variable `verilog-library-flags' or
8800 `verilog-library-directories'. Macros `modname are translated through the
8801 vh-{name} Emacs variable, if that is not found, it just ignores the `.
8803 In templates you must have one signal per line, ending in a ), or ));,
8804 and have proper () nesting, including a final ); to end the template.
8806 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8808 SystemVerilog multidimensional input/output has only experimental support.
8810 Parameters referenced by the instantiation will remain symbolic, unless
8811 `verilog-auto-inst-param-value' is set.
8813 For example, first take the submodule InstModule.v:
8815 module InstModule (o,i)
8818 wire [31:0] o = {32{i}};
8821 This is then used in a upper level module:
8823 module ExampInst (o,i)
8830 Typing \\[verilog-auto] will make this into:
8832 module ExampInst (o,i)
8843 Where the list of inputs and outputs came from the inst module.
8847 Unless you are instantiating a module multiple times, or the module is
8848 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
8849 It just makes for unmaintainable code. To sanitize signal names, try
8850 vrename from URL `http://www.veripool.org'.
8852 When you need to violate this suggestion there are two ways to list
8853 exceptions, placing them before the AUTOINST, or using templates.
8855 Any ports defined before the /*AUTOINST*/ are not included in the list of
8856 automatics. This is similar to making a template as described below, but
8857 is restricted to simple connections just like you normally make. Also note
8858 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
8859 you have the appropriate // Input or // Output comment, and exactly the
8860 same line formatting as AUTOINST itself uses.
8864 .i (my_i_dont_mess_with_it),
8872 For multiple instantiations based upon a single template, create a
8873 commented out template:
8875 /* InstModule AUTO_TEMPLATE (
8880 Templates go ABOVE the instantiation(s). When an instantiation is
8881 expanded `verilog-mode' simply searches up for the closest template.
8882 Thus you can have multiple templates for the same module, just alternate
8883 between the template for an instantiation and the instantiation itself.
8885 The module name must be the same as the name of the module in the
8886 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
8887 words and capitalized. Only signals that must be different for each
8888 instantiation need to be listed.
8890 Inside a template, a [] in a connection name (with nothing else inside
8891 the brackets) will be replaced by the same bus subscript as it is being
8892 connected to, or the [] will be removed if it is a single bit signal.
8893 Generally it is a good idea to do this for all connections in a template,
8894 as then they will work for any width signal, and with AUTOWIRE. See
8895 PTL_BUS becoming PTL_BUSNEW below.
8897 If you have a complicated template, set `verilog-auto-inst-template-numbers'
8898 to see which regexps are matching. Don't leave that mode set after
8899 debugging is completed though, it will result in lots of extra differences
8900 and merge conflicts.
8904 /* InstModule AUTO_TEMPLATE (
8905 .ptl_bus (ptl_busnew[]),
8908 InstModule ms2m (/*AUTOINST*/);
8910 Typing \\[verilog-auto] will make this into:
8912 InstModule ms2m (/*AUTOINST*/
8914 .NotInTemplate (NotInTemplate),
8915 .ptl_bus (ptl_busnew[3:0]), // Templated
8920 It is common to instantiate a cell multiple times, so templates make it
8921 trivial to substitute part of the cell name into the connection name.
8923 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
8925 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
8929 If no regular expression is provided immediately after the AUTO_TEMPLATE
8930 keyword, then the @ character in any connection names will be replaced
8931 with the instantiation number; the first digits found in the cell's
8934 If a regular expression is provided, the @ character will be replaced
8935 with the first \(\) grouping that matches against the cell name. Using a
8936 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
8937 regexp is provided. If you use multiple layers of parenthesis,
8938 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
8939 characters after test and before _, whereas
8940 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
8945 /* InstModule AUTO_TEMPLATE (
8946 .ptl_mapvalidx (ptl_mapvalid[@]),
8947 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
8950 InstModule ms2m (/*AUTOINST*/);
8952 Typing \\[verilog-auto] will make this into:
8954 InstModule ms2m (/*AUTOINST*/
8956 .ptl_mapvalidx (ptl_mapvalid[2]),
8957 .ptl_mapvalidp1x (ptl_mapvalid[3]));
8959 Note the @ character was replaced with the 2 from \"ms2m\".
8961 Alternatively, using a regular expression for @:
8963 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
8964 .ptl_mapvalidx (@_ptl_mapvalid),
8965 .ptl_mapvalidp1x (ptl_mapvalid_@),
8968 InstModule ms2_FOO (/*AUTOINST*/);
8969 InstModule ms2_BAR (/*AUTOINST*/);
8971 Typing \\[verilog-auto] will make this into:
8973 InstModule ms2_FOO (/*AUTOINST*/
8975 .ptl_mapvalidx (FOO_ptl_mapvalid),
8976 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
8977 InstModule ms2_BAR (/*AUTOINST*/
8979 .ptl_mapvalidx (BAR_ptl_mapvalid),
8980 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
8985 A template entry of the form
8987 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
8989 will apply an Emacs style regular expression search for any port beginning
8990 in pci_req followed by numbers and ending in _l and connecting that to
8991 the pci_req_jtag_[] net, with the bus subscript coming from what matches
8992 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
8994 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
8995 does the same thing. (Note a @ in the connection/replacement text is
8996 completely different -- still use \\1 there!) Thus this is the same as
8999 .pci_req@_l (pci_req_jtag_[\\1]),
9001 Here's another example to remove the _l, useful when naming conventions
9002 specify _ alone to mean active low. Note the use of [] to keep the bus
9005 .\\(.*\\)_l (\\1_[]),
9009 First any regular expression template is expanded.
9011 If the syntax @\"( ... )\" is found in a connection, the expression in
9012 quotes will be evaluated as a Lisp expression, with @ replaced by the
9013 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
9014 4 into the brackets. Quote all double-quotes inside the expression with
9015 a leading backslash (\\\"...\\\"); or if the Lisp template is also a
9016 regexp template backslash the backslash quote (\\\\\"...\\\\\").
9018 There are special variables defined that are useful in these
9021 vl-name Name portion of the input/output port.
9022 vl-bits Bus bits portion of the input/output port ('[2:0]').
9023 vl-width Width of the input/output port ('3' for [2:0]).
9024 May be a (...) expression if bits isn't a constant.
9025 vl-dir Direction of the pin input/output/inout/interface.
9026 vl-modport The modport, if an interface with a modport.
9027 vl-cell-type Module name/type of the cell ('InstModule').
9028 vl-cell-name Instance name of the cell ('instName').
9030 Normal Lisp variables may be used in expressions. See
9031 `verilog-read-defines' which can set vh-{definename} variables for use
9032 here. Also, any comments of the form:
9034 /*AUTO_LISP(setq foo 1)*/
9036 will evaluate any Lisp expression inside the parenthesis between the
9037 beginning of the buffer and the point of the AUTOINST. This allows
9038 functions to be defined or variables to be changed between instantiations.
9039 (See also `verilog-auto-insert-lisp' if you want the output from your
9040 lisp function to be inserted.)
9042 Note that when using lisp expressions errors may occur when @ is not a
9043 number; you may need to use the standard Emacs Lisp functions
9044 `number-to-string' and `string-to-number'.
9046 After the evaluation is completed, @ substitution and [] substitution
9049 For more information see the \\[verilog-faq] and forums at URL
9050 `http://www.veripool.org'."
9054 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
9055 (indent-pt (save-excursion (verilog-backward-open-paren)
9056 (1+ (current-column))))
9057 (verilog-auto-inst-column (max verilog-auto-inst-column
9058 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
9059 (modi (verilog-modi-current))
9060 (moddecls (verilog-modi-get-decls modi))
9061 (vector-skip-list (unless verilog-auto-inst-vector
9062 (verilog-decls-get-signals moddecls)))
9063 submod submodi submoddecls
9064 inst skip-pins tpl-list tpl-num did-first par-values)
9066 ;; Find module name that is instantiated
9067 (setq submod (verilog-read-inst-module)
9068 inst (verilog-read-inst-name)
9071 skip-pins (aref (verilog-read-inst-pins) 0))
9073 ;; Parse any AUTO_LISP() before here
9074 (verilog-read-auto-lisp (point-min) pt)
9076 ;; Read parameters (after AUTO_LISP)
9077 (setq par-values (and verilog-auto-inst-param-value
9078 (verilog-read-inst-param-value)))
9080 ;; Lookup position, etc of submodule
9081 ;; Note this may raise an error
9082 (when (setq submodi (verilog-modi-lookup submod t))
9083 (setq submoddecls (verilog-modi-get-decls submodi))
9084 ;; If there's a number in the instantiation, it may be a argument to the
9085 ;; automatic variable instantiation program.
9086 (let* ((tpl-info (verilog-read-auto-template submod))
9087 (tpl-regexp (aref tpl-info 0)))
9088 (setq tpl-num (if (string-match tpl-regexp inst)
9089 (match-string 1 inst)
9091 tpl-list (aref tpl-info 1)))
9092 ;; Find submodule's signals and dump
9093 (let ((sig-list (verilog-signals-not-in
9094 (verilog-decls-get-interfaces submoddecls)
9096 (vl-dir "interface"))
9098 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
9099 (indent-to indent-pt)
9100 ;; Note these are searched for in verilog-read-sub-decls.
9101 (insert "// Interfaces\n")
9102 (mapc (lambda (port)
9103 (verilog-auto-inst-port port indent-pt
9104 tpl-list tpl-num for-star par-values))
9106 (let ((sig-list (verilog-signals-not-in
9107 (verilog-decls-get-outputs submoddecls)
9111 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
9112 (indent-to indent-pt)
9113 (insert "// Outputs\n")
9114 (mapc (lambda (port)
9115 (verilog-auto-inst-port port indent-pt
9116 tpl-list tpl-num for-star par-values))
9118 (let ((sig-list (verilog-signals-not-in
9119 (verilog-decls-get-inouts submoddecls)
9123 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
9124 (indent-to indent-pt)
9125 (insert "// Inouts\n")
9126 (mapc (lambda (port)
9127 (verilog-auto-inst-port port indent-pt
9128 tpl-list tpl-num for-star par-values))
9130 (let ((sig-list (verilog-signals-not-in
9131 (verilog-decls-get-inputs submoddecls)
9135 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
9136 (indent-to indent-pt)
9137 (insert "// Inputs\n")
9138 (mapc (lambda (port)
9139 (verilog-auto-inst-port port indent-pt
9140 tpl-list tpl-num for-star par-values))
9145 (re-search-backward "," pt t)
9148 (search-forward "\n") ;; Added by inst-port
9149 (delete-backward-char 1)
9150 (if (search-forward ")" nil t) ;; From user, moved up a line
9151 (delete-backward-char 1))
9152 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
9153 (delete-backward-char 1)))))))))
9155 (defun verilog-auto-inst-param ()
9156 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
9157 Replace the parameter connections to an instantiation with ones
9158 automatically derived from the module header of the instantiated netlist.
9160 See \\[verilog-auto-inst] for limitations, and templates to customize the
9163 For example, first take the submodule InstModule.v:
9165 module InstModule (o,i)
9169 This is then used in a upper level module:
9171 module ExampInst (o,i)
9173 InstModule #(/*AUTOINSTPARAM*/)
9174 instName (/*AUTOINST*/);
9177 Typing \\[verilog-auto] will make this into:
9179 module ExampInst (o,i)
9182 InstModule #(/*AUTOINSTPARAM*/
9185 instName (/*AUTOINST*/);
9188 Where the list of parameter connections come from the inst module.
9192 You can customize the parameter connections using AUTO_TEMPLATEs,
9193 just as you would with \\[verilog-auto-inst]."
9197 (indent-pt (save-excursion (verilog-backward-open-paren)
9198 (1+ (current-column))))
9199 (verilog-auto-inst-column (max verilog-auto-inst-column
9200 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
9201 (modi (verilog-modi-current))
9202 (moddecls (verilog-modi-get-decls modi))
9203 (vector-skip-list (unless verilog-auto-inst-vector
9204 (verilog-decls-get-signals moddecls)))
9205 submod submodi submoddecls
9206 inst skip-pins tpl-list tpl-num did-first)
9207 ;; Find module name that is instantiated
9208 (setq submod (save-excursion
9209 ;; Get to the point where AUTOINST normally is to read the module
9210 (verilog-re-search-forward-quick "[(;]" nil nil)
9211 (verilog-read-inst-module))
9212 inst (save-excursion
9213 ;; Get to the point where AUTOINST normally is to read the module
9214 (verilog-re-search-forward-quick "[(;]" nil nil)
9215 (verilog-read-inst-name))
9218 skip-pins (aref (verilog-read-inst-pins) 0))
9220 ;; Parse any AUTO_LISP() before here
9221 (verilog-read-auto-lisp (point-min) pt)
9223 ;; Lookup position, etc of submodule
9224 ;; Note this may raise an error
9225 (when (setq submodi (verilog-modi-lookup submod t))
9226 (setq submoddecls (verilog-modi-get-decls submodi))
9227 ;; If there's a number in the instantiation, it may be a argument to the
9228 ;; automatic variable instantiation program.
9229 (let* ((tpl-info (verilog-read-auto-template submod))
9230 (tpl-regexp (aref tpl-info 0)))
9231 (setq tpl-num (if (string-match tpl-regexp inst)
9232 (match-string 1 inst)
9234 tpl-list (aref tpl-info 1)))
9235 ;; Find submodule's signals and dump
9236 (let ((sig-list (verilog-signals-not-in
9237 (verilog-decls-get-gparams submoddecls)
9239 (vl-dir "parameter"))
9241 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
9242 (indent-to indent-pt)
9243 ;; Note these are searched for in verilog-read-sub-decls.
9244 (insert "// Parameters\n")
9245 (mapc (lambda (port)
9246 (verilog-auto-inst-port port indent-pt
9247 tpl-list tpl-num nil nil))
9252 (re-search-backward "," pt t)
9255 (search-forward "\n") ;; Added by inst-port
9256 (delete-backward-char 1)
9257 (if (search-forward ")" nil t) ;; From user, moved up a line
9258 (delete-backward-char 1)))))))))
9260 (defun verilog-auto-reg ()
9261 "Expand AUTOREG statements, as part of \\[verilog-auto].
9262 Make reg statements for any output that isn't already declared,
9263 and isn't a wire output from a block.
9266 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
9268 This does NOT work on memories, declare those yourself.
9272 module ExampReg (o,i)
9279 Typing \\[verilog-auto] will make this into:
9281 module ExampReg (o,i)
9285 // Beginning of automatic regs (for this module's undeclared outputs)
9287 // End of automatics
9291 ;; Point must be at insertion point.
9292 (let* ((indent-pt (current-indentation))
9293 (modi (verilog-modi-current))
9294 (moddecls (verilog-modi-get-decls modi))
9295 (modsubdecls (verilog-modi-get-sub-decls modi))
9296 (sig-list (verilog-signals-not-in
9297 (verilog-decls-get-outputs moddecls)
9298 (append (verilog-decls-get-wires moddecls)
9299 (verilog-decls-get-regs moddecls)
9300 (verilog-decls-get-assigns moddecls)
9301 (verilog-decls-get-consts moddecls)
9302 (verilog-decls-get-gparams moddecls)
9303 (verilog-subdecls-get-outputs modsubdecls)
9304 (verilog-subdecls-get-inouts modsubdecls)))))
9307 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
9308 (verilog-insert-definition sig-list "reg" indent-pt nil)
9309 (verilog-modi-cache-add-regs modi sig-list)
9310 (verilog-insert-indent "// End of automatics\n")))))
9312 (defun verilog-auto-reg-input ()
9313 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
9314 Make reg statements instantiation inputs that aren't already declared.
9315 This is useful for making a top level shell for testing the module that is
9319 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
9321 This does NOT work on memories, declare those yourself.
9323 An example (see `verilog-auto-inst' for what else is going on here):
9325 module ExampRegInput (o,i)
9333 Typing \\[verilog-auto] will make this into:
9335 module ExampRegInput (o,i)
9339 // Beginning of automatic reg inputs (for undeclared ...
9340 reg [31:0] iv; // From inst of inst.v
9341 // End of automatics
9350 ;; Point must be at insertion point.
9351 (let* ((indent-pt (current-indentation))
9352 (modi (verilog-modi-current))
9353 (moddecls (verilog-modi-get-decls modi))
9354 (modsubdecls (verilog-modi-get-sub-decls modi))
9355 (sig-list (verilog-signals-combine-bus
9356 (verilog-signals-not-in
9357 (append (verilog-subdecls-get-inputs modsubdecls)
9358 (verilog-subdecls-get-inouts modsubdecls))
9359 (verilog-decls-get-signals moddecls)))))
9362 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
9363 (verilog-insert-definition sig-list "reg" indent-pt nil)
9364 (verilog-modi-cache-add-regs modi sig-list)
9365 (verilog-insert-indent "// End of automatics\n")))))
9367 (defun verilog-auto-wire ()
9368 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
9369 Make wire statements for instantiations outputs that aren't
9373 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
9374 and all busses must have widths, such as those from AUTOINST, or using []
9377 This does NOT work on memories or SystemVerilog .name connections,
9378 declare those yourself.
9380 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
9381 determine how to bus together. This occurs when you have ports with
9382 non-numeric or non-sequential bus subscripts. If Verilog mode
9383 mis-guessed, you'll have to declare them yourself.
9385 An example (see `verilog-auto-inst' for what else is going on here):
9387 module ExampWire (o,i)
9395 Typing \\[verilog-auto] will make this into:
9397 module ExampWire (o,i)
9401 // Beginning of automatic wires
9402 wire [31:0] ov; // From inst of inst.v
9403 // End of automatics
9413 ;; Point must be at insertion point.
9414 (let* ((indent-pt (current-indentation))
9415 (modi (verilog-modi-current))
9416 (moddecls (verilog-modi-get-decls modi))
9417 (modsubdecls (verilog-modi-get-sub-decls modi))
9418 (sig-list (verilog-signals-combine-bus
9419 (verilog-signals-not-in
9420 (append (verilog-subdecls-get-outputs modsubdecls)
9421 (verilog-subdecls-get-inouts modsubdecls))
9422 (verilog-decls-get-signals moddecls)))))
9425 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
9426 (verilog-insert-definition sig-list "wire" indent-pt nil)
9427 (verilog-modi-cache-add-wires modi sig-list)
9428 (verilog-insert-indent "// End of automatics\n")
9429 (when nil ;; Too slow on huge modules, plus makes everyone's module change
9432 (verilog-pretty-declarations quiet)
9434 (verilog-pretty-expr t "//"))))))
9436 (defun verilog-auto-output (&optional with-params)
9437 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
9438 Make output statements for any output signal from an /*AUTOINST*/ that
9439 isn't a input to another AUTOINST. This is useful for modules which
9440 only instantiate other modules.
9443 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
9445 If placed inside the parenthesis of a module declaration, it creates
9446 Verilog 2001 style, else uses Verilog 1995 style.
9448 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
9449 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
9451 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
9453 Signals matching `verilog-auto-output-ignore-regexp' are not included.
9455 An example (see `verilog-auto-inst' for what else is going on here):
9457 module ExampOutput (ov,i)
9464 Typing \\[verilog-auto] will make this into:
9466 module ExampOutput (ov,i)
9469 // Beginning of automatic outputs (from unused autoinst outputs)
9470 output [31:0] ov; // From inst of inst.v
9471 // End of automatics
9480 You may also provide an optional regular expression, in which case only
9481 signals matching the regular expression will be included. For example the
9482 same expansion will result from only extracting outputs starting with ov:
9484 /*AUTOOUTPUT(\"^ov\")*/"
9486 ;; Point must be at insertion point.
9487 (let* ((indent-pt (current-indentation))
9488 (regexp (and with-params
9489 (nth 0 (verilog-read-auto-params 1))))
9490 (v2k (verilog-in-paren))
9491 (modi (verilog-modi-current))
9492 (moddecls (verilog-modi-get-decls modi))
9493 (modsubdecls (verilog-modi-get-sub-decls modi))
9494 (sig-list (verilog-signals-not-in
9495 (verilog-subdecls-get-outputs modsubdecls)
9496 (append (verilog-decls-get-outputs moddecls)
9497 (verilog-decls-get-inouts moddecls)
9498 (verilog-subdecls-get-inputs modsubdecls)
9499 (verilog-subdecls-get-inouts modsubdecls)))))
9501 (setq sig-list (verilog-signals-matching-regexp
9503 (setq sig-list (verilog-signals-not-matching-regexp
9504 sig-list verilog-auto-output-ignore-regexp))
9506 (when v2k (verilog-repair-open-comma))
9508 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
9509 (verilog-insert-definition sig-list "output" indent-pt v2k)
9510 (verilog-modi-cache-add-outputs modi sig-list)
9511 (verilog-insert-indent "// End of automatics\n"))
9512 (when v2k (verilog-repair-close-comma)))))
9514 (defun verilog-auto-output-every ()
9515 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
9516 Make output statements for any signals that aren't primary inputs or
9517 outputs already. This makes every signal in the design a output. This is
9518 useful to get Synopsys to preserve every signal in the design, since it
9519 won't optimize away the outputs.
9523 module ExampOutputEvery (o,i,tempa,tempb)
9532 Typing \\[verilog-auto] will make this into:
9534 module ExampOutputEvery (o,i,tempa,tempb)
9538 // Beginning of automatic outputs (every signal)
9541 // End of automatics
9547 ;;Point must be at insertion point
9548 (let* ((indent-pt (current-indentation))
9549 (v2k (verilog-in-paren))
9550 (modi (verilog-modi-current))
9551 (moddecls (verilog-modi-get-decls modi))
9552 (sig-list (verilog-signals-combine-bus
9553 (verilog-signals-not-in
9554 (verilog-decls-get-signals moddecls)
9555 (verilog-decls-get-ports moddecls)))))
9557 (when v2k (verilog-repair-open-comma))
9559 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
9560 (verilog-insert-definition sig-list "output" indent-pt v2k)
9561 (verilog-modi-cache-add-outputs modi sig-list)
9562 (verilog-insert-indent "// End of automatics\n"))
9563 (when v2k (verilog-repair-close-comma)))))
9565 (defun verilog-auto-input (&optional with-params)
9566 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
9567 Make input statements for any input signal into an /*AUTOINST*/ that
9568 isn't declared elsewhere inside the module. This is useful for modules which
9569 only instantiate other modules.
9572 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
9574 If placed inside the parenthesis of a module declaration, it creates
9575 Verilog 2001 style, else uses Verilog 1995 style.
9577 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
9578 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
9580 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
9582 Signals matching `verilog-auto-input-ignore-regexp' are not included.
9584 An example (see `verilog-auto-inst' for what else is going on here):
9586 module ExampInput (ov,i)
9593 Typing \\[verilog-auto] will make this into:
9595 module ExampInput (ov,i)
9598 // Beginning of automatic inputs (from unused autoinst inputs)
9599 input i; // From inst of inst.v
9600 // End of automatics
9609 You may also provide an optional regular expression, in which case only
9610 signals matching the regular expression will be included. For example the
9611 same expansion will result from only extracting inputs starting with i:
9613 /*AUTOINPUT(\"^i\")*/"
9615 (let* ((indent-pt (current-indentation))
9616 (regexp (and with-params
9617 (nth 0 (verilog-read-auto-params 1))))
9618 (v2k (verilog-in-paren))
9619 (modi (verilog-modi-current))
9620 (moddecls (verilog-modi-get-decls modi))
9621 (modsubdecls (verilog-modi-get-sub-decls modi))
9622 (sig-list (verilog-signals-not-in
9623 (verilog-subdecls-get-inputs modsubdecls)
9624 (append (verilog-decls-get-inputs moddecls)
9625 (verilog-decls-get-inouts moddecls)
9626 (verilog-decls-get-wires moddecls)
9627 (verilog-decls-get-regs moddecls)
9628 (verilog-decls-get-consts moddecls)
9629 (verilog-decls-get-gparams moddecls)
9630 (verilog-subdecls-get-outputs modsubdecls)
9631 (verilog-subdecls-get-inouts modsubdecls)))))
9633 (setq sig-list (verilog-signals-matching-regexp
9635 (setq sig-list (verilog-signals-not-matching-regexp
9636 sig-list verilog-auto-input-ignore-regexp))
9638 (when v2k (verilog-repair-open-comma))
9640 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
9641 (verilog-insert-definition sig-list "input" indent-pt v2k)
9642 (verilog-modi-cache-add-inputs modi sig-list)
9643 (verilog-insert-indent "// End of automatics\n"))
9644 (when v2k (verilog-repair-close-comma)))))
9646 (defun verilog-auto-inout (&optional with-params)
9647 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
9648 Make inout statements for any inout signal in an /*AUTOINST*/ that
9649 isn't declared elsewhere inside the module.
9652 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
9654 If placed inside the parenthesis of a module declaration, it creates
9655 Verilog 2001 style, else uses Verilog 1995 style.
9657 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
9658 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
9660 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
9662 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
9664 An example (see `verilog-auto-inst' for what else is going on here):
9666 module ExampInout (ov,i)
9673 Typing \\[verilog-auto] will make this into:
9675 module ExampInout (ov,i)
9678 // Beginning of automatic inouts (from unused autoinst inouts)
9679 inout [31:0] ov; // From inst of inst.v
9680 // End of automatics
9689 You may also provide an optional regular expression, in which case only
9690 signals matching the regular expression will be included. For example the
9691 same expansion will result from only extracting inouts starting with i:
9693 /*AUTOINOUT(\"^i\")*/"
9695 ;; Point must be at insertion point.
9696 (let* ((indent-pt (current-indentation))
9697 (regexp (and with-params
9698 (nth 0 (verilog-read-auto-params 1))))
9699 (v2k (verilog-in-paren))
9700 (modi (verilog-modi-current))
9701 (moddecls (verilog-modi-get-decls modi))
9702 (modsubdecls (verilog-modi-get-sub-decls modi))
9703 (sig-list (verilog-signals-not-in
9704 (verilog-subdecls-get-inouts modsubdecls)
9705 (append (verilog-decls-get-outputs moddecls)
9706 (verilog-decls-get-inouts moddecls)
9707 (verilog-decls-get-inputs moddecls)
9708 (verilog-subdecls-get-inputs modsubdecls)
9709 (verilog-subdecls-get-outputs modsubdecls)))))
9711 (setq sig-list (verilog-signals-matching-regexp
9713 (setq sig-list (verilog-signals-not-matching-regexp
9714 sig-list verilog-auto-inout-ignore-regexp))
9716 (when v2k (verilog-repair-open-comma))
9718 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
9719 (verilog-insert-definition sig-list "inout" indent-pt v2k)
9720 (verilog-modi-cache-add-inouts modi sig-list)
9721 (verilog-insert-indent "// End of automatics\n"))
9722 (when v2k (verilog-repair-close-comma)))))
9724 (defun verilog-auto-inout-module (&optional complement)
9725 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
9726 Take input/output/inout statements from the specified module and insert
9727 into the current module. This is useful for making null templates and
9728 shell modules which need to have identical I/O with another module.
9729 Any I/O which are already defined in this module will not be redefined.
9732 If placed inside the parenthesis of a module declaration, it creates
9733 Verilog 2001 style, else uses Verilog 1995 style.
9735 Concatenation and outputting partial busses is not supported.
9737 Module names must be resolvable to filenames. See `verilog-auto-inst'.
9739 Signals are not inserted in the same order as in the original module,
9740 though they will appear to be in the same order to a AUTOINST
9741 instantiating either module.
9745 module ExampShell (/*AUTOARG*/)
9746 /*AUTOINOUTMODULE(\"ExampMain\")*/
9749 module ExampMain (i,o,io)
9755 Typing \\[verilog-auto] will make this into:
9757 module ExampShell (/*AUTOARG*/i,o,io)
9758 /*AUTOINOUTMODULE(\"ExampMain\")*/
9759 // Beginning of automatic in/out/inouts (from specific module)
9763 // End of automatics
9766 You may also provide an optional regular expression, in which case only
9767 signals matching the regular expression will be included. For example the
9768 same expansion will result from only extracting signals starting with i:
9770 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
9772 You may also provide an optional second regular expression, in
9773 which case only signals which have that pin direction and data
9774 type will be included. This matches against everything before
9775 the signal name in the declaration, for example against
9776 \"input\" (single bit), \"output logic\" (direction and type) or
9777 \"output [1:0]\" (direction and implicit type). You also
9778 probably want to skip spaces in your regexp.
9780 For example, the below will result in matching the output \"o\"
9781 against the previous example's module:
9783 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/"
9785 (let* ((params (verilog-read-auto-params 1 3))
9786 (submod (nth 0 params))
9787 (regexp (nth 1 params))
9788 (direction-re (nth 2 params))
9790 ;; Lookup position, etc of co-module
9791 ;; Note this may raise an error
9792 (when (setq submodi (verilog-modi-lookup submod t))
9793 (let* ((indent-pt (current-indentation))
9794 (v2k (verilog-in-paren))
9795 (modi (verilog-modi-current))
9796 (moddecls (verilog-modi-get-decls modi))
9797 (submoddecls (verilog-modi-get-decls submodi))
9798 (sig-list-i (verilog-signals-not-in
9800 (verilog-decls-get-outputs submoddecls)
9801 (verilog-decls-get-inputs submoddecls))
9802 (append (verilog-decls-get-inputs moddecls))))
9803 (sig-list-o (verilog-signals-not-in
9805 (verilog-decls-get-inputs submoddecls)
9806 (verilog-decls-get-outputs submoddecls))
9807 (append (verilog-decls-get-outputs moddecls))))
9808 (sig-list-io (verilog-signals-not-in
9809 (verilog-decls-get-inouts submoddecls)
9810 (append (verilog-decls-get-inouts moddecls))))
9811 (sig-list-if (verilog-signals-not-in
9812 (verilog-decls-get-interfaces submoddecls)
9813 (append (verilog-decls-get-interfaces moddecls)))))
9815 (setq sig-list-i (verilog-signals-matching-dir-re
9816 (verilog-signals-matching-regexp sig-list-i regexp)
9817 "input" direction-re)
9818 sig-list-o (verilog-signals-matching-dir-re
9819 (verilog-signals-matching-regexp sig-list-o regexp)
9820 "output" direction-re)
9821 sig-list-io (verilog-signals-matching-dir-re
9822 (verilog-signals-matching-regexp sig-list-io regexp)
9823 "inout" direction-re)
9824 sig-list-if (verilog-signals-matching-dir-re
9825 (verilog-signals-matching-regexp sig-list-if regexp)
9826 "interface" direction-re))
9827 (when v2k (verilog-repair-open-comma))
9828 (when (or sig-list-i sig-list-o sig-list-io)
9829 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
9830 ;; Don't sort them so a upper AUTOINST will match the main module
9831 (verilog-insert-definition sig-list-o "output" indent-pt v2k t)
9832 (verilog-insert-definition sig-list-io "inout" indent-pt v2k t)
9833 (verilog-insert-definition sig-list-i "input" indent-pt v2k t)
9834 (verilog-insert-definition sig-list-if "interface" indent-pt v2k t)
9835 (verilog-modi-cache-add-inputs modi sig-list-i)
9836 (verilog-modi-cache-add-outputs modi sig-list-o)
9837 (verilog-modi-cache-add-inouts modi sig-list-io)
9838 (verilog-insert-indent "// End of automatics\n"))
9839 (when v2k (verilog-repair-close-comma)))))))
9841 (defun verilog-auto-inout-comp ()
9842 "Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
9843 Take input/output/inout statements from the specified module and
9844 insert the inverse into the current module (inputs become outputs
9845 and vice-versa.) This is useful for making test and stimulus
9846 modules which need to have complementing I/O with another module.
9847 Any I/O which are already defined in this module will not be
9851 If placed inside the parenthesis of a module declaration, it creates
9852 Verilog 2001 style, else uses Verilog 1995 style.
9854 Concatenation and outputting partial busses is not supported.
9856 Module names must be resolvable to filenames. See `verilog-auto-inst'.
9858 Signals are not inserted in the same order as in the original module,
9859 though they will appear to be in the same order to a AUTOINST
9860 instantiating either module.
9864 module ExampShell (/*AUTOARG*/)
9865 /*AUTOINOUTCOMP(\"ExampMain\")*/
9868 module ExampMain (i,o,io)
9874 Typing \\[verilog-auto] will make this into:
9876 module ExampShell (/*AUTOARG*/i,o,io)
9877 /*AUTOINOUTCOMP(\"ExampMain\")*/
9878 // Beginning of automatic in/out/inouts (from specific module)
9882 // End of automatics
9885 You may also provide an optional regular expression, in which case only
9886 signals matching the regular expression will be included. For example the
9887 same expansion will result from only extracting signals starting with i:
9889 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
9890 (verilog-auto-inout-module t))
9892 (defun verilog-auto-insert-lisp ()
9893 "Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
9894 The Lisp code provided is called, and the Lisp code calls
9895 `insert` to insert text into the current file beginning on the
9896 line after the AUTOINSERTLISP.
9898 See also AUTO_LISP, which takes a Lisp expression and evaluates
9899 it during `verilog-auto-inst' but does not insert any text.
9903 module ExampInsertLisp;
9904 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
9907 // For this example we declare the function in the
9908 // module's file itself. Often you'd define it instead
9909 // in a site-start.el or .emacs file.
9913 (defun my-verilog-insert-hello (who)
9914 (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
9918 Typing \\[verilog-auto] will call my-verilog-insert-hello and
9919 expand the above into:
9921 // Beginning of automatic insert lisp
9922 initial $write(\"hello world\");
9923 // End of automatics
9925 You can also call an external program and insert the returned
9928 /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
9929 // Beginning of automatic insert lisp
9931 // End of automatics"
9933 ;; Point is at end of /*AUTO...*/
9934 (let* ((indent-pt (current-indentation))
9935 (cmd-end-pt (save-excursion (search-backward ")")
9937 (point))) ;; Closing paren
9938 (cmd-beg-pt (save-excursion (goto-char cmd-end-pt)
9940 (point))) ;; Beginning paren
9941 (cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
9943 ;; Some commands don't move point (like insert-file) so we always
9944 ;; add the begin/end comments, then delete it if not needed
9945 (verilog-insert-indent "// Beginning of automatic insert lisp\n")
9946 (verilog-insert-indent "// End of automatics\n")
9950 (verilog-delete-empty-auto-pair))))
9952 (defun verilog-auto-sense-sigs (moddecls presense-sigs)
9953 "Return list of signals for current AUTOSENSE block."
9954 (let* ((sigss (verilog-read-always-signals))
9955 (sig-list (verilog-signals-not-params
9956 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
9957 (append (and (not verilog-auto-sense-include-inputs)
9958 (verilog-alw-get-outputs sigss))
9959 (verilog-decls-get-consts moddecls)
9960 (verilog-decls-get-gparams moddecls)
9964 (defun verilog-auto-sense ()
9965 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
9966 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
9967 with one automatically derived from all inputs declared in the always
9968 statement. Signals that are generated within the same always block are NOT
9969 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
9970 Long lines are split based on the `fill-column', see \\[set-fill-column].
9973 Verilog does not allow memories (multidimensional arrays) in sensitivity
9974 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
9977 AUTOSENSE cannot always determine if a `define is a constant or a signal
9978 (it could be in a include file for example). If a `define or other signal
9979 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
9980 declaration anywhere in the module (parenthesis are required):
9982 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
9984 Better yet, use a parameter, which will be understood to be constant
9988 If AUTOSENSE makes a mistake, please report it. (First try putting
9989 a begin/end after your always!) As a workaround, if a signal that
9990 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
9991 If a signal should be in the sensitivity list wasn't, placing it before
9992 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
9993 autos are updated (or added if it occurs there already).
9997 always @ (/*AS*/) begin
9998 /* AUTO_CONSTANT (`constant) */
9999 outin = ina | inb | `constant;
10003 Typing \\[verilog-auto] will make this into:
10005 always @ (/*AS*/ina or inb) begin
10006 /* AUTO_CONSTANT (`constant) */
10007 outin = ina | inb | `constant;
10011 Note in Verilog 2001, you can often get the same result from the new @*
10012 operator. (This was added to the language in part due to AUTOSENSE!)
10015 outin = ina | inb | `constant;
10020 (let* ((start-pt (save-excursion
10021 (verilog-re-search-backward "(" nil t)
10023 (indent-pt (save-excursion
10024 (or (and (goto-char start-pt) (1+ (current-column)))
10025 (current-indentation))))
10026 (modi (verilog-modi-current))
10027 (moddecls (verilog-modi-get-decls modi))
10028 (sig-memories (verilog-signals-memory
10030 (verilog-decls-get-regs moddecls)
10031 (verilog-decls-get-wires moddecls))))
10032 sig-list not-first presense-sigs)
10033 ;; Read signals in always, eliminate outputs from sense list
10034 (setq presense-sigs (verilog-signals-from-signame
10036 (verilog-read-signals start-pt (point)))))
10037 (setq sig-list (verilog-auto-sense-sigs moddecls presense-sigs))
10039 (let ((tlen (length sig-list)))
10040 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
10041 (if (not (eq tlen (length sig-list))) (insert " /*memory or*/ "))))
10042 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
10043 (save-excursion (goto-char (point))
10044 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
10045 (verilog-re-search-backward "\\s-" start-pt t)
10046 (while (looking-at "\\s-`endif")
10047 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
10048 (verilog-re-search-backward "\\s-" start-pt t))
10049 (not (looking-at "\\s-or\\b"))))
10050 (setq not-first t))
10051 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
10053 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
10055 (indent-to indent-pt)
10056 (if not-first (insert "or ")))
10057 (not-first (insert " or ")))
10058 (insert (verilog-sig-name (car sig-list)))
10059 (setq sig-list (cdr sig-list)
10062 (defun verilog-auto-reset ()
10063 "Expand AUTORESET statements, as part of \\[verilog-auto].
10064 Replace the /*AUTORESET*/ comment with code to initialize all
10065 registers set elsewhere in the always block.
10068 AUTORESET will not clear memories.
10070 AUTORESET uses <= if there are any <= assigmnents in the block,
10073 /*AUTORESET*/ presumes that any signals mentioned between the previous
10074 begin/case/if statement and the AUTORESET comment are being reset manually
10075 and should not be automatically reset. This includes omitting any signals
10076 used on the right hand side of assignments.
10078 By default, AUTORESET will include the width of the signal in the autos,
10079 this is a recent change. To control this behavior, see
10080 `verilog-auto-reset-widths'.
10082 AUTORESET ties signals to deasserted, which is presumed to be zero.
10083 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
10088 always @(posedge clk or negedge reset_l) begin
10089 if (!reset_l) begin
10100 Typing \\[verilog-auto] will make this into:
10102 always @(posedge core_clk or negedge reset_l) begin
10103 if (!reset_l) begin
10106 // Beginning of autoreset for uninitialized flops
10109 // End of automatics
10121 (let* ((indent-pt (current-indentation))
10122 (modi (verilog-modi-current))
10123 (moddecls (verilog-modi-get-decls modi))
10124 (all-list (verilog-decls-get-signals moddecls))
10125 sigss sig-list prereset-sigs assignment-str)
10126 ;; Read signals in always, eliminate outputs from reset list
10127 (setq prereset-sigs (verilog-signals-from-signame
10129 (verilog-read-signals
10131 (verilog-re-search-backward "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
10135 (verilog-re-search-backward "@" nil t)
10136 (setq sigss (verilog-read-always-signals)))
10137 (setq assignment-str (if (verilog-alw-get-uses-delayed sigss)
10138 (concat " <= " verilog-assignment-delay)
10140 (setq sig-list (verilog-signals-not-in (verilog-alw-get-outputs sigss)
10142 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
10145 (indent-to indent-pt)
10146 (insert "// Beginning of autoreset for uninitialized flops\n");
10147 (indent-to indent-pt)
10149 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
10151 (insert (verilog-sig-name sig)
10153 (verilog-sig-tieoff sig (not verilog-auto-reset-widths))
10155 (indent-to indent-pt)
10156 (setq sig-list (cdr sig-list))))
10157 (insert "// End of automatics")))))
10159 (defun verilog-auto-tieoff ()
10160 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
10161 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
10162 signals to deasserted.
10164 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
10165 input/output list as another module, but no internals. Specifically, it
10166 finds all outputs in the module, and if that input is not otherwise declared
10167 as a register or wire, creates a tieoff.
10169 AUTORESET ties signals to deasserted, which is presumed to be zero.
10170 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
10173 An example of making a stub for another module:
10175 module ExampStub (/*AUTOINST*/);
10176 /*AUTOINOUTMODULE(\"Foo\")*/
10178 // verilator lint_off UNUSED
10179 wire _unused_ok = &{1'b0,
10182 // verilator lint_on UNUSED
10185 Typing \\[verilog-auto] will make this into:
10187 module ExampStub (/*AUTOINST*/...);
10188 /*AUTOINOUTMODULE(\"Foo\")*/
10189 // Beginning of autotieoff
10191 // End of automatics
10194 // Beginning of autotieoff
10195 wire [2:0] foo = 3'b0;
10196 // End of automatics
10202 (let* ((indent-pt (current-indentation))
10203 (modi (verilog-modi-current))
10204 (moddecls (verilog-modi-get-decls modi))
10205 (modsubdecls (verilog-modi-get-sub-decls modi))
10206 (sig-list (verilog-signals-not-in
10207 (verilog-decls-get-outputs moddecls)
10208 (append (verilog-decls-get-wires moddecls)
10209 (verilog-decls-get-regs moddecls)
10210 (verilog-decls-get-assigns moddecls)
10211 (verilog-decls-get-consts moddecls)
10212 (verilog-decls-get-gparams moddecls)
10213 (verilog-subdecls-get-outputs modsubdecls)
10214 (verilog-subdecls-get-inouts modsubdecls)))))
10217 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
10218 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
10219 (verilog-modi-cache-add-wires modi sig-list) ; Before we trash list
10221 (let ((sig (car sig-list)))
10222 (verilog-insert-one-definition sig "wire" indent-pt)
10223 (indent-to (max 48 (+ indent-pt 40)))
10224 (insert "= " (verilog-sig-tieoff sig)
10226 (setq sig-list (cdr sig-list))))
10227 (verilog-insert-indent "// End of automatics\n")))))
10229 (defun verilog-auto-unused ()
10230 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
10231 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
10232 input and inout signals.
10234 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
10235 input/output list as another module, but no internals. Specifically, it
10236 finds all inputs and inouts in the module, and if that input is not otherwise
10237 used, adds it to a comma separated list.
10239 The comma separated list is intended to be used to create a _unused_ok
10240 signal. Using the exact name \"_unused_ok\" for name of the temporary
10241 signal is recommended as it will insure maximum forward compatibility, it
10242 also makes lint warnings easy to understand; ignore any unused warnings
10243 with \"unused\" in the signal name.
10245 To reduce simulation time, the _unused_ok signal should be forced to a
10246 constant to prevent wiggling. The easiest thing to do is use a
10247 reduction-and with 1'b0 as shown.
10249 This way all unused signals are in one place, making it convenient to add
10250 your tool's specific pragmas around the assignment to disable any unused
10253 You can add signals you do not want included in AUTOUNUSED with
10254 `verilog-auto-unused-ignore-regexp'.
10256 An example of making a stub for another module:
10258 module ExampStub (/*AUTOINST*/);
10259 /*AUTOINOUTMODULE(\"Examp\")*/
10261 // verilator lint_off UNUSED
10262 wire _unused_ok = &{1'b0,
10265 // verilator lint_on UNUSED
10268 Typing \\[verilog-auto] will make this into:
10271 // verilator lint_off UNUSED
10272 wire _unused_ok = &{1'b0,
10274 // Beginning of automatics
10278 // End of automatics
10280 // verilator lint_on UNUSED
10285 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
10286 (modi (verilog-modi-current))
10287 (moddecls (verilog-modi-get-decls modi))
10288 (modsubdecls (verilog-modi-get-sub-decls modi))
10289 (sig-list (verilog-signals-not-in
10290 (append (verilog-decls-get-inputs moddecls)
10291 (verilog-decls-get-inouts moddecls))
10292 (append (verilog-subdecls-get-inputs modsubdecls)
10293 (verilog-subdecls-get-inouts modsubdecls)))))
10294 (setq sig-list (verilog-signals-not-matching-regexp
10295 sig-list verilog-auto-unused-ignore-regexp))
10298 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
10299 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
10301 (let ((sig (car sig-list)))
10302 (indent-to indent-pt)
10303 (insert (verilog-sig-name sig) ",\n")
10304 (setq sig-list (cdr sig-list))))
10305 (verilog-insert-indent "// End of automatics\n")))))
10307 (defun verilog-enum-ascii (signm elim-regexp)
10308 "Convert an enum name SIGNM to an ascii string for insertion.
10309 Remove user provided prefix ELIM-REGEXP."
10310 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
10311 (let ((case-fold-search t))
10312 ;; All upper becomes all lower for readability
10313 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
10315 (defun verilog-auto-ascii-enum ()
10316 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
10317 Create a register to contain the ASCII decode of a enumerated signal type.
10318 This will allow trace viewers to show the ASCII name of states.
10320 First, parameters are built into a enumeration using the synopsys enum
10321 comment. The comment must be between the keyword and the symbol.
10322 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
10324 Next, registers which that enum applies to are also tagged with the same
10325 enum. Synopsys also suggests labeling state vectors, but `verilog-mode'
10328 Finally, a AUTOASCIIENUM command is used.
10330 The first parameter is the name of the signal to be decoded.
10331 If and only if the first parameter width is 2^(number of states
10332 in enum) and does NOT match the width of the enum, the signal
10333 is assumed to be a one hot decode. Otherwise, it's a normal
10334 encoded state vector.
10336 The second parameter is the name to store the ASCII code into. For the
10337 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
10338 a signal that is just for simulation, and the magic characters _ascii
10339 tell viewers like Dinotrace to display in ASCII format.
10341 The final optional parameter is a string which will be removed from the
10346 //== State enumeration
10347 parameter [2:0] // synopsys enum state_info
10351 //== State variables
10352 reg [2:0] /* synopsys enum state_info */
10353 state_r; /* synopsys state_vector state_r */
10354 reg [2:0] /* synopsys enum state_info */
10357 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
10359 Typing \\[verilog-auto] will make this into:
10361 ... same front matter ...
10363 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
10364 // Beginning of automatic ASCII enum decoding
10365 reg [39:0] state_ascii_r; // Decode of state_r
10366 always @(state_r) begin
10368 SM_IDLE: state_ascii_r = \"idle \";
10369 SM_SEND: state_ascii_r = \"send \";
10370 SM_WAIT1: state_ascii_r = \"wait1\";
10371 default: state_ascii_r = \"%Erro\";
10374 // End of automatics"
10376 (let* ((params (verilog-read-auto-params 2 3))
10377 (undecode-name (nth 0 params))
10378 (ascii-name (nth 1 params))
10379 (elim-regexp (nth 2 params))
10381 (indent-pt (current-indentation))
10382 (modi (verilog-modi-current))
10383 (moddecls (verilog-modi-get-decls modi))
10385 (sig-list-consts (append (verilog-decls-get-consts moddecls)
10386 (verilog-decls-get-gparams moddecls)))
10387 (sig-list-all (append (verilog-decls-get-regs moddecls)
10388 (verilog-decls-get-outputs moddecls)
10389 (verilog-decls-get-inouts moddecls)
10390 (verilog-decls-get-inputs moddecls)
10391 (verilog-decls-get-wires moddecls)))
10393 (undecode-sig (or (assoc undecode-name sig-list-all)
10394 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
10395 (undecode-enum (or (verilog-sig-enum undecode-sig)
10396 (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name)))
10398 (enum-sigs (verilog-signals-not-in
10399 (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
10400 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum))
10403 (one-hot (and ;; width(enum) != width(sig)
10404 (or (not (verilog-sig-bits (car enum-sigs)))
10405 (not (equal (verilog-sig-width (car enum-sigs))
10406 (verilog-sig-width undecode-sig))))
10407 ;; count(enums) == width(sig)
10408 (equal (number-to-string (length enum-sigs))
10409 (verilog-sig-width undecode-sig))))
10413 ;; Find number of ascii chars needed
10414 (let ((tmp-sigs enum-sigs))
10416 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
10417 ascii-chars (max ascii-chars (length (verilog-enum-ascii
10418 (verilog-sig-name (car tmp-sigs))
10420 tmp-sigs (cdr tmp-sigs))))
10423 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
10424 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
10425 (concat "Decode of " undecode-name) nil nil))))
10426 (verilog-insert-definition decode-sig-list "reg" indent-pt nil)
10427 (verilog-modi-cache-add-regs modi decode-sig-list))
10429 (verilog-insert-indent "always @(" undecode-name ") begin\n")
10430 (setq indent-pt (+ indent-pt verilog-indent-level))
10431 (indent-to indent-pt)
10432 (insert "case ({" undecode-name "})\n")
10433 (setq indent-pt (+ indent-pt verilog-case-indent))
10435 (let ((tmp-sigs enum-sigs)
10436 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n"
10437 (+ (if one-hot 9 1) (max 8 enum-chars))
10438 ascii-name ascii-chars))
10439 (errname (substring "%Error" 0 (min 6 ascii-chars))))
10441 (verilog-insert-indent
10444 (concat (if one-hot "(")
10445 (if one-hot (verilog-sig-width undecode-sig))
10446 ;; We use a shift instead of var[index]
10447 ;; so that a non-one hot value will show as error.
10448 (if one-hot "'b1<<")
10449 (verilog-sig-name (car tmp-sigs))
10450 (if one-hot ")") ":")
10451 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
10453 (setq tmp-sigs (cdr tmp-sigs)))
10454 (verilog-insert-indent (format chrfmt "default:" errname)))
10456 (setq indent-pt (- indent-pt verilog-case-indent))
10457 (verilog-insert-indent "endcase\n")
10458 (setq indent-pt (- indent-pt verilog-indent-level))
10459 (verilog-insert-indent "end\n"
10460 "// End of automatics\n"))))
10462 (defun verilog-auto-templated-rel ()
10463 "Replace Templated relative line numbers with absolute line numbers.
10464 Internal use only. This hacks around the line numbers in AUTOINST Templates
10465 being different from the final output's line numbering."
10466 (let ((templateno 0) (template-line (list 0)))
10467 ;; Find line number each template is on
10468 (goto-char (point-min))
10469 (while (search-forward "AUTO_TEMPLATE" nil t)
10470 (setq templateno (1+ templateno))
10471 (setq template-line
10472 (cons (count-lines (point-min) (point)) template-line)))
10473 (setq template-line (nreverse template-line))
10474 ;; Replace T# L# with absolute line number
10475 (goto-char (point-min))
10476 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
10478 (concat " Templated "
10479 (int-to-string (+ (nth (string-to-number (match-string 1))
10481 (string-to-number (match-string 2)))))
10489 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg
10490 "Expand AUTO statements.
10491 Look for any /*AUTO...*/ commands in the code, as used in
10492 instantiations or argument headers. Update the list of signals
10493 following the /*AUTO...*/ command.
10495 Use \\[verilog-delete-auto] to remove the AUTOs.
10497 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
10499 Use \\[verilog-faq] for a pointer to frequently asked questions.
10501 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
10502 called before and after this function, respectively.
10505 module ModuleName (/*AUTOARG*/)
10510 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
10512 You can also update the AUTOs from the shell using:
10513 emacs --batch <filenames.v> -f verilog-batch-auto
10514 Or fix indentation with:
10515 emacs --batch <filenames.v> -f verilog-batch-indent
10516 Likewise, you can delete or inject AUTOs with:
10517 emacs --batch <filenames.v> -f verilog-batch-delete-auto
10518 emacs --batch <filenames.v> -f verilog-batch-inject-auto
10520 Using \\[describe-function], see also:
10521 `verilog-auto-arg' for AUTOARG module instantiations
10522 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
10523 `verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
10524 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
10525 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
10526 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
10527 `verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
10528 `verilog-auto-inst' for AUTOINST instantiation pins
10529 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
10530 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
10531 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
10532 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
10533 `verilog-auto-reg' for AUTOREG registers
10534 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
10535 `verilog-auto-reset' for AUTORESET flop resets
10536 `verilog-auto-sense' for AUTOSENSE always sensitivity lists
10537 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
10538 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
10539 `verilog-auto-wire' for AUTOWIRE instantiation wires
10541 `verilog-read-defines' for reading `define values
10542 `verilog-read-includes' for reading `includes
10544 If you have bugs with these autos, please file an issue at
10545 URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
10546 Wilson Snyder (wsnyder@wsnyder.org)."
10548 (unless noninteractive (message "Updating AUTOs..."))
10549 (if (fboundp 'dinotrace-unannotate-all)
10550 (dinotrace-unannotate-all))
10551 (let ((oldbuf (if (not (buffer-modified-p))
10553 ;; Before version 20, match-string with font-lock returns a
10554 ;; vector that is not equal to the string. IE if on "input"
10555 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
10556 (fontlocked (when (and (boundp 'font-lock-mode)
10560 ;; Cache directories; we don't write new files, so can't change
10561 (verilog-dir-cache-preserving t))
10564 ;; If we're not in verilog-mode, change syntax table so parsing works right
10565 (unless (eq major-mode `verilog-mode) (verilog-mode))
10566 ;; Allow user to customize
10567 (run-hooks 'verilog-before-auto-hook)
10568 ;; Try to save the user from needing to revert-file to reread file local-variables
10569 (verilog-auto-reeval-locals)
10570 (verilog-read-auto-lisp (point-min) (point-max))
10571 (verilog-getopt-flags)
10572 ;; From here on out, we can cache anything we read from disk
10573 (verilog-preserve-dir-cache
10574 ;; These two may seem obvious to do always, but on large includes it can be way too slow
10575 (when verilog-auto-read-includes
10576 (verilog-read-includes)
10577 (verilog-read-defines nil nil t))
10578 ;; This particular ordering is important
10579 ;; INST: Lower modules correct, no internal dependencies, FIRST
10580 (verilog-preserve-modi-cache
10581 ;; Clear existing autos else we'll be screwed by existing ones
10582 (verilog-delete-auto)
10583 ;; Injection if appropriate
10585 (verilog-inject-inst)
10586 (verilog-inject-sense)
10587 (verilog-inject-arg))
10589 ;; Do user inserts first, so their code can insert AUTOs
10590 ;; We may provide a AUTOINSERTLISPLAST if another cleanup pass is needed
10591 (verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
10592 'verilog-auto-insert-lisp)
10593 ;; Expand instances before need the signals the instances input/output
10594 (verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
10595 (verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
10596 (verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
10597 ;; Doesn't matter when done, but combine it with a common changer
10598 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
10599 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
10600 ;; Must be done before autoin/out as creates a reg
10601 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum)
10603 ;; first in/outs from other files
10604 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
10605 (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP([^)]*)\\*/" 'verilog-auto-inout-comp)
10606 ;; next in/outs which need previous sucked inputs first
10607 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((\"[^\"]*\")\\)\\*/"
10608 '(lambda () (verilog-auto-output t)))
10609 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\*/" 'verilog-auto-output)
10610 (verilog-auto-re-search-do "/\\*AUTOINPUT\\((\"[^\"]*\")\\)\\*/"
10611 '(lambda () (verilog-auto-input t)))
10612 (verilog-auto-re-search-do "/\\*AUTOINPUT\\*/" 'verilog-auto-input)
10613 (verilog-auto-re-search-do "/\\*AUTOINOUT\\((\"[^\"]*\")\\)\\*/"
10614 '(lambda () (verilog-auto-inout t)))
10615 (verilog-auto-re-search-do "/\\*AUTOINOUT\\*/" 'verilog-auto-inout)
10616 ;; Then tie off those in/outs
10617 (verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
10618 ;; Wires/regs must be after inputs/outputs
10619 (verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
10620 (verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
10621 (verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
10622 ;; outputevery needs AUTOOUTPUTs done first
10623 (verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\*/" 'verilog-auto-output-every)
10624 ;; After we've created all new variables
10625 (verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
10626 ;; Must be after all inputs outputs are generated
10627 (verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
10628 ;; Fix line numbers (comments only)
10629 (verilog-auto-templated-rel)))
10631 (run-hooks 'verilog-auto-hook)
10633 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))
10635 ;; If end result is same as when started, clear modified flag
10636 (cond ((and oldbuf (equal oldbuf (buffer-string)))
10637 (set-buffer-modified-p nil)
10638 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
10639 (t (unless noninteractive (message "Updating AUTOs...done")))))
10642 ;; Restore font-lock
10643 (when fontlocked (font-lock-mode t))))))
10647 ;; Skeleton based code insertion
10649 (defvar verilog-template-map
10650 (let ((map (make-sparse-keymap)))
10651 (define-key map "a" 'verilog-sk-always)
10652 (define-key map "b" 'verilog-sk-begin)
10653 (define-key map "c" 'verilog-sk-case)
10654 (define-key map "f" 'verilog-sk-for)
10655 (define-key map "g" 'verilog-sk-generate)
10656 (define-key map "h" 'verilog-sk-header)
10657 (define-key map "i" 'verilog-sk-initial)
10658 (define-key map "j" 'verilog-sk-fork)
10659 (define-key map "m" 'verilog-sk-module)
10660 (define-key map "p" 'verilog-sk-primitive)
10661 (define-key map "r" 'verilog-sk-repeat)
10662 (define-key map "s" 'verilog-sk-specify)
10663 (define-key map "t" 'verilog-sk-task)
10664 (define-key map "w" 'verilog-sk-while)
10665 (define-key map "x" 'verilog-sk-casex)
10666 (define-key map "z" 'verilog-sk-casez)
10667 (define-key map "?" 'verilog-sk-if)
10668 (define-key map ":" 'verilog-sk-else-if)
10669 (define-key map "/" 'verilog-sk-comment)
10670 (define-key map "A" 'verilog-sk-assign)
10671 (define-key map "F" 'verilog-sk-function)
10672 (define-key map "I" 'verilog-sk-input)
10673 (define-key map "O" 'verilog-sk-output)
10674 (define-key map "S" 'verilog-sk-state-machine)
10675 (define-key map "=" 'verilog-sk-inout)
10676 (define-key map "W" 'verilog-sk-wire)
10677 (define-key map "R" 'verilog-sk-reg)
10678 (define-key map "D" 'verilog-sk-define-signal)
10680 "Keymap used in Verilog mode for smart template operations.")
10684 ;; Place the templates into Verilog Mode. They may be inserted under any key.
10685 ;; C-c C-t will be the default. If you use templates a lot, you
10686 ;; may want to consider moving the binding to another key in your .emacs
10689 ;(define-key verilog-mode-map "\C-ct" verilog-template-map)
10690 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
10692 ;;; ---- statement skeletons ------------------------------------------
10694 (define-skeleton verilog-sk-prompt-condition
10695 "Prompt for the loop condition."
10696 "[condition]: " str )
10698 (define-skeleton verilog-sk-prompt-init
10699 "Prompt for the loop init statement."
10700 "[initial statement]: " str )
10702 (define-skeleton verilog-sk-prompt-inc
10703 "Prompt for the loop increment statement."
10704 "[increment statement]: " str )
10706 (define-skeleton verilog-sk-prompt-name
10707 "Prompt for the name of something."
10710 (define-skeleton verilog-sk-prompt-clock
10711 "Prompt for the name of something."
10712 "name and edge of clock(s): " str)
10714 (defvar verilog-sk-reset nil)
10715 (defun verilog-sk-prompt-reset ()
10716 "Prompt for the name of a state machine reset."
10717 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
10720 (define-skeleton verilog-sk-prompt-state-selector
10721 "Prompt for the name of a state machine selector."
10722 "name of selector (eg {a,b,c,d}): " str )
10724 (define-skeleton verilog-sk-prompt-output
10725 "Prompt for the name of something."
10728 (define-skeleton verilog-sk-prompt-msb
10729 "Prompt for least significant bit specification."
10730 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
10732 (define-skeleton verilog-sk-prompt-lsb
10733 "Prompt for least significant bit specification."
10736 (defvar verilog-sk-p nil)
10737 (define-skeleton verilog-sk-prompt-width
10738 "Prompt for a width specification."
10741 (setq verilog-sk-p (point))
10742 (verilog-sk-prompt-msb)
10743 (if (> (point) verilog-sk-p) "] " " ")))
10745 (defun verilog-sk-header ()
10746 "Insert a descriptive header at the top of the file.
10747 See also `verilog-header' for an alternative format."
10750 (goto-char (point-min))
10751 (verilog-sk-header-tmpl)))
10753 (define-skeleton verilog-sk-header-tmpl
10754 "Insert a comment block containing the module title, author, etc."
10756 "// -*- Mode: Verilog -*-"
10757 "\n// Filename : " (buffer-name)
10758 "\n// Description : " str
10759 "\n// Author : " (user-full-name)
10760 "\n// Created On : " (current-time-string)
10761 "\n// Last Modified By: " (user-full-name)
10762 "\n// Last Modified On: " (current-time-string)
10763 "\n// Update Count : 0"
10764 "\n// Status : Unknown, Use with caution!"
10767 (define-skeleton verilog-sk-module
10768 "Insert a module definition."
10770 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
10772 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
10774 (define-skeleton verilog-sk-primitive
10775 "Insert a task definition."
10777 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
10779 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
10781 (define-skeleton verilog-sk-task
10782 "Insert a task definition."
10784 > "task " '(verilog-sk-prompt-name) & ?; \n
10788 > (- verilog-indent-level-behavioral) "end" \n
10789 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
10791 (define-skeleton verilog-sk-function
10792 "Insert a function definition."
10794 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
10798 > (- verilog-indent-level-behavioral) "end" \n
10799 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
10801 (define-skeleton verilog-sk-always
10802 "Insert always block. Uses the minibuffer to prompt
10803 for sensitivity list."
10805 > "always @ ( /*AUTOSENSE*/ ) begin\n"
10807 > (- verilog-indent-level-behavioral) "end" \n >
10810 (define-skeleton verilog-sk-initial
10811 "Insert an initial block."
10813 > "initial begin\n"
10815 > (- verilog-indent-level-behavioral) "end" \n > )
10817 (define-skeleton verilog-sk-specify
10818 "Insert specify block. "
10822 > (- verilog-indent-level-behavioral) "endspecify" \n > )
10824 (define-skeleton verilog-sk-generate
10825 "Insert generate block. "
10829 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
10831 (define-skeleton verilog-sk-begin
10832 "Insert begin end block. Uses the minibuffer to prompt for name."
10834 > "begin" '(verilog-sk-prompt-name) \n
10836 > (- verilog-indent-level-behavioral) "end"
10839 (define-skeleton verilog-sk-fork
10840 "Insert a fork join block."
10845 > (- verilog-indent-level-behavioral) "end" \n
10848 > (- verilog-indent-level-behavioral) "end" \n
10849 > (- verilog-indent-level-behavioral) "join" \n
10853 (define-skeleton verilog-sk-case
10854 "Build skeleton case statement, prompting for the selector expression,
10855 and the case items."
10856 "[selector expression]: "
10857 > "case (" str ") " \n
10858 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
10859 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
10861 (define-skeleton verilog-sk-casex
10862 "Build skeleton casex statement, prompting for the selector expression,
10863 and the case items."
10864 "[selector expression]: "
10865 > "casex (" str ") " \n
10866 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
10867 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
10869 (define-skeleton verilog-sk-casez
10870 "Build skeleton casez statement, prompting for the selector expression,
10871 and the case items."
10872 "[selector expression]: "
10873 > "casez (" str ") " \n
10874 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
10875 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
10877 (define-skeleton verilog-sk-if
10878 "Insert a skeleton if statement."
10879 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
10881 > (- verilog-indent-level-behavioral) "end " \n )
10883 (define-skeleton verilog-sk-else-if
10884 "Insert a skeleton else if statement."
10885 > (verilog-indent-line) "else if ("
10886 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
10888 > "end" (progn (electric-verilog-terminate-line) nil))
10890 (define-skeleton verilog-sk-datadef
10891 "Common routine to get data definition."
10893 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
10895 (define-skeleton verilog-sk-input
10896 "Insert an input definition."
10898 > "input [" '(verilog-sk-datadef))
10900 (define-skeleton verilog-sk-output
10901 "Insert an output definition."
10903 > "output [" '(verilog-sk-datadef))
10905 (define-skeleton verilog-sk-inout
10906 "Insert an inout definition."
10908 > "inout [" '(verilog-sk-datadef))
10910 (defvar verilog-sk-signal nil)
10911 (define-skeleton verilog-sk-def-reg
10912 "Insert a reg definition."
10914 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) )
10916 (defun verilog-sk-define-signal ()
10917 "Insert a definition of signal under point at top of module."
10919 (let* ((sig-re "[a-zA-Z0-9_]*")
10920 (v1 (buffer-substring
10922 (skip-chars-backward sig-re)
10925 (skip-chars-forward sig-re)
10927 (if (not (member v1 verilog-keywords))
10929 (setq verilog-sk-signal v1)
10930 (verilog-beg-of-defun)
10931 (verilog-end-of-statement)
10932 (verilog-forward-syntactic-ws)
10933 (verilog-sk-def-reg)
10934 (message "signal at point is %s" v1))
10935 (message "object at point (%s) is a keyword" v1))))
10937 (define-skeleton verilog-sk-wire
10938 "Insert a wire definition."
10940 > "wire [" '(verilog-sk-datadef))
10942 (define-skeleton verilog-sk-reg
10943 "Insert a reg definition."
10945 > "reg [" '(verilog-sk-datadef))
10947 (define-skeleton verilog-sk-assign
10948 "Insert a skeleton assign statement."
10950 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
10952 (define-skeleton verilog-sk-while
10953 "Insert a skeleton while loop statement."
10955 > "while (" '(verilog-sk-prompt-condition) ") begin" \n
10957 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10959 (define-skeleton verilog-sk-repeat
10960 "Insert a skeleton repeat loop statement."
10962 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
10964 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10966 (define-skeleton verilog-sk-for
10967 "Insert a skeleton while loop statement."
10970 '(verilog-sk-prompt-init) "; "
10971 '(verilog-sk-prompt-condition) "; "
10972 '(verilog-sk-prompt-inc)
10975 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10977 (define-skeleton verilog-sk-comment
10978 "Inserts three comment lines, making a display comment."
10984 (define-skeleton verilog-sk-state-machine
10985 "Insert a state machine definition."
10986 "Name of state variable: "
10987 '(setq input "state")
10988 > "// State registers for " str | -23 \n
10989 '(setq verilog-sk-state str)
10990 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
10993 > "// State FF for " verilog-sk-state \n
10994 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
10995 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
10996 > verilog-sk-state " = next_" verilog-sk-state ?; \n
10997 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
10999 > "// Next State Logic for " verilog-sk-state \n
11000 > "always @ ( /*AUTOSENSE*/ ) begin\n"
11001 > "case (" '(verilog-sk-prompt-state-selector) ") " \n
11002 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
11003 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
11004 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
11008 ;; Include file loading with mouse/return event
11010 ;; idea & first impl.: M. Rouat (eldo-mode.el)
11011 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
11013 (if (featurep 'xemacs)
11014 (require 'overlay))
11016 (defconst verilog-include-file-regexp
11017 "^`include\\s-+\"\\([^\n\"]*\\)\""
11018 "Regexp that matches the include file.")
11020 (defvar verilog-mode-mouse-map
11021 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
11022 (set-keymap-parent map verilog-mode-map)
11023 ;; mouse button bindings
11024 (define-key map "\r" 'verilog-load-file-at-point)
11025 (if (featurep 'xemacs)
11026 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
11027 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
11028 (if (featurep 'xemacs)
11029 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
11030 (define-key map [S-mouse-2] 'mouse-yank-at-click))
11032 "Map containing mouse bindings for `verilog-mode'.")
11035 (defun verilog-colorize-include-files (beg end old-len)
11036 "This function colorizes included files when the mouse passes over them.
11037 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
11042 (setq end-point (verilog-get-end-of-line))
11044 (beginning-of-line) ; scan entire line !
11045 ;; delete overlays existing on this line
11046 (let ((overlays (overlays-in (point) end-point)))
11049 (overlay-get (car overlays) 'detachable)
11050 (overlay-get (car overlays) 'verilog-include-file))
11051 (delete-overlay (car overlays)))
11052 (setq overlays (cdr overlays)))) ; let
11053 ;; make new ones, could reuse deleted one ?
11054 (while (search-forward-regexp verilog-include-file-regexp end-point t)
11056 (goto-char (match-beginning 1))
11057 (setq ov (make-overlay (match-beginning 1) (match-end 1)))
11058 (overlay-put ov 'start-closed 't)
11059 (overlay-put ov 'end-closed 't)
11060 (overlay-put ov 'evaporate 't)
11061 (overlay-put ov 'verilog-include-file 't)
11062 (overlay-put ov 'mouse-face 'highlight)
11063 (overlay-put ov 'local-map verilog-mode-mouse-map)))))))
11066 (defun verilog-colorize-include-files-buffer ()
11067 "Colorize an include file."
11070 (let ((overlays (overlays-in (point-min) (point-max))))
11073 (overlay-get (car overlays) 'detachable)
11074 (overlay-get (car overlays) 'verilog-include-file))
11075 (delete-overlay (car overlays)))
11076 (setq overlays (cdr overlays)))) ; let
11078 (verilog-colorize-include-files (point-min) (point-max) nil))
11080 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
11081 ;; so define this function to do more or less the same as ffap-at-mouse
11082 ;; but first resolve filename...
11083 (defun verilog-load-file-at-mouse (event)
11084 "Load file under button 2 click's EVENT.
11085 Files are checked based on `verilog-library-directories'."
11087 (save-excursion ;; implement a Verilog specific ffap-at-mouse
11088 (mouse-set-point event)
11089 (beginning-of-line)
11090 (if (looking-at verilog-include-file-regexp)
11091 (if (and (car (verilog-library-filenames
11092 (match-string 1) (buffer-file-name)))
11093 (file-readable-p (car (verilog-library-filenames
11094 (match-string 1) (buffer-file-name)))))
11095 (find-file (car (verilog-library-filenames
11096 (match-string 1) (buffer-file-name))))
11099 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
11100 (match-string 1)))))))
11102 ;; ffap isn't useable for Verilog mode. It uses library paths.
11103 ;; so define this function to do more or less the same as ffap
11104 ;; but first resolve filename...
11105 (defun verilog-load-file-at-point ()
11106 "Load file under point.
11107 Files are checked based on `verilog-library-directories'."
11109 (save-excursion ;; implement a Verilog specific ffap
11110 (beginning-of-line)
11111 (if (looking-at verilog-include-file-regexp)
11113 (car (verilog-library-filenames
11114 (match-string 1) (buffer-file-name)))
11115 (file-readable-p (car (verilog-library-filenames
11116 (match-string 1) (buffer-file-name)))))
11117 (find-file (car (verilog-library-filenames
11118 (match-string 1) (buffer-file-name))))))))
11125 (defun verilog-faq ()
11126 "Tell the user their current version, and where to get the FAQ etc."
11128 (with-output-to-temp-buffer "*verilog-mode help*"
11129 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
11131 (princ "For new releases, see http://www.verilog.com\n")
11133 (princ "For frequently asked questions, see http://www.veripool.org/verilog-mode-faq.html\n")
11135 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
11138 (autoload 'reporter-submit-bug-report "reporter")
11139 (defvar reporter-prompt-for-summary-p)
11141 (defun verilog-submit-bug-report ()
11142 "Submit via mail a bug report on verilog-mode.el."
11144 (let ((reporter-prompt-for-summary-p t))
11145 (reporter-submit-bug-report
11147 (concat "verilog-mode v" verilog-mode-version)
11149 verilog-align-ifelse
11150 verilog-auto-endcomments
11152 verilog-auto-indent-on-newline
11153 verilog-auto-inst-vector
11154 verilog-auto-inst-template-numbers
11155 verilog-auto-lineup
11156 verilog-auto-newline
11157 verilog-auto-save-policy
11158 verilog-auto-sense-defines-constant
11159 verilog-auto-sense-include-inputs
11160 verilog-before-auto-hook
11161 verilog-case-indent
11162 verilog-cexp-indent
11165 verilog-highlight-translate-off
11166 verilog-indent-begin-after-if
11167 verilog-indent-declaration-macros
11168 verilog-indent-level
11169 verilog-indent-level-behavioral
11170 verilog-indent-level-declaration
11171 verilog-indent-level-directive
11172 verilog-indent-level-module
11173 verilog-indent-lists
11174 verilog-library-flags
11175 verilog-library-directories
11176 verilog-library-extensions
11177 verilog-library-files
11179 verilog-minimum-comment-distance
11182 verilog-tab-always-indent
11183 verilog-tab-to-comment
11188 I want to report a bug. I've read the `Bugs' section of `Info' on
11189 Emacs, so I know how to make a clear and unambiguous report. To get
11190 to that Info section, I typed
11192 M-x info RET m " invocation-name " RET m bugs RET
11194 Before I go further, I want to say that Verilog mode has changed my life.
11195 I save so much time, my files are colored nicely, my co workers respect
11196 my coding ability... until now. I'd really appreciate anything you
11197 could do to help me out with this minor deficiency in the product.
11199 If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson
11200 Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.org.
11201 You may also want to look at the Verilog-Mode FAQ, see
11202 http://www.veripool.org/verilog-mode-faq.html.
11204 To reproduce the bug, start a fresh Emacs via " invocation-name "
11205 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
11206 the code included below.
11208 Given those lines, I expected [[Fill in here]] to happen;
11209 but instead, [[Fill in here]] happens!.
11211 == The code: =="))))
11213 (provide 'verilog-mode)
11215 ;; Local Variables:
11216 ;; checkdoc-permit-comma-termination-flag:t
11217 ;; checkdoc-force-docstrings-flag:nil
11220 ;; arch-tag: 87923725-57b3-41b5-9494-be21118c6a6f
11221 ;;; verilog-mode.el ends here