2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/i386/apic/Attic/mpapic.c,v 1.17 2005/11/21 18:02:38 dillon Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <machine/globaldata.h>
32 #include <machine/smp.h>
33 #include <arch/apic/mpapic.h>
34 #include <machine/segments.h>
35 #include <sys/thread2.h>
37 #include <i386/isa/intr_machdep.h> /* Xspuriousint() */
39 /* EISA Edge/Level trigger control registers */
40 #define ELCR0 0x4d0 /* eisa irq 0-7 */
41 #define ELCR1 0x4d1 /* eisa irq 8-15 */
44 * pointers to pmapped apic hardware.
47 volatile ioapic_t
**ioapic
;
50 * Enable APIC, configure interrupts.
58 * setup LVT1 as ExtINT on the BSP. This is theoretically an
59 * aggregate interrupt input from the 8259. The INTA cycle
60 * will be routed to the external controller (the 8259) which
61 * is expected to supply the vector.
63 * Must be setup edge triggered, active high.
65 * Disable LVT1 on the APs. It doesn't matter what delivery
66 * mode we use because we leave it masked.
68 temp
= lapic
.lvt_lint0
;
69 temp
&= ~(APIC_LVT_MASKED
| APIC_LVT_TRIG_MASK
|
70 APIC_LVT_POLARITY_MASK
| APIC_LVT_DM_MASK
);
71 if (mycpu
->gd_cpuid
== 0)
72 temp
|= APIC_LVT_DM_EXTINT
;
74 temp
|= APIC_LVT_DM_FIXED
| APIC_LVT_MASKED
;
75 lapic
.lvt_lint0
= temp
;
78 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
80 temp
= lapic
.lvt_lint1
;
81 temp
&= ~(APIC_LVT_MASKED
| APIC_LVT_TRIG_MASK
|
82 APIC_LVT_POLARITY_MASK
| APIC_LVT_DM_MASK
);
83 temp
|= APIC_LVT_MASKED
| APIC_LVT_DM_NMI
;
84 lapic
.lvt_lint1
= temp
;
87 * Mask the apic error interrupt, apic performance counter
88 * interrupt, and the apic timer interrupt.
90 lapic
.lvt_error
= lapic
.lvt_error
| APIC_LVT_MASKED
;
91 lapic
.lvt_pcint
= lapic
.lvt_pcint
| APIC_LVT_MASKED
;
92 lapic
.lvt_timer
= lapic
.lvt_timer
| APIC_LVT_MASKED
;
95 * Set the Task Priority Register as needed. At the moment allow
96 * interrupts on all cpus (the APs will remain CLId until they are
97 * ready to deal). We could disable all but IPIs by setting
98 * temp |= TPR_IPI_ONLY for cpu != 0.
101 temp
&= ~APIC_TPR_PRIO
; /* clear priority field */
104 * If we are NOT running the IO APICs, the LAPIC will only be used
105 * for IPIs. Set the TPR to prevent any unintentional interrupts.
107 temp
|= TPR_IPI_ONLY
;
113 * enable the local APIC
116 temp
|= APIC_SVR_ENABLE
; /* enable the APIC */
117 temp
&= ~APIC_SVR_FOCUS_DISABLE
; /* enable lopri focus processor */
120 * Set the spurious interrupt vector. The low 4 bits of the vector
123 if ((XSPURIOUSINT_OFFSET
& 0x0F) != 0x0F)
124 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET
);
125 temp
&= ~APIC_SVR_VECTOR
;
126 temp
|= XSPURIOUSINT_OFFSET
;
131 apic_dump("apic_initialize()");
136 * dump contents of local APIC registers
141 printf("SMP: CPU%d %s:\n", mycpu
->gd_cpuid
, str
);
142 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
143 lapic
.lvt_lint0
, lapic
.lvt_lint1
, lapic
.tpr
, lapic
.svr
);
153 #define IOAPIC_ISA_INTS 16
154 #define REDIRCNT_IOAPIC(A) \
155 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
157 static int trigger (int apic
, int pin
, u_int32_t
* flags
);
158 static void polarity (int apic
, int pin
, u_int32_t
* flags
, int level
);
160 #define DEFAULT_FLAGS \
166 #define DEFAULT_ISA_FLAGS \
175 io_apic_set_id(int apic
, int id
)
179 ux
= io_apic_read(apic
, IOAPIC_ID
); /* get current contents */
180 if (((ux
& APIC_ID_MASK
) >> 24) != id
) {
181 printf("Changing APIC ID for IO APIC #%d"
182 " from %d to %d on chip\n",
183 apic
, ((ux
& APIC_ID_MASK
) >> 24), id
);
184 ux
&= ~APIC_ID_MASK
; /* clear the ID field */
186 io_apic_write(apic
, IOAPIC_ID
, ux
); /* write new value */
187 ux
= io_apic_read(apic
, IOAPIC_ID
); /* re-read && test */
188 if (((ux
& APIC_ID_MASK
) >> 24) != id
)
189 panic("can't control IO APIC #%d ID, reg: 0x%08x",
196 io_apic_get_id(int apic
)
198 return (io_apic_read(apic
, IOAPIC_ID
) & APIC_ID_MASK
) >> 24;
207 extern int apic_pin_trigger
; /* 'opaque' */
210 io_apic_setup_intpin(int apic
, int pin
)
212 int bus
, bustype
, irq
;
213 u_char select
; /* the select register is 8 bits */
214 u_int32_t flags
; /* the window register is 32 bits */
215 u_int32_t target
; /* the window register is 32 bits */
216 u_int32_t vector
; /* the window register is 32 bits */
219 select
= pin
* 2 + IOAPIC_REDTBL0
; /* register */
222 * Always clear an IO APIC pin before [re]programming it. This is
223 * particularly important if the pin is set up for a level interrupt
224 * as the IOART_REM_IRR bit might be set. When we reprogram the
225 * vector any EOI from pending ints on this pin could be lost and
226 * IRR might never get reset.
228 * To fix this problem, clear the vector and make sure it is
229 * programmed as an edge interrupt. This should theoretically
230 * clear IRR so we can later, safely program it as a level
235 flags
= io_apic_read(apic
, select
) & IOART_RESV
;
236 flags
|= IOART_INTMSET
| IOART_TRGREDG
| IOART_INTAHI
;
237 flags
|= IOART_DESTPHY
| IOART_DELFIXED
;
239 target
= io_apic_read(apic
, select
+ 1) & IOART_HI_DEST_RESV
;
240 target
|= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
244 io_apic_write(apic
, select
, flags
| vector
);
245 io_apic_write(apic
, select
+ 1, target
);
250 * We only deal with vectored interrupts here. ? documentation is
251 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
254 * This test also catches unconfigured pins.
256 if (apic_int_type(apic
, pin
) != 0)
260 * Leave the pin unprogrammed if it does not correspond to
263 irq
= apic_irq(apic
, pin
);
267 /* determine the bus type for this pin */
268 bus
= apic_src_bus_id(apic
, pin
);
271 bustype
= apic_bus_type(bus
);
273 if ((bustype
== ISA
) &&
274 (pin
< IOAPIC_ISA_INTS
) &&
276 (apic_polarity(apic
, pin
) == 0x1) &&
277 (apic_trigger(apic
, pin
) == 0x3)) {
279 * A broken BIOS might describe some ISA
280 * interrupts as active-high level-triggered.
281 * Use default ISA flags for those interrupts.
283 flags
= DEFAULT_ISA_FLAGS
;
286 * Program polarity and trigger mode according to
289 flags
= DEFAULT_FLAGS
;
290 level
= trigger(apic
, pin
, &flags
);
292 apic_pin_trigger
|= (1 << irq
);
293 polarity(apic
, pin
, &flags
, level
);
297 printf("IOAPIC #%d intpin %d -> irq %d\n",
302 * Program the appropriate registers. This routing may be
303 * overridden when an interrupt handler for a device is
304 * actually added (see register_int(), which calls through
305 * the MACHINTR ABI to set up an interrupt handler/vector).
307 * The order in which we must program the two registers for
308 * safety is unclear! XXX
312 vector
= IDT_OFFSET
+ irq
; /* IDT vec */
313 target
= io_apic_read(apic
, select
+ 1) & IOART_HI_DEST_RESV
;
314 target
|= IOART_HI_DEST_BROADCAST
;
315 flags
|= io_apic_read(apic
, select
) & IOART_RESV
;
316 io_apic_write(apic
, select
, flags
| vector
);
317 io_apic_write(apic
, select
+ 1, target
);
323 io_apic_setup(int apic
)
329 apic_pin_trigger
= 0; /* default to edge-triggered */
331 maxpin
= REDIRCNT_IOAPIC(apic
); /* pins in APIC */
332 printf("Programming %d pins in IOAPIC #%d\n", maxpin
, apic
);
334 for (pin
= 0; pin
< maxpin
; ++pin
) {
335 io_apic_setup_intpin(apic
, pin
);
338 if (apic_int_type(apic
, pin
) >= 0) {
339 printf("Warning: IOAPIC #%d pin %d does not exist,"
340 " cannot program!\n", apic
, pin
);
345 /* return GOOD status */
348 #undef DEFAULT_ISA_FLAGS
352 #define DEFAULT_EXTINT_FLAGS \
361 * Setup the source of External INTerrupts.
364 ext_int_setup(int apic
, int intr
)
366 u_char select
; /* the select register is 8 bits */
367 u_int32_t flags
; /* the window register is 32 bits */
368 u_int32_t target
; /* the window register is 32 bits */
369 u_int32_t vector
; /* the window register is 32 bits */
371 if (apic_int_type(apic
, intr
) != 3)
374 target
= IOART_HI_DEST_BROADCAST
;
375 select
= IOAPIC_REDTBL0
+ (2 * intr
);
376 vector
= IDT_OFFSET
+ intr
;
377 flags
= DEFAULT_EXTINT_FLAGS
;
379 io_apic_write(apic
, select
, flags
| vector
);
380 io_apic_write(apic
, select
+ 1, target
);
384 #undef DEFAULT_EXTINT_FLAGS
388 * Set the trigger level for an IO APIC pin.
391 trigger(int apic
, int pin
, u_int32_t
* flags
)
396 static int intcontrol
= -1;
398 switch (apic_trigger(apic
, pin
)) {
404 *flags
&= ~IOART_TRGRLVL
; /* *flags |= IOART_TRGREDG */
408 *flags
|= IOART_TRGRLVL
;
416 if ((id
= apic_src_bus_id(apic
, pin
)) == -1)
419 switch (apic_bus_type(id
)) {
421 *flags
&= ~IOART_TRGRLVL
; /* *flags |= IOART_TRGREDG; */
425 eirq
= apic_src_bus_irq(apic
, pin
);
427 if (eirq
< 0 || eirq
> 15) {
428 printf("EISA IRQ %d?!?!\n", eirq
);
432 if (intcontrol
== -1) {
433 intcontrol
= inb(ELCR1
) << 8;
434 intcontrol
|= inb(ELCR0
);
435 printf("EISA INTCONTROL = %08x\n", intcontrol
);
438 /* Use ELCR settings to determine level or edge mode */
439 level
= (intcontrol
>> eirq
) & 1;
442 * Note that on older Neptune chipset based systems, any
443 * pci interrupts often show up here and in the ELCR as well
444 * as level sensitive interrupts attributed to the EISA bus.
448 *flags
|= IOART_TRGRLVL
;
450 *flags
&= ~IOART_TRGRLVL
;
455 *flags
|= IOART_TRGRLVL
;
464 panic("bad APIC IO INT flags");
469 * Set the polarity value for an IO APIC pin.
472 polarity(int apic
, int pin
, u_int32_t
* flags
, int level
)
476 switch (apic_polarity(apic
, pin
)) {
482 *flags
&= ~IOART_INTALO
; /* *flags |= IOART_INTAHI */
486 *flags
|= IOART_INTALO
;
494 if ((id
= apic_src_bus_id(apic
, pin
)) == -1)
497 switch (apic_bus_type(id
)) {
499 *flags
&= ~IOART_INTALO
; /* *flags |= IOART_INTAHI */
503 /* polarity converter always gives active high */
504 *flags
&= ~IOART_INTALO
;
508 *flags
|= IOART_INTALO
;
517 panic("bad APIC IO INT flags");
522 * Print contents of apic_imen.
524 extern u_int apic_imen
; /* keep apic_imen 'opaque' */
530 printf("SMP: enabled INTs: ");
531 for (x
= 0; x
< 24; ++x
)
532 if ((apic_imen
& (1 << x
)) == 0)
534 printf("apic_imen: 0x%08x\n", apic_imen
);
539 * Inter Processor Interrupt functions.
545 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
547 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
548 * vector is any valid SYSTEM INT vector
549 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
551 * A backlog of requests can create a deadlock between cpus. To avoid this
552 * we have to be able to accept IPIs at the same time we are trying to send
553 * them. The critical section prevents us from attempting to send additional
554 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
555 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
556 * to occur but fortunately it does not happen too often.
559 apic_ipi(int dest_type
, int vector
, int delivery_mode
)
564 if ((lapic
.icr_lo
& APIC_DELSTAT_MASK
) != 0) {
565 unsigned int eflags
= read_eflags();
567 while ((lapic
.icr_lo
& APIC_DELSTAT_MASK
) != 0) {
570 write_eflags(eflags
);
573 icr_lo
= (lapic
.icr_lo
& APIC_ICRLO_RESV_MASK
) | dest_type
|
574 delivery_mode
| vector
;
575 lapic
.icr_lo
= icr_lo
;
581 single_apic_ipi(int cpu
, int vector
, int delivery_mode
)
587 if ((lapic
.icr_lo
& APIC_DELSTAT_MASK
) != 0) {
588 unsigned int eflags
= read_eflags();
590 while ((lapic
.icr_lo
& APIC_DELSTAT_MASK
) != 0) {
593 write_eflags(eflags
);
595 icr_hi
= lapic
.icr_hi
& ~APIC_ID_MASK
;
596 icr_hi
|= (CPU_TO_ID(cpu
) << 24);
597 lapic
.icr_hi
= icr_hi
;
600 icr_lo
= (lapic
.icr_lo
& APIC_ICRLO_RESV_MASK
)
601 | APIC_DEST_DESTFLD
| delivery_mode
| vector
;
604 lapic
.icr_lo
= icr_lo
;
611 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
613 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
614 * to the target, and the scheduler does not 'poll' for IPI messages.
617 single_apic_ipi_passive(int cpu
, int vector
, int delivery_mode
)
623 if ((lapic
.icr_lo
& APIC_DELSTAT_MASK
) != 0) {
627 icr_hi
= lapic
.icr_hi
& ~APIC_ID_MASK
;
628 icr_hi
|= (CPU_TO_ID(cpu
) << 24);
629 lapic
.icr_hi
= icr_hi
;
632 icr_lo
= (lapic
.icr_lo
& APIC_RESV2_MASK
)
633 | APIC_DEST_DESTFLD
| delivery_mode
| vector
;
636 lapic
.icr_lo
= icr_lo
;
644 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
646 * target is a bitmask of destination cpus. Vector is any
647 * valid system INT vector. Delivery mode may be either
648 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
651 selected_apic_ipi(u_int target
, int vector
, int delivery_mode
)
655 int n
= bsfl(target
);
657 single_apic_ipi(n
, vector
, delivery_mode
);
663 * Timer code, in development...
664 * - suggested by rgrimes@gndrsh.aac.dev.com
667 /** XXX FIXME: temp hack till we can determin bus clock */
669 #define BUS_CLOCK 66000000
670 #define bus_clock() 66000000
674 int acquire_apic_timer (void);
675 int release_apic_timer (void);
678 * Acquire the APIC timer for exclusive use.
681 acquire_apic_timer(void)
686 /** XXX FIXME: make this really do something */
687 panic("APIC timer in use when attempting to aquire");
693 * Return the APIC timer.
696 release_apic_timer(void)
701 /** XXX FIXME: make this really do something */
702 panic("APIC timer was already released");
709 * Load a 'downcount time' in uSeconds.
712 set_apic_timer(int value
)
715 long ticks_per_microsec
;
718 * Calculate divisor and count from value:
720 * timeBase == CPU bus clock divisor == [1,2,4,8,16,32,64,128]
721 * value == time in uS
723 lapic
.dcr_timer
= APIC_TDCR_1
;
724 ticks_per_microsec
= bus_clock() / 1000000;
726 /* configure timer as one-shot */
727 lvtt
= lapic
.lvt_timer
;
728 lvtt
&= ~(APIC_LVTT_VECTOR
| APIC_LVTT_DS
);
729 lvtt
&= ~(APIC_LVTT_PERIODIC
);
730 lvtt
|= APIC_LVTT_MASKED
; /* no INT, one-shot */
731 lapic
.lvt_timer
= lvtt
;
734 lapic
.icr_timer
= value
* ticks_per_microsec
;
739 * Read remaining time in timer.
742 read_apic_timer(void)
745 /** XXX FIXME: we need to return the actual remaining time,
746 * for now we just return the remaining count.
749 return lapic
.ccr_timer
;
755 * Spin-style delay, set delay time in uS, spin till it drains.
760 set_apic_timer(count
);
761 while (read_apic_timer())