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e1000 - Literally import e1000 driver from FreeBSD
[dragonfly.git] / sys / dev / netif / e1000 / e1000_80003es2lan.c
blobdb32f8cbe363e404f0a10880739df9f3aef12c57
1 /******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 /*
36 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
38 */
39
40 #include "e1000_api.h"
41
42 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
43 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
44 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
45 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
46 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
47 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
48 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
49 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
50 u32 offset,
51 u16 *data);
52 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
53 u32 offset,
54 u16 data);
55 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
58 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
59 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
60 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
61 u16 *duplex);
62 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
63 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
64 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
65 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
66 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
67 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
68 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
69 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
70 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
71 u16 *data);
72 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
73 u16 data);
74 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
75 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
76 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
77 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
78 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
79
80 /*
81 * A table for the GG82563 cable length where the range is defined
82 * with a lower bound at "index" and the upper bound at
83 * "index + 5".
84 */
85 static const u16 e1000_gg82563_cable_length_table[] =
86 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
87 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
88 (sizeof(e1000_gg82563_cable_length_table) / \
89 sizeof(e1000_gg82563_cable_length_table[0]))
90
91 /**
92 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
93 * @hw: pointer to the HW structure
94 **/
95 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
96 {
97 struct e1000_phy_info *phy = &hw->phy;
98 s32 ret_val = E1000_SUCCESS;
99
100 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
101
102 if (hw->phy.media_type != e1000_media_type_copper) {
103 phy->type = e1000_phy_none;
104 goto out;
105 } else {
106 phy->ops.power_up = e1000_power_up_phy_copper;
107 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
108 }
109
110 phy->addr = 1;
111 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
112 phy->reset_delay_us = 100;
113 phy->type = e1000_phy_gg82563;
114
115 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
116 phy->ops.check_polarity = e1000_check_polarity_m88;
117 phy->ops.check_reset_block = e1000_check_reset_block_generic;
118 phy->ops.commit = e1000_phy_sw_reset_generic;
119 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
120 phy->ops.get_info = e1000_get_phy_info_m88;
121 phy->ops.release = e1000_release_phy_80003es2lan;
122 phy->ops.reset = e1000_phy_hw_reset_generic;
123 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
124
125 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
126 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
127 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
128 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
129
130 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
131
132 /* This can only be done after all function pointers are setup. */
133 ret_val = e1000_get_phy_id(hw);
134
135 /* Verify phy id */
136 if (phy->id != GG82563_E_PHY_ID) {
137 ret_val = -E1000_ERR_PHY;
138 goto out;
139 }
140
141 out:
142 return ret_val;
143 }
144
145 /**
146 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
147 * @hw: pointer to the HW structure
148 **/
149 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
150 {
151 struct e1000_nvm_info *nvm = &hw->nvm;
152 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
153 u16 size;
154
155 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
156
157 nvm->opcode_bits = 8;
158 nvm->delay_usec = 1;
159 switch (nvm->override) {
160 case e1000_nvm_override_spi_large:
161 nvm->page_size = 32;
162 nvm->address_bits = 16;
163 break;
164 case e1000_nvm_override_spi_small:
165 nvm->page_size = 8;
166 nvm->address_bits = 8;
167 break;
168 default:
169 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
170 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
171 break;
172 }
173
174 nvm->type = e1000_nvm_eeprom_spi;
175
176 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
177 E1000_EECD_SIZE_EX_SHIFT);
178
179 /*
180 * Added to a constant, "size" becomes the left-shift value
181 * for setting word_size.
182 */
183 size += NVM_WORD_SIZE_BASE_SHIFT;
184
185 /* EEPROM access above 16k is unsupported */
186 if (size > 14)
187 size = 14;
188 nvm->word_size = 1 << size;
189
190 /* Function Pointers */
191 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
192 nvm->ops.read = e1000_read_nvm_eerd;
193 nvm->ops.release = e1000_release_nvm_80003es2lan;
194 nvm->ops.update = e1000_update_nvm_checksum_generic;
195 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
196 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
197 nvm->ops.write = e1000_write_nvm_80003es2lan;
198
199 return E1000_SUCCESS;
200 }
201
202 /**
203 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
204 * @hw: pointer to the HW structure
205 **/
206 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
207 {
208 struct e1000_mac_info *mac = &hw->mac;
209
210 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
211
212 /* Set media type and media-dependent function pointers */
213 switch (hw->device_id) {
214 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
215 hw->phy.media_type = e1000_media_type_internal_serdes;
216 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
217 mac->ops.setup_physical_interface =
218 e1000_setup_fiber_serdes_link_generic;
219 break;
220 default:
221 hw->phy.media_type = e1000_media_type_copper;
222 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
223 mac->ops.setup_physical_interface =
224 e1000_setup_copper_link_80003es2lan;
225 break;
226 }
227
228 /* Set mta register count */
229 mac->mta_reg_count = 128;
230 /* Set rar entry count */
231 mac->rar_entry_count = E1000_RAR_ENTRIES;
232 /* Set if part includes ASF firmware */
233 mac->asf_firmware_present = TRUE;
234 /* Set if manageability features are enabled. */
235 mac->arc_subsystem_valid =
236 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
237 ? TRUE : FALSE;
238 /* Adaptive IFS not supported */
239 mac->adaptive_ifs = FALSE;
240
241 /* Function pointers */
242
243 /* bus type/speed/width */
244 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
245 /* reset */
246 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
247 /* hw initialization */
248 mac->ops.init_hw = e1000_init_hw_80003es2lan;
249 /* link setup */
250 mac->ops.setup_link = e1000_setup_link_generic;
251 /* check management mode */
252 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
253 /* multicast address update */
254 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
255 /* writing VFTA */
256 mac->ops.write_vfta = e1000_write_vfta_generic;
257 /* clearing VFTA */
258 mac->ops.clear_vfta = e1000_clear_vfta_generic;
259 /* read mac address */
260 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
261 /* ID LED init */
262 mac->ops.id_led_init = e1000_id_led_init_generic;
263 /* blink LED */
264 mac->ops.blink_led = e1000_blink_led_generic;
265 /* setup LED */
266 mac->ops.setup_led = e1000_setup_led_generic;
267 /* cleanup LED */
268 mac->ops.cleanup_led = e1000_cleanup_led_generic;
269 /* turn on/off LED */
270 mac->ops.led_on = e1000_led_on_generic;
271 mac->ops.led_off = e1000_led_off_generic;
272 /* clear hardware counters */
273 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
274 /* link info */
275 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
276
277 /* set lan id for port to determine which phy lock to use */
278 hw->mac.ops.set_lan_id(hw);
279
280 return E1000_SUCCESS;
281 }
282
283 /**
284 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
285 * @hw: pointer to the HW structure
286 *
287 * Called to initialize all function pointers and parameters.
288 **/
289 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
290 {
291 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
292
293 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
294 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
295 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
296 }
297
298 /**
299 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
300 * @hw: pointer to the HW structure
301 *
302 * A wrapper to acquire access rights to the correct PHY.
303 **/
304 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
305 {
306 u16 mask;
307
308 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
309
310 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
311 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
312 }
313
314 /**
315 * e1000_release_phy_80003es2lan - Release rights to access PHY
316 * @hw: pointer to the HW structure
317 *
318 * A wrapper to release access rights to the correct PHY.
319 **/
320 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
321 {
322 u16 mask;
323
324 DEBUGFUNC("e1000_release_phy_80003es2lan");
325
326 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
327 e1000_release_swfw_sync_80003es2lan(hw, mask);
328 }
329
330 /**
331 * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
332 * @hw: pointer to the HW structure
333 *
334 * Acquire the semaphore to access the Kumeran interface.
335 *
336 **/
337 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
338 {
339 u16 mask;
340
341 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
342
343 mask = E1000_SWFW_CSR_SM;
344
345 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
346 }
347
348 /**
349 * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
350 * @hw: pointer to the HW structure
351 *
352 * Release the semaphore used to access the Kumeran interface
353 **/
354 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
355 {
356 u16 mask;
357
358 DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
359
360 mask = E1000_SWFW_CSR_SM;
361
362 e1000_release_swfw_sync_80003es2lan(hw, mask);
363 }
364
365 /**
366 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
367 * @hw: pointer to the HW structure
368 *
369 * Acquire the semaphore to access the EEPROM.
370 **/
371 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
372 {
373 s32 ret_val;
374
375 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
376
377 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
378 if (ret_val)
379 goto out;
380
381 ret_val = e1000_acquire_nvm_generic(hw);
382
383 if (ret_val)
384 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
385
386 out:
387 return ret_val;
388 }
389
390 /**
391 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
392 * @hw: pointer to the HW structure
393 *
394 * Release the semaphore used to access the EEPROM.
395 **/
396 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
397 {
398 DEBUGFUNC("e1000_release_nvm_80003es2lan");
399
400 e1000_release_nvm_generic(hw);
401 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
402 }
403
404 /**
405 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
406 * @hw: pointer to the HW structure
407 * @mask: specifies which semaphore to acquire
408 *
409 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
410 * will also specify which port we're acquiring the lock for.
411 **/
412 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
413 {
414 u32 swfw_sync;
415 u32 swmask = mask;
416 u32 fwmask = mask << 16;
417 s32 ret_val = E1000_SUCCESS;
418 s32 i = 0, timeout = 50;
419
420 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
421
422 while (i < timeout) {
423 if (e1000_get_hw_semaphore_generic(hw)) {
424 ret_val = -E1000_ERR_SWFW_SYNC;
425 goto out;
426 }
427
428 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
429 if (!(swfw_sync & (fwmask | swmask)))
430 break;
431
432 /*
433 * Firmware currently using resource (fwmask)
434 * or other software thread using resource (swmask)
435 */
436 e1000_put_hw_semaphore_generic(hw);
437 msec_delay_irq(5);
438 i++;
439 }
440
441 if (i == timeout) {
442 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
443 ret_val = -E1000_ERR_SWFW_SYNC;
444 goto out;
445 }
446
447 swfw_sync |= swmask;
448 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
449
450 e1000_put_hw_semaphore_generic(hw);
451
452 out:
453 return ret_val;
454 }
455
456 /**
457 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
458 * @hw: pointer to the HW structure
459 * @mask: specifies which semaphore to acquire
460 *
461 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
462 * will also specify which port we're releasing the lock for.
463 **/
464 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
465 {
466 u32 swfw_sync;
467
468 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
469
470 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
471 ; /* Empty */
472
473 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
474 swfw_sync &= ~mask;
475 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
476
477 e1000_put_hw_semaphore_generic(hw);
478 }
479
480 /**
481 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
482 * @hw: pointer to the HW structure
483 * @offset: offset of the register to read
484 * @data: pointer to the data returned from the operation
485 *
486 * Read the GG82563 PHY register.
487 **/
488 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
489 u32 offset, u16 *data)
490 {
491 s32 ret_val;
492 u32 page_select;
493 u16 temp;
494
495 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
496
497 ret_val = e1000_acquire_phy_80003es2lan(hw);
498 if (ret_val)
499 goto out;
500
501 /* Select Configuration Page */
502 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
503 page_select = GG82563_PHY_PAGE_SELECT;
504 } else {
505 /*
506 * Use Alternative Page Select register to access
507 * registers 30 and 31
508 */
509 page_select = GG82563_PHY_PAGE_SELECT_ALT;
510 }
511
512 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
513 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
514 if (ret_val) {
515 e1000_release_phy_80003es2lan(hw);
516 goto out;
517 }
518
519 if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) {
520 /*
521 * The "ready" bit in the MDIC register may be incorrectly set
522 * before the device has completed the "Page Select" MDI
523 * transaction. So we wait 200us after each MDI command...
524 */
525 usec_delay(200);
526
527 /* ...and verify the command was successful. */
528 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
529
530 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
531 ret_val = -E1000_ERR_PHY;
532 e1000_release_phy_80003es2lan(hw);
533 goto out;
534 }
535
536 usec_delay(200);
537
538 ret_val = e1000_read_phy_reg_mdic(hw,
539 MAX_PHY_REG_ADDRESS & offset,
540 data);
541
542 usec_delay(200);
543 } else {
544 ret_val = e1000_read_phy_reg_mdic(hw,
545 MAX_PHY_REG_ADDRESS & offset,
546 data);
547 }
548
549 e1000_release_phy_80003es2lan(hw);
550
551 out:
552 return ret_val;
553 }
554
555 /**
556 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
557 * @hw: pointer to the HW structure
558 * @offset: offset of the register to read
559 * @data: value to write to the register
560 *
561 * Write to the GG82563 PHY register.
562 **/
563 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
564 u32 offset, u16 data)
565 {
566 s32 ret_val;
567 u32 page_select;
568 u16 temp;
569
570 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
571
572 ret_val = e1000_acquire_phy_80003es2lan(hw);
573 if (ret_val)
574 goto out;
575
576 /* Select Configuration Page */
577 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
578 page_select = GG82563_PHY_PAGE_SELECT;
579 } else {
580 /*
581 * Use Alternative Page Select register to access
582 * registers 30 and 31
583 */
584 page_select = GG82563_PHY_PAGE_SELECT_ALT;
585 }
586
587 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
588 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
589 if (ret_val) {
590 e1000_release_phy_80003es2lan(hw);
591 goto out;
592 }
593
594 if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) {
595 /*
596 * The "ready" bit in the MDIC register may be incorrectly set
597 * before the device has completed the "Page Select" MDI
598 * transaction. So we wait 200us after each MDI command...
599 */
600 usec_delay(200);
601
602 /* ...and verify the command was successful. */
603 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
604
605 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
606 ret_val = -E1000_ERR_PHY;
607 e1000_release_phy_80003es2lan(hw);
608 goto out;
609 }
610
611 usec_delay(200);
612
613 ret_val = e1000_write_phy_reg_mdic(hw,
614 MAX_PHY_REG_ADDRESS & offset,
615 data);
616
617 usec_delay(200);
618 } else {
619 ret_val = e1000_write_phy_reg_mdic(hw,
620 MAX_PHY_REG_ADDRESS & offset,
621 data);
622 }
623
624 e1000_release_phy_80003es2lan(hw);
625
626 out:
627 return ret_val;
628 }
629
630 /**
631 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
632 * @hw: pointer to the HW structure
633 * @offset: offset of the register to read
634 * @words: number of words to write
635 * @data: buffer of data to write to the NVM
636 *
637 * Write "words" of data to the ESB2 NVM.
638 **/
639 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
640 u16 words, u16 *data)
641 {
642 DEBUGFUNC("e1000_write_nvm_80003es2lan");
643
644 return e1000_write_nvm_spi(hw, offset, words, data);
645 }
646
647 /**
648 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
649 * @hw: pointer to the HW structure
650 *
651 * Wait a specific amount of time for manageability processes to complete.
652 * This is a function pointer entry point called by the phy module.
653 **/
654 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
655 {
656 s32 timeout = PHY_CFG_TIMEOUT;
657 s32 ret_val = E1000_SUCCESS;
658 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
659
660 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
661
662 if (hw->bus.func == 1)
663 mask = E1000_NVM_CFG_DONE_PORT_1;
664
665 while (timeout) {
666 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
667 break;
668 msec_delay(1);
669 timeout--;
670 }
671 if (!timeout) {
672 DEBUGOUT("MNG configuration cycle has not completed.\n");
673 ret_val = -E1000_ERR_RESET;
674 goto out;
675 }
676
677 out:
678 return ret_val;
679 }
680
681 /**
682 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
683 * @hw: pointer to the HW structure
684 *
685 * Force the speed and duplex settings onto the PHY. This is a
686 * function pointer entry point called by the phy module.
687 **/
688 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
689 {
690 s32 ret_val = E1000_SUCCESS;
691 u16 phy_data;
692 bool link;
693
694 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
695
696 if (!(hw->phy.ops.read_reg))
697 goto out;
698
699 /*
700 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
701 * forced whenever speed and duplex are forced.
702 */
703 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
704 if (ret_val)
705 goto out;
706
707 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
708 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
709 if (ret_val)
710 goto out;
711
712 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
713
714 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
715 if (ret_val)
716 goto out;
717
718 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
719
720 /* Reset the phy to commit changes. */
721 phy_data |= MII_CR_RESET;
722
723 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
724 if (ret_val)
725 goto out;
726
727 usec_delay(1);
728
729 if (hw->phy.autoneg_wait_to_complete) {
730 DEBUGOUT("Waiting for forced speed/duplex link "
731 "on GG82563 phy.\n");
732
733 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
734 100000, &link);
735 if (ret_val)
736 goto out;
737
738 if (!link) {
739 /*
740 * We didn't get link.
741 * Reset the DSP and cross our fingers.
742 */
743 ret_val = e1000_phy_reset_dsp_generic(hw);
744 if (ret_val)
745 goto out;
746 }
747
748 /* Try once more */
749 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
750 100000, &link);
751 if (ret_val)
752 goto out;
753 }
754
755 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
756 if (ret_val)
757 goto out;
758
759 /*
760 * Resetting the phy means we need to verify the TX_CLK corresponds
761 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
762 */
763 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
764 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
765 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
766 else
767 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
768
769 /*
770 * In addition, we must re-enable CRS on Tx for both half and full
771 * duplex.
772 */
773 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
774 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
775
776 out:
777 return ret_val;
778 }
779
780 /**
781 * e1000_get_cable_length_80003es2lan - Set approximate cable length
782 * @hw: pointer to the HW structure
783 *
784 * Find the approximate cable length as measured by the GG82563 PHY.
785 * This is a function pointer entry point called by the phy module.
786 **/
787 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
788 {
789 struct e1000_phy_info *phy = &hw->phy;
790 s32 ret_val = E1000_SUCCESS;
791 u16 phy_data, index;
792
793 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
794
795 if (!(hw->phy.ops.read_reg))
796 goto out;
797
798 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
799 if (ret_val)
800 goto out;
801
802 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
803
804 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
805 ret_val = -E1000_ERR_PHY;
806 goto out;
807 }
808
809 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
810 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
811
812 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
813
814 out:
815 return ret_val;
816 }
817
818 /**
819 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
820 * @hw: pointer to the HW structure
821 * @speed: pointer to speed buffer
822 * @duplex: pointer to duplex buffer
823 *
824 * Retrieve the current speed and duplex configuration.
825 **/
826 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
827 u16 *duplex)
828 {
829 s32 ret_val;
830
831 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
832
833 if (hw->phy.media_type == e1000_media_type_copper) {
834 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
835 speed,
836 duplex);
837 hw->phy.ops.cfg_on_link_up(hw);
838 } else {
839 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
840 speed,
841 duplex);
842 }
843
844 return ret_val;
845 }
846
847 /**
848 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
849 * @hw: pointer to the HW structure
850 *
851 * Perform a global reset to the ESB2 controller.
852 **/
853 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
854 {
855 u32 ctrl, icr;
856 s32 ret_val;
857
858 DEBUGFUNC("e1000_reset_hw_80003es2lan");
859
860 /*
861 * Prevent the PCI-E bus from sticking if there is no TLP connection
862 * on the last TLP read/write transaction when MAC is reset.
863 */
864 ret_val = e1000_disable_pcie_master_generic(hw);
865 if (ret_val)
866 DEBUGOUT("PCI-E Master disable polling has failed.\n");
867
868 DEBUGOUT("Masking off all interrupts\n");
869 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
870
871 E1000_WRITE_REG(hw, E1000_RCTL, 0);
872 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
873 E1000_WRITE_FLUSH(hw);
874
875 msec_delay(10);
876
877 ctrl = E1000_READ_REG(hw, E1000_CTRL);
878
879 ret_val = e1000_acquire_phy_80003es2lan(hw);
880 DEBUGOUT("Issuing a global reset to MAC\n");
881 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
882 e1000_release_phy_80003es2lan(hw);
883
884 ret_val = e1000_get_auto_rd_done_generic(hw);
885 if (ret_val)
886 /* We don't want to continue accessing MAC registers. */
887 goto out;
888
889 /* Clear any pending interrupt events. */
890 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
891 icr = E1000_READ_REG(hw, E1000_ICR);
892
893 ret_val = e1000_check_alt_mac_addr_generic(hw);
894
895 out:
896 return ret_val;
897 }
898
899 /**
900 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
901 * @hw: pointer to the HW structure
902 *
903 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
904 **/
905 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
906 {
907 struct e1000_mac_info *mac = &hw->mac;
908 u32 reg_data;
909 s32 ret_val;
910 u16 i;
911
912 DEBUGFUNC("e1000_init_hw_80003es2lan");
913
914 e1000_initialize_hw_bits_80003es2lan(hw);
915
916 /* Initialize identification LED */
917 ret_val = mac->ops.id_led_init(hw);
918 if (ret_val)
919 DEBUGOUT("Error initializing identification LED\n");
920 /* This is not fatal and we should not stop init due to this */
921
922 /* Disabling VLAN filtering */
923 DEBUGOUT("Initializing the IEEE VLAN\n");
924 mac->ops.clear_vfta(hw);
925
926 /* Setup the receive address. */
927 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
928
929 /* Zero out the Multicast HASH table */
930 DEBUGOUT("Zeroing the MTA\n");
931 for (i = 0; i < mac->mta_reg_count; i++)
932 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
933
934 /* Setup link and flow control */
935 ret_val = mac->ops.setup_link(hw);
936
937 /* Set the transmit descriptor write-back policy */
938 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
939 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
940 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
941 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
942
943 /* ...for both queues. */
944 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
945 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
946 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
947 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
948
949 /* Enable retransmit on late collisions */
950 reg_data = E1000_READ_REG(hw, E1000_TCTL);
951 reg_data |= E1000_TCTL_RTLC;
952 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
953
954 /* Configure Gigabit Carry Extend Padding */
955 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
956 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
957 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
958 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
959
960 /* Configure Transmit Inter-Packet Gap */
961 reg_data = E1000_READ_REG(hw, E1000_TIPG);
962 reg_data &= ~E1000_TIPG_IPGT_MASK;
963 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
964 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
965
966 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
967 reg_data &= ~0x00100000;
968 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
969
970 /* default to TRUE to enable the MDIC W/A */
971 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
972
973 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
974 E1000_KMRNCTRLSTA_OFFSET >>
975 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
976 &i);
977 if (!ret_val) {
978 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
979 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
980 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE;
981 }
982
983 /*
984 * Clear all of the statistics registers (clear on read). It is
985 * important that we do this after we have tried to establish link
986 * because the symbol error count will increment wildly if there
987 * is no link.
988 */
989 e1000_clear_hw_cntrs_80003es2lan(hw);
990
991 return ret_val;
992 }
993
994 /**
995 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
996 * @hw: pointer to the HW structure
997 *
998 * Initializes required hardware-dependent bits needed for normal operation.
999 **/
1000 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
1001 {
1002 u32 reg;
1003
1004 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
1005
1006 /* Transmit Descriptor Control 0 */
1007 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1008 reg |= (1 << 22);
1009 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1010
1011 /* Transmit Descriptor Control 1 */
1012 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1013 reg |= (1 << 22);
1014 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1015
1016 /* Transmit Arbitration Control 0 */
1017 reg = E1000_READ_REG(hw, E1000_TARC(0));
1018 reg &= ~(0xF << 27); /* 30:27 */
1019 if (hw->phy.media_type != e1000_media_type_copper)
1020 reg &= ~(1 << 20);
1021 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1022
1023 /* Transmit Arbitration Control 1 */
1024 reg = E1000_READ_REG(hw, E1000_TARC(1));
1025 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1026 reg &= ~(1 << 28);
1027 else
1028 reg |= (1 << 28);
1029 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1030
1031 return;
1032 }
1033
1034 /**
1035 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1036 * @hw: pointer to the HW structure
1037 *
1038 * Setup some GG82563 PHY registers for obtaining link
1039 **/
1040 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1041 {
1042 struct e1000_phy_info *phy = &hw->phy;
1043 s32 ret_val;
1044 u32 ctrl_ext;
1045 u16 data;
1046
1047 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1048
1049 if (phy->reset_disable)
1050 goto skip_reset;
1051
1052 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1053 &data);
1054 if (ret_val)
1055 goto out;
1056
1057 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1058 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1059 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1060
1061 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1062 data);
1063 if (ret_val)
1064 goto out;
1065
1066 /*
1067 * Options:
1068 * MDI/MDI-X = 0 (default)
1069 * 0 - Auto for all speeds
1070 * 1 - MDI mode
1071 * 2 - MDI-X mode
1072 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1073 */
1074 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1075 if (ret_val)
1076 goto out;
1077
1078 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1079
1080 switch (phy->mdix) {
1081 case 1:
1082 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1083 break;
1084 case 2:
1085 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1086 break;
1087 case 0:
1088 default:
1089 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1090 break;
1091 }
1092
1093 /*
1094 * Options:
1095 * disable_polarity_correction = 0 (default)
1096 * Automatic Correction for Reversed Cable Polarity
1097 * 0 - Disabled
1098 * 1 - Enabled
1099 */
1100 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1101 if (phy->disable_polarity_correction)
1102 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1103
1104 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1105 if (ret_val)
1106 goto out;
1107
1108 /* SW Reset the PHY so all changes take effect */
1109 ret_val = hw->phy.ops.commit(hw);
1110 if (ret_val) {
1111 DEBUGOUT("Error Resetting the PHY\n");
1112 goto out;
1113 }
1114
1115 skip_reset:
1116 /* Bypass Rx and Tx FIFO's */
1117 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1118 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1119 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1120 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1121 if (ret_val)
1122 goto out;
1123
1124 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1125 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1126 &data);
1127 if (ret_val)
1128 goto out;
1129 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1130 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1131 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1132 data);
1133 if (ret_val)
1134 goto out;
1135
1136 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1137 if (ret_val)
1138 goto out;
1139
1140 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1141 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1142 if (ret_val)
1143 goto out;
1144
1145 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1146 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1147 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1148
1149 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1150 if (ret_val)
1151 goto out;
1152
1153 /*
1154 * Do not init these registers when the HW is in IAMT mode, since the
1155 * firmware will have already initialized them. We only initialize
1156 * them if the HW is not in IAMT mode.
1157 */
1158 if (!(hw->mac.ops.check_mng_mode(hw))) {
1159 /* Enable Electrical Idle on the PHY */
1160 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1161 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1162 data);
1163 if (ret_val)
1164 goto out;
1165
1166 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1167 &data);
1168 if (ret_val)
1169 goto out;
1170
1171 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1172 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1173 data);
1174 if (ret_val)
1175 goto out;
1176 }
1177
1178 /*
1179 * Workaround: Disable padding in Kumeran interface in the MAC
1180 * and in the PHY to avoid CRC errors.
1181 */
1182 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1183 if (ret_val)
1184 goto out;
1185
1186 data |= GG82563_ICR_DIS_PADDING;
1187 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1188 if (ret_val)
1189 goto out;
1190
1191 out:
1192 return ret_val;
1193 }
1194
1195 /**
1196 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1197 * @hw: pointer to the HW structure
1198 *
1199 * Essentially a wrapper for setting up all things "copper" related.
1200 * This is a function pointer entry point called by the mac module.
1201 **/
1202 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1203 {
1204 u32 ctrl;
1205 s32 ret_val;
1206 u16 reg_data;
1207
1208 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1209
1210 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1211 ctrl |= E1000_CTRL_SLU;
1212 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1213 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1214
1215 /*
1216 * Set the mac to wait the maximum time between each
1217 * iteration and increase the max iterations when
1218 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1219 */
1220 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1221 0xFFFF);
1222 if (ret_val)
1223 goto out;
1224 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1225 &reg_data);
1226 if (ret_val)
1227 goto out;
1228 reg_data |= 0x3F;
1229 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1230 reg_data);
1231 if (ret_val)
1232 goto out;
1233 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1234 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1235 &reg_data);
1236 if (ret_val)
1237 goto out;
1238 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1239 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1240 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1241 reg_data);
1242 if (ret_val)
1243 goto out;
1244
1245 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1246 if (ret_val)
1247 goto out;
1248
1249 ret_val = e1000_setup_copper_link_generic(hw);
1250
1251 out:
1252 return ret_val;
1253 }
1254
1255 /**
1256 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1257 * @hw: pointer to the HW structure
1258 * @duplex: current duplex setting
1259 *
1260 * Configure the KMRN interface by applying last minute quirks for
1261 * 10/100 operation.
1262 **/
1263 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1264 {
1265 s32 ret_val = E1000_SUCCESS;
1266 u16 speed;
1267 u16 duplex;
1268
1269 DEBUGFUNC("e1000_configure_on_link_up");
1270
1271 if (hw->phy.media_type == e1000_media_type_copper) {
1272 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
1273 &speed,
1274 &duplex);
1275 if (ret_val)
1276 goto out;
1277
1278 if (speed == SPEED_1000)
1279 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1280 else
1281 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1282 }
1283
1284 out:
1285 return ret_val;
1286 }
1287
1288 /**
1289 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1290 * @hw: pointer to the HW structure
1291 * @duplex: current duplex setting
1292 *
1293 * Configure the KMRN interface by applying last minute quirks for
1294 * 10/100 operation.
1295 **/
1296 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1297 {
1298 s32 ret_val = E1000_SUCCESS;
1299 u32 tipg;
1300 u32 i = 0;
1301 u16 reg_data, reg_data2;
1302
1303 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1304
1305 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1306 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1307 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1308 reg_data);
1309 if (ret_val)
1310 goto out;
1311
1312 /* Configure Transmit Inter-Packet Gap */
1313 tipg = E1000_READ_REG(hw, E1000_TIPG);
1314 tipg &= ~E1000_TIPG_IPGT_MASK;
1315 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1316 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1317
1318 do {
1319 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1320 &reg_data);
1321 if (ret_val)
1322 goto out;
1323
1324 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1325 &reg_data2);
1326 if (ret_val)
1327 goto out;
1328 i++;
1329 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1330
1331 if (duplex == HALF_DUPLEX)
1332 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1333 else
1334 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1335
1336 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1337
1338 out:
1339 return ret_val;
1340 }
1341
1342 /**
1343 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1344 * @hw: pointer to the HW structure
1345 *
1346 * Configure the KMRN interface by applying last minute quirks for
1347 * gigabit operation.
1348 **/
1349 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1350 {
1351 s32 ret_val = E1000_SUCCESS;
1352 u16 reg_data, reg_data2;
1353 u32 tipg;
1354 u32 i = 0;
1355
1356 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1357
1358 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1359 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1360 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1361 reg_data);
1362 if (ret_val)
1363 goto out;
1364
1365 /* Configure Transmit Inter-Packet Gap */
1366 tipg = E1000_READ_REG(hw, E1000_TIPG);
1367 tipg &= ~E1000_TIPG_IPGT_MASK;
1368 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1369 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1370
1371 do {
1372 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1373 &reg_data);
1374 if (ret_val)
1375 goto out;
1376
1377 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1378 &reg_data2);
1379 if (ret_val)
1380 goto out;
1381 i++;
1382 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1383
1384 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1385 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1386
1387 out:
1388 return ret_val;
1389 }
1390
1391 /**
1392 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1393 * @hw: pointer to the HW structure
1394 * @offset: register offset to be read
1395 * @data: pointer to the read data
1396 *
1397 * Acquire semaphore, then read the PHY register at offset
1398 * using the kumeran interface. The information retrieved is stored in data.
1399 * Release the semaphore before exiting.
1400 **/
1401 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1402 u16 *data)
1403 {
1404 u32 kmrnctrlsta;
1405 s32 ret_val = E1000_SUCCESS;
1406
1407 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1408
1409 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1410 if (ret_val)
1411 goto out;
1412
1413 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1414 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1415 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1416
1417 usec_delay(2);
1418
1419 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1420 *data = (u16)kmrnctrlsta;
1421
1422 e1000_release_mac_csr_80003es2lan(hw);
1423
1424 out:
1425 return ret_val;
1426 }
1427
1428 /**
1429 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1430 * @hw: pointer to the HW structure
1431 * @offset: register offset to write to
1432 * @data: data to write at register offset
1433 *
1434 * Acquire semaphore, then write the data to PHY register
1435 * at the offset using the kumeran interface. Release semaphore
1436 * before exiting.
1437 **/
1438 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1439 u16 data)
1440 {
1441 u32 kmrnctrlsta;
1442 s32 ret_val = E1000_SUCCESS;
1443
1444 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1445
1446 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1447 if (ret_val)
1448 goto out;
1449
1450 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1451 E1000_KMRNCTRLSTA_OFFSET) | data;
1452 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1453
1454 usec_delay(2);
1455
1456 e1000_release_mac_csr_80003es2lan(hw);
1457
1458 out:
1459 return ret_val;
1460 }
1461
1462 /**
1463 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1464 * @hw: pointer to the HW structure
1465 **/
1466 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1467 {
1468 s32 ret_val = E1000_SUCCESS;
1469
1470 DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1471
1472 /*
1473 * If there's an alternate MAC address place it in RAR0
1474 * so that it will override the Si installed default perm
1475 * address.
1476 */
1477 ret_val = e1000_check_alt_mac_addr_generic(hw);
1478 if (ret_val)
1479 goto out;
1480
1481 ret_val = e1000_read_mac_addr_generic(hw);
1482
1483 out:
1484 return ret_val;
1485 }
1486
1487 /**
1488 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1489 * @hw: pointer to the HW structure
1490 *
1491 * In the case of a PHY power down to save power, or to turn off link during a
1492 * driver unload, or wake on lan is not enabled, remove the link.
1493 **/
1494 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1495 {
1496 /* If the management interface is not enabled, then power down */
1497 if (!(hw->mac.ops.check_mng_mode(hw) ||
1498 hw->phy.ops.check_reset_block(hw)))
1499 e1000_power_down_phy_copper(hw);
1500
1501 return;
1502 }
1503
1504 /**
1505 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1506 * @hw: pointer to the HW structure
1507 *
1508 * Clears the hardware counters by reading the counter registers.
1509 **/
1510 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1511 {
1512 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1513
1514 e1000_clear_hw_cntrs_base_generic(hw);
1515
1516 E1000_READ_REG(hw, E1000_PRC64);
1517 E1000_READ_REG(hw, E1000_PRC127);
1518 E1000_READ_REG(hw, E1000_PRC255);
1519 E1000_READ_REG(hw, E1000_PRC511);
1520 E1000_READ_REG(hw, E1000_PRC1023);
1521 E1000_READ_REG(hw, E1000_PRC1522);
1522 E1000_READ_REG(hw, E1000_PTC64);
1523 E1000_READ_REG(hw, E1000_PTC127);
1524 E1000_READ_REG(hw, E1000_PTC255);
1525 E1000_READ_REG(hw, E1000_PTC511);
1526 E1000_READ_REG(hw, E1000_PTC1023);
1527 E1000_READ_REG(hw, E1000_PTC1522);
1528
1529 E1000_READ_REG(hw, E1000_ALGNERRC);
1530 E1000_READ_REG(hw, E1000_RXERRC);
1531 E1000_READ_REG(hw, E1000_TNCRS);
1532 E1000_READ_REG(hw, E1000_CEXTERR);
1533 E1000_READ_REG(hw, E1000_TSCTC);
1534 E1000_READ_REG(hw, E1000_TSCTFC);
1535
1536 E1000_READ_REG(hw, E1000_MGTPRC);
1537 E1000_READ_REG(hw, E1000_MGTPDC);
1538 E1000_READ_REG(hw, E1000_MGTPTC);
1539
1540 E1000_READ_REG(hw, E1000_IAC);
1541 E1000_READ_REG(hw, E1000_ICRXOC);
1542
1543 E1000_READ_REG(hw, E1000_ICRXPTC);
1544 E1000_READ_REG(hw, E1000_ICRXATC);
1545 E1000_READ_REG(hw, E1000_ICTXPTC);
1546 E1000_READ_REG(hw, E1000_ICTXATC);
1547 E1000_READ_REG(hw, E1000_ICTXQEC);
1548 E1000_READ_REG(hw, E1000_ICTXQMTC);
1549 E1000_READ_REG(hw, E1000_ICRXDMTC);
1550 }
DragonFly BSD