2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $FreeBSD: src/sys/dev/pci/pci_pci.c,v 1.50.2.2.4.1 2009/04/15 03:14:26 kensmith Exp $
34 * PCI:PCI bridge support.
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
43 #include <sys/sysctl.h>
44 #include <machine_base/apic/ioapic.h>
46 #include <bus/pci/pcivar.h>
47 #include <bus/pci/pcireg.h>
48 #include <bus/pci/pcib_private.h>
52 static int pcib_probe(device_t dev
);
54 static device_method_t pcib_methods
[] = {
55 /* Device interface */
56 DEVMETHOD(device_probe
, pcib_probe
),
57 DEVMETHOD(device_attach
, pcib_attach
),
58 DEVMETHOD(device_detach
, bus_generic_detach
),
59 DEVMETHOD(device_shutdown
, bus_generic_shutdown
),
60 DEVMETHOD(device_suspend
, bus_generic_suspend
),
61 DEVMETHOD(device_resume
, bus_generic_resume
),
64 DEVMETHOD(bus_print_child
, bus_generic_print_child
),
65 DEVMETHOD(bus_read_ivar
, pcib_read_ivar
),
66 DEVMETHOD(bus_write_ivar
, pcib_write_ivar
),
67 DEVMETHOD(bus_alloc_resource
, pcib_alloc_resource
),
68 DEVMETHOD(bus_release_resource
, bus_generic_release_resource
),
69 DEVMETHOD(bus_activate_resource
, bus_generic_activate_resource
),
70 DEVMETHOD(bus_deactivate_resource
, bus_generic_deactivate_resource
),
71 DEVMETHOD(bus_setup_intr
, bus_generic_setup_intr
),
72 DEVMETHOD(bus_teardown_intr
, bus_generic_teardown_intr
),
75 DEVMETHOD(pcib_maxslots
, pcib_maxslots
),
76 DEVMETHOD(pcib_read_config
, pcib_read_config
),
77 DEVMETHOD(pcib_write_config
, pcib_write_config
),
78 DEVMETHOD(pcib_route_interrupt
, pcib_route_interrupt
),
79 DEVMETHOD(pcib_alloc_msi
, pcib_alloc_msi
),
80 DEVMETHOD(pcib_release_msi
, pcib_release_msi
),
81 DEVMETHOD(pcib_alloc_msix
, pcib_alloc_msix
),
82 DEVMETHOD(pcib_release_msix
, pcib_release_msix
),
83 DEVMETHOD(pcib_map_msi
, pcib_map_msi
),
88 static devclass_t pcib_devclass
;
90 DEFINE_CLASS_0(pcib
, pcib_driver
, pcib_methods
, sizeof(struct pcib_softc
));
91 DRIVER_MODULE(pcib
, pci
, pcib_driver
, pcib_devclass
, NULL
, NULL
);
94 * Is the prefetch window open (eg, can we allocate memory in it?)
97 pcib_is_prefetch_open(struct pcib_softc
*sc
)
99 return (sc
->pmembase
> 0 && sc
->pmembase
< sc
->pmemlimit
);
103 * Is the nonprefetch window open (eg, can we allocate memory in it?)
106 pcib_is_nonprefetch_open(struct pcib_softc
*sc
)
108 return (sc
->membase
> 0 && sc
->membase
< sc
->memlimit
);
112 * Is the io window open (eg, can we allocate ports in it?)
115 pcib_is_io_open(struct pcib_softc
*sc
)
117 return (sc
->iobase
> 0 && sc
->iobase
< sc
->iolimit
);
121 * Generic device interface
124 pcib_probe(device_t dev
)
126 if ((pci_get_class(dev
) == PCIC_BRIDGE
) &&
127 (pci_get_subclass(dev
) == PCIS_BRIDGE_PCI
)) {
128 device_set_desc(dev
, "PCI-PCI bridge");
129 #if defined(__x86_64__)
130 /* PCIBIOS PCI-PCI bridge is -2000 */
140 pcib_attach_common(device_t dev
)
142 struct pcib_softc
*sc
;
145 sc
= device_get_softc(dev
);
149 * Get current bridge configuration.
151 sc
->command
= pci_read_config(dev
, PCIR_COMMAND
, 1);
152 sc
->domain
= pci_get_domain(dev
);
153 sc
->secbus
= pci_read_config(dev
, PCIR_SECBUS_1
, 1);
154 sc
->subbus
= pci_read_config(dev
, PCIR_SUBBUS_1
, 1);
155 sc
->secstat
= pci_read_config(dev
, PCIR_SECSTAT_1
, 2);
156 sc
->bridgectl
= pci_read_config(dev
, PCIR_BRIDGECTL_1
, 2);
157 sc
->seclat
= pci_read_config(dev
, PCIR_SECLAT_1
, 1);
160 * Determine current I/O decode.
162 if (sc
->command
& PCIM_CMD_PORTEN
) {
163 iolow
= pci_read_config(dev
, PCIR_IOBASEL_1
, 1);
164 if ((iolow
& PCIM_BRIO_MASK
) == PCIM_BRIO_32
) {
165 sc
->iobase
= PCI_PPBIOBASE(pci_read_config(dev
, PCIR_IOBASEH_1
, 2),
166 pci_read_config(dev
, PCIR_IOBASEL_1
, 1));
168 sc
->iobase
= PCI_PPBIOBASE(0, pci_read_config(dev
, PCIR_IOBASEL_1
, 1));
171 iolow
= pci_read_config(dev
, PCIR_IOLIMITL_1
, 1);
172 if ((iolow
& PCIM_BRIO_MASK
) == PCIM_BRIO_32
) {
173 sc
->iolimit
= PCI_PPBIOLIMIT(pci_read_config(dev
, PCIR_IOLIMITH_1
, 2),
174 pci_read_config(dev
, PCIR_IOLIMITL_1
, 1));
176 sc
->iolimit
= PCI_PPBIOLIMIT(0, pci_read_config(dev
, PCIR_IOLIMITL_1
, 1));
181 * Determine current memory decode.
183 if (sc
->command
& PCIM_CMD_MEMEN
) {
184 sc
->membase
= PCI_PPBMEMBASE(0, pci_read_config(dev
, PCIR_MEMBASE_1
, 2));
185 sc
->memlimit
= PCI_PPBMEMLIMIT(0, pci_read_config(dev
, PCIR_MEMLIMIT_1
, 2));
186 iolow
= pci_read_config(dev
, PCIR_PMBASEL_1
, 1);
187 if ((iolow
& PCIM_BRPM_MASK
) == PCIM_BRPM_64
)
188 sc
->pmembase
= PCI_PPBMEMBASE(
189 pci_read_config(dev
, PCIR_PMBASEH_1
, 4),
190 pci_read_config(dev
, PCIR_PMBASEL_1
, 2));
192 sc
->pmembase
= PCI_PPBMEMBASE(0,
193 pci_read_config(dev
, PCIR_PMBASEL_1
, 2));
194 iolow
= pci_read_config(dev
, PCIR_PMLIMITL_1
, 1);
195 if ((iolow
& PCIM_BRPM_MASK
) == PCIM_BRPM_64
)
196 sc
->pmemlimit
= PCI_PPBMEMLIMIT(
197 pci_read_config(dev
, PCIR_PMLIMITH_1
, 4),
198 pci_read_config(dev
, PCIR_PMLIMITL_1
, 2));
200 sc
->pmemlimit
= PCI_PPBMEMLIMIT(0,
201 pci_read_config(dev
, PCIR_PMLIMITL_1
, 2));
207 switch (pci_get_devid(dev
)) {
208 case 0x12258086: /* Intel 82454KX/GX (Orion) */
212 supbus
= pci_read_config(dev
, 0x41, 1);
213 if (supbus
!= 0xff) {
214 sc
->secbus
= supbus
+ 1;
215 sc
->subbus
= supbus
+ 1;
221 * The i82380FB mobile docking controller is a PCI-PCI bridge,
222 * and it is a subtractive bridge. However, the ProgIf is wrong
223 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
224 * happen. There's also a Toshiba bridge that behaves this
227 case 0x124b8086: /* Intel 82380FB Mobile */
228 case 0x060513d7: /* Toshiba ???? */
229 sc
->flags
|= PCIB_SUBTRACTIVE
;
232 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
237 if ((cp
= kgetenv("smbios.planar.maker")) == NULL
)
239 if (strncmp(cp
, "Compal", 6) != 0) {
244 if ((cp
= kgetenv("smbios.planar.product")) == NULL
)
246 if (strncmp(cp
, "08A0", 4) != 0) {
251 if (sc
->subbus
< 0xa) {
252 pci_write_config(dev
, PCIR_SUBBUS_1
, 0xa, 1);
253 sc
->subbus
= pci_read_config(dev
, PCIR_SUBBUS_1
, 1);
259 if (pci_msi_device_blacklisted(dev
))
260 sc
->flags
|= PCIB_DISABLE_MSI
;
263 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
264 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
265 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
266 * This means they act as if they were subtractively decoding
267 * bridges and pass all transactions. Mark them and real ProgIf 1
268 * parts as subtractive.
270 if ((pci_get_devid(dev
) & 0xff00ffff) == 0x24008086 ||
271 pci_read_config(dev
, PCIR_PROGIF
, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE
)
272 sc
->flags
|= PCIB_SUBTRACTIVE
;
275 device_printf(dev
, " domain %d\n", sc
->domain
);
276 device_printf(dev
, " secondary bus %d\n", sc
->secbus
);
277 device_printf(dev
, " subordinate bus %d\n", sc
->subbus
);
278 device_printf(dev
, " I/O decode 0x%x-0x%x\n", sc
->iobase
, sc
->iolimit
);
279 if (pcib_is_nonprefetch_open(sc
))
280 device_printf(dev
, " memory decode 0x%jx-0x%jx\n",
281 (uintmax_t)sc
->membase
, (uintmax_t)sc
->memlimit
);
282 if (pcib_is_prefetch_open(sc
))
283 device_printf(dev
, " prefetched decode 0x%jx-0x%jx\n",
284 (uintmax_t)sc
->pmembase
, (uintmax_t)sc
->pmemlimit
);
286 device_printf(dev
, " no prefetched decode\n");
287 if (sc
->flags
& PCIB_SUBTRACTIVE
)
288 device_printf(dev
, " Subtractively decoded bridge.\n");
291 if (pci_is_pcie(dev
) && pcie_slot_implemented(dev
)) {
297 * Before proper PCI Express hot-plug support is in place,
298 * disable all hot-plug interrupts on the PCI Express root
299 * port or down stream port for now.
301 #define HPINTRS (PCIEM_SLTCTL_HPINTR_MASK | PCIEM_SLTCTL_HPINTR_EN)
303 ptr
= pci_get_pciecap_ptr(dev
);
304 slot_ctrl
= pci_read_config(dev
, ptr
+ PCIER_SLOTCTRL
, 2);
305 if (slot_ctrl
& HPINTRS
) {
306 device_printf(dev
, "Disable PCI Express hot-plug "
307 "interrupts(0x%04x)\n", slot_ctrl
& HPINTRS
);
308 slot_ctrl
&= ~HPINTRS
;
309 pci_write_config(dev
, ptr
+ PCIER_SLOTCTRL
, slot_ctrl
, 2);
316 * XXX If the secondary bus number is zero, we should assign a bus number
317 * since the BIOS hasn't, then initialise the bridge.
321 * XXX If the subordinate bus number is less than the secondary bus number,
322 * we should pick a better value. One sensible alternative would be to
323 * pick 255; the only tradeoff here is that configuration transactions
324 * would be more widely routed than absolutely necessary.
329 pcib_attach(device_t dev
)
331 struct pcib_softc
*sc
;
334 pcib_attach_common(dev
);
335 sc
= device_get_softc(dev
);
336 if (sc
->secbus
!= 0) {
337 child
= device_add_child(dev
, "pci", sc
->secbus
);
339 return(bus_generic_attach(dev
));
342 /* no secondary bus; we should have fixed this */
347 pcib_read_ivar(device_t dev
, device_t child
, int which
, uintptr_t *result
)
349 struct pcib_softc
*sc
= device_get_softc(dev
);
352 case PCIB_IVAR_DOMAIN
:
353 *result
= sc
->domain
;
356 *result
= sc
->secbus
;
363 pcib_write_ivar(device_t dev
, device_t child
, int which
, uintptr_t value
)
365 struct pcib_softc
*sc
= device_get_softc(dev
);
368 case PCIB_IVAR_DOMAIN
:
378 * We have to trap resource allocation requests and ensure that the bridge
379 * is set up to, or capable of handling them.
382 pcib_alloc_resource(device_t dev
, device_t child
, int type
, int *rid
,
383 u_long start
, u_long end
, u_long count
, u_int flags
, int cpuid
)
385 struct pcib_softc
*sc
= device_get_softc(dev
);
386 const char *name
, *suffix
;
390 * Fail the allocation for this range if it's not supported.
392 name
= device_get_nameunit(child
);
401 if (!pcib_is_io_open(sc
))
403 ok
= (start
>= sc
->iobase
&& end
<= sc
->iolimit
);
406 * Make sure we allow access to VGA I/O addresses when the
407 * bridge has the "VGA Enable" bit set.
409 if (!ok
&& pci_is_vga_ioport_range(start
, end
))
410 ok
= (sc
->bridgectl
& PCIB_BCR_VGA_ENABLE
) ? 1 : 0;
412 if ((sc
->flags
& PCIB_SUBTRACTIVE
) == 0) {
414 if (start
< sc
->iobase
)
416 if (end
> sc
->iolimit
)
424 if (start
< sc
->iobase
&& end
> sc
->iolimit
) {
431 device_printf(dev
, "ioport: end (%lx) < start (%lx)\n",
438 device_printf(dev
, "%s%srequested unsupported I/O "
439 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
440 name
, suffix
, start
, end
, sc
->iobase
, sc
->iolimit
);
445 "%s%srequested I/O range 0x%lx-0x%lx: in range\n",
446 name
, suffix
, start
, end
);
451 if (pcib_is_nonprefetch_open(sc
))
452 ok
= ok
|| (start
>= sc
->membase
&& end
<= sc
->memlimit
);
453 if (pcib_is_prefetch_open(sc
))
454 ok
= ok
|| (start
>= sc
->pmembase
&& end
<= sc
->pmemlimit
);
457 * Make sure we allow access to VGA memory addresses when the
458 * bridge has the "VGA Enable" bit set.
460 if (!ok
&& pci_is_vga_memory_range(start
, end
))
461 ok
= (sc
->bridgectl
& PCIB_BCR_VGA_ENABLE
) ? 1 : 0;
463 if ((sc
->flags
& PCIB_SUBTRACTIVE
) == 0) {
466 if (flags
& RF_PREFETCHABLE
) {
467 if (pcib_is_prefetch_open(sc
)) {
468 if (start
< sc
->pmembase
)
469 start
= sc
->pmembase
;
470 if (end
> sc
->pmemlimit
)
475 } else { /* non-prefetchable */
476 if (pcib_is_nonprefetch_open(sc
)) {
477 if (start
< sc
->membase
)
479 if (end
> sc
->memlimit
)
487 ok
= 1; /* subtractive bridge: always ok */
489 if (pcib_is_nonprefetch_open(sc
)) {
490 if (start
< sc
->membase
&& end
> sc
->memlimit
) {
495 if (pcib_is_prefetch_open(sc
)) {
496 if (start
< sc
->pmembase
&& end
> sc
->pmemlimit
) {
497 start
= sc
->pmembase
;
504 device_printf(dev
, "memory: end (%lx) < start (%lx)\n",
510 if (!ok
&& bootverbose
)
512 "%s%srequested unsupported memory range %#lx-%#lx "
513 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
514 name
, suffix
, start
, end
,
515 (uintmax_t)sc
->membase
, (uintmax_t)sc
->memlimit
,
516 (uintmax_t)sc
->pmembase
, (uintmax_t)sc
->pmemlimit
);
520 device_printf(dev
,"%s%srequested memory range "
521 "0x%lx-0x%lx: good\n",
522 name
, suffix
, start
, end
);
529 * Bridge is OK decoding this resource, so pass it up.
531 return (bus_generic_alloc_resource(dev
, child
, type
, rid
, start
, end
,
532 count
, flags
, cpuid
));
539 pcib_maxslots(device_t dev
)
545 * Since we are a child of a PCI bus, its parent must support the pcib interface.
548 pcib_read_config(device_t dev
, int b
, int s
, int f
, int reg
, int width
)
550 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev
)), b
, s
, f
, reg
, width
));
554 pcib_write_config(device_t dev
, int b
, int s
, int f
, int reg
, uint32_t val
, int width
)
556 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev
)), b
, s
, f
, reg
, val
, width
);
560 * Route an interrupt across a PCI bridge.
563 pcib_route_interrupt(device_t pcib
, device_t dev
, int pin
)
571 * The PCI standard defines a swizzle of the child-side device/intpin to
572 * the parent-side intpin as follows.
574 * device = device on child bus
575 * child_intpin = intpin on child bus slot (0-3)
576 * parent_intpin = intpin on parent bus slot (0-3)
578 * parent_intpin = (device + child_intpin) % 4
580 parent_intpin
= (pci_get_slot(dev
) + (pin
- 1)) % 4;
583 * Our parent is a PCI bus. Its parent must export the pcib interface
584 * which includes the ability to route interrupts.
586 bus
= device_get_parent(pcib
);
587 intnum
= PCIB_ROUTE_INTERRUPT(device_get_parent(bus
), pcib
, parent_intpin
+ 1);
588 if (PCI_INTERRUPT_VALID(intnum
) && bootverbose
) {
589 device_printf(pcib
, "slot %d INT%c is routed to irq %d\n",
590 pci_get_slot(dev
), 'A' + pin
- 1, intnum
);
595 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
597 pcib_alloc_msi(device_t pcib
, device_t dev
, int count
, int maxcount
,
598 int *irqs
, int cpuid
)
600 struct pcib_softc
*sc
= device_get_softc(pcib
);
603 if (sc
->flags
& PCIB_DISABLE_MSI
)
605 bus
= device_get_parent(pcib
);
606 return (PCIB_ALLOC_MSI(device_get_parent(bus
), dev
, count
, maxcount
,
610 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
612 pcib_release_msi(device_t pcib
, device_t dev
, int count
, int *irqs
, int cpuid
)
616 bus
= device_get_parent(pcib
);
617 return (PCIB_RELEASE_MSI(device_get_parent(bus
), dev
, count
, irqs
,
621 /* Pass request to alloc an MSI-X message up to the parent bridge. */
623 pcib_alloc_msix(device_t pcib
, device_t dev
, int *irq
, int cpuid
)
625 struct pcib_softc
*sc
= device_get_softc(pcib
);
628 if (sc
->flags
& PCIB_DISABLE_MSI
)
630 bus
= device_get_parent(pcib
);
631 return (PCIB_ALLOC_MSIX(device_get_parent(bus
), dev
, irq
, cpuid
));
634 /* Pass request to release an MSI-X message up to the parent bridge. */
636 pcib_release_msix(device_t pcib
, device_t dev
, int irq
, int cpuid
)
640 bus
= device_get_parent(pcib
);
641 return (PCIB_RELEASE_MSIX(device_get_parent(bus
), dev
, irq
, cpuid
));
644 /* Pass request to map MSI/MSI-X message up to parent bridge. */
646 pcib_map_msi(device_t pcib
, device_t dev
, int irq
, uint64_t *addr
,
647 uint32_t *data
, int cpuid
)
652 bus
= device_get_parent(pcib
);
653 error
= PCIB_MAP_MSI(device_get_parent(bus
), dev
, irq
, addr
, data
,
658 pci_ht_map_msi(pcib
, *addr
);
663 * Try to read the bus number of a host-PCI bridge using appropriate config
667 host_pcib_get_busno(pci_read_config_fn read_config
, int bus
, int slot
, int func
,
672 id
= read_config(bus
, slot
, func
, PCIR_DEVVENDOR
, 4);
673 if (id
== 0xffffffff)
679 /* XXX This is a guess */
680 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
684 /* Intel 82454KX/GX (Orion) */
685 *busnum
= read_config(bus
, slot
, func
, 0x4a, 1);
689 * For the 450nx chipset, there is a whole bundle of
690 * things pretending to be host bridges. The MIOC will
691 * be seen first and isn't really a pci bridge (the
692 * actual busses are attached to the PXB's). We need to
693 * read the registers of the MIOC to figure out the
694 * bus numbers for the PXB channels.
696 * Since the MIOC doesn't have a pci bus attached, we
697 * pretend it wasn't there.
703 /* Intel 82454NX PXB#0, Bus#A */
704 *busnum
= read_config(bus
, 0x10, func
, 0xd0, 1);
707 /* Intel 82454NX PXB#0, Bus#B */
708 *busnum
= read_config(bus
, 0x10, func
, 0xd1, 1) + 1;
711 /* Intel 82454NX PXB#1, Bus#A */
712 *busnum
= read_config(bus
, 0x10, func
, 0xd3, 1);
715 /* Intel 82454NX PXB#1, Bus#B */
716 *busnum
= read_config(bus
, 0x10, func
, 0xd4, 1) + 1;
721 /* ServerWorks -- vendor 0x1166 */
733 *busnum
= read_config(bus
, slot
, func
, 0x44, 1);
736 /* Compaq/HP -- vendor 0x0e11 */
738 *busnum
= read_config(bus
, slot
, func
, 0xc8, 1);
741 /* Don't know how to read bus number. */