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ext2fs - A few bug fixes and syntax adjustments.
[dragonfly.git] / sys / dev / atm / en / midway.c
blobbc6e14bca5f73ea97cf3195905962d66a802e6ea
1 /* $NetBSD: midway.c,v 1.30 1997/09/29 17:40:38 chuck Exp $ */
2 /* (sync'd to midway.c 1.68) */
3
4 /*
5 *
6 * Copyright (c) 1996 Charles D. Cranor and Washington University.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Charles D. Cranor and
20 * Washington University.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: src/sys/dev/en/midway.c,v 1.19.2.1 2003/01/23 21:06:42 sam Exp $
36 * $DragonFly: src/sys/dev/atm/en/midway.c,v 1.24 2008/03/01 22:03:13 swildner Exp $
37 */
38
39 /*
40 *
41 * m i d w a y . c e n i 1 5 5 d r i v e r
42 *
43 * author: Chuck Cranor <chuck@ccrc.wustl.edu>
44 * started: spring, 1996 (written from scratch).
45 *
46 * notes from the author:
47 * Extra special thanks go to Werner Almesberger, EPFL LRC. Werner's
48 * ENI driver was especially useful in figuring out how this card works.
49 * I would also like to thank Werner for promptly answering email and being
50 * generally helpful.
51 */
52
53 #undef EN_DEBUG
54 #undef EN_DEBUG_RANGE /* check ranges on en_read/en_write's? */
55 #define EN_MBUF_OPT /* try and put more stuff in mbuf? */
56 #define EN_DIAG
57 #define EN_STAT
58 #ifndef EN_DMA
59 #define EN_DMA 1 /* use dma? */
60 #endif
61 #define EN_NOTXDMA 0 /* hook to disable tx dma only */
62 #define EN_NORXDMA 0 /* hook to disable rx dma only */
63 #define EN_DDBHOOK 1 /* compile in ddb functions */
64 #if defined(MIDWAY_ADPONLY)
65 #define EN_ENIDMAFIX 0 /* no ENI cards to worry about */
66 #else
67 #define EN_ENIDMAFIX 1 /* avoid byte DMA on the ENI card (see below) */
68 #endif
69
70 /*
71 * note on EN_ENIDMAFIX: the byte aligner on the ENI version of the card
72 * appears to be broken. it works just fine if there is no load... however
73 * when the card is loaded the data get corrupted. to see this, one only
74 * has to use "telnet" over ATM. do the following command in "telnet":
75 * cat /usr/share/misc/termcap
76 * "telnet" seems to generate lots of 1023 byte mbufs (which make great
77 * use of the byte aligner). watch "netstat -s" for checksum errors.
78 *
79 * I further tested this by adding a function that compared the transmit
80 * data on the card's SRAM with the data in the mbuf chain _after_ the
81 * "transmit DMA complete" interrupt. using the "telnet" test I got data
82 * mismatches where the byte-aligned data should have been. using ddb
83 * and en_dumpmem() I verified that the DTQs fed into the card were
84 * absolutely correct. thus, we are forced to concluded that the ENI
85 * hardware is buggy. note that the Adaptec version of the card works
86 * just fine with byte DMA.
87 *
88 * bottom line: we set EN_ENIDMAFIX to 1 to avoid byte DMAs on the ENI
89 * card.
90 */
91
92 #if defined(DIAGNOSTIC) && !defined(EN_DIAG)
93 #define EN_DIAG /* link in with master DIAG option */
94 #endif
95 #ifdef EN_STAT
96 #define EN_COUNT(X) (X)++
97 #else
98 #define EN_COUNT(X) /* nothing */
99 #endif
100
101 #ifdef EN_DEBUG
102 #undef EN_DDBHOOK
103 #define EN_DDBHOOK 1
104 #define STATIC /* nothing */
105 #define INLINE /* nothing */
106 #else /* EN_DEBUG */
107 #define STATIC static
108 #define INLINE __inline
109 #endif /* EN_DEBUG */
110
111 #include "use_en.h" /* XXX for midwayvar.h's NEN */
112 #include "opt_inet.h"
113 #include "opt_natm.h"
114 #include "opt_ddb.h"
115 /* enable DDBHOOK when DDB is available */
116 #undef EN_DDBHOOK
117 #ifdef DDB
118 #define EN_DDBHOOK 1
119 #endif
120
121 #include <sys/param.h>
122 #include <sys/systm.h>
123 #include <sys/queue.h>
124 #include <sys/sockio.h>
125 #include <sys/mbuf.h>
126 #include <sys/socket.h>
127 #include <sys/proc.h>
128 #include <sys/thread2.h>
129
130 #include <net/if.h>
131 #include <net/if_atm.h>
132
133 #include <vm/vm.h>
134
135 #if defined(INET) || defined(INET6)
136 #include <netinet/in.h>
137 #include <netinet/if_atm.h>
138 #endif
139
140 #ifdef NATM
141 #include <netproto/natm/natm.h>
142 #endif
143
144 #include "midwayreg.h"
145 #include "midwayvar.h"
146 #include <vm/pmap.h> /* for vtophys proto */
147
148 #ifndef IFF_NOTRAILERS
149 #define IFF_NOTRAILERS 0
150 #endif
151
152 #include <net/bpf.h>
153 #define BPFATTACH(ifp, dlt, hlen) bpfattach((ifp), (dlt), (hlen))
154
155 /*
156 * params
157 */
158
159 #ifndef EN_TXHIWAT
160 #define EN_TXHIWAT (64*1024) /* max 64 KB waiting to be DMAd out */
161 #endif
162
163 #ifndef EN_MINDMA
164 #define EN_MINDMA 32 /* don't DMA anything less than this (bytes) */
165 #endif
166
167 #define RX_NONE 0xffff /* recv VC not in use */
168
169 #define EN_OBHDR ATM_PH_DRIVER7 /* TBD in first mbuf ! */
170 #define EN_OBTRL ATM_PH_DRIVER8 /* PDU trailier in last mbuf ! */
171
172 #define ENOTHER_FREE 0x01 /* free rxslot */
173 #define ENOTHER_DRAIN 0x02 /* almost free (drain DRQ dma) */
174 #define ENOTHER_RAW 0x04 /* 'raw' access (aka boodi mode) */
175 #define ENOTHER_SWSL 0x08 /* in software service list */
176
177 static int en_dma = EN_DMA; /* use DMA (switch off for dbg) */
178
179 /*
180 * autoconfig attachments
181 */
182
183 struct cfdriver en_cd = {
184 0, "en", DV_IFNET,
185 };
186
187 /*
188 * local structures
189 */
190
191 /*
192 * params to en_txlaunch() function
193 */
194
195 struct en_launch {
196 u_int32_t tbd1; /* TBD 1 */
197 u_int32_t tbd2; /* TBD 2 */
198 u_int32_t pdu1; /* PDU 1 (aal5) */
199 int nodma; /* don't use DMA */
200 int need; /* total space we need (pad out if less data) */
201 int mlen; /* length of mbuf (for dtq) */
202 struct mbuf *t; /* data */
203 u_int32_t aal; /* aal code */
204 u_int32_t atm_vci; /* vci */
205 u_int8_t atm_flags; /* flags */
206 };
207
208
209 /*
210 * dma table (index by # of words)
211 *
212 * plan A: use WMAYBE (obsolete)
213 * plan B: avoid WMAYBE
214 */
215
216 struct en_dmatab {
217 u_int8_t bcode; /* code */
218 u_int8_t divshift; /* byte divisor */
219 };
220
221 static struct en_dmatab en_dma_planB[] = {
222 { 0, 0 }, /* 0 */ { MIDDMA_WORD, 2}, /* 1 */
223 { MIDDMA_2WORD, 3}, /* 2 */ { MIDDMA_WORD, 2}, /* 3 */
224 { MIDDMA_4WORD, 4}, /* 4 */ { MIDDMA_WORD, 2}, /* 5 */
225 { MIDDMA_2WORD, 3}, /* 6 */ { MIDDMA_WORD, 2}, /* 7 */
226 { MIDDMA_8WORD, 5}, /* 8 */ { MIDDMA_WORD, 2}, /* 9 */
227 { MIDDMA_2WORD, 3}, /* 10 */ { MIDDMA_WORD, 2}, /* 11 */
228 { MIDDMA_4WORD, 4}, /* 12 */ { MIDDMA_WORD, 2}, /* 13 */
229 { MIDDMA_2WORD, 3}, /* 14 */ { MIDDMA_WORD, 2}, /* 15 */
230 { MIDDMA_16WORD, 6}, /* 16 */
231 };
232
233 static struct en_dmatab *en_dmaplan = en_dma_planB;
234
235 /*
236 * prototypes
237 */
238
239 STATIC INLINE int en_b2sz (int) __attribute__ ((unused));
240 #ifdef EN_DDBHOOK
241 int en_dump (int,int);
242 int en_dumpmem (int,int,int);
243 #endif
244 STATIC void en_dmaprobe (struct en_softc *);
245 STATIC int en_dmaprobe_doit (struct en_softc *, u_int8_t *,
246 u_int8_t *, int);
247 STATIC INLINE int en_dqneed (struct en_softc *, caddr_t, u_int,
248 u_int) __attribute__ ((unused));
249 STATIC void en_init (struct en_softc *);
250 STATIC int en_ioctl (struct ifnet *, EN_IOCTL_CMDT, caddr_t,
251 struct ucred *);
252 STATIC INLINE int en_k2sz (int) __attribute__ ((unused));
253 STATIC void en_loadvc (struct en_softc *, int);
254 STATIC int en_mfix (struct en_softc *, struct mbuf **,
255 struct mbuf *);
256 STATIC INLINE struct mbuf *en_mget (struct en_softc *, u_int,
257 u_int *) __attribute__ ((unused));
258 STATIC INLINE u_int32_t en_read (struct en_softc *,
259 u_int32_t) __attribute__ ((unused));
260 STATIC int en_rxctl (struct en_softc *, struct atm_pseudoioctl *,
261 int);
262 STATIC void en_txdma (struct en_softc *, int);
263 STATIC void en_txlaunch (struct en_softc *, int,
264 struct en_launch *);
265 STATIC void en_service (struct en_softc *);
266 STATIC void en_start (struct ifnet *);
267 STATIC INLINE int en_sz2b (int) __attribute__ ((unused));
268 STATIC INLINE void en_write (struct en_softc *, u_int32_t,
269 u_int32_t) __attribute__ ((unused));
270
271 /*
272 * macros/inline
273 */
274
275 /*
276 * raw read/write macros
277 */
278
279 #define EN_READDAT(SC,R) en_read(SC,R)
280 #define EN_WRITEDAT(SC,R,V) en_write(SC,R,V)
281
282 /*
283 * cooked read/write macros
284 */
285
286 #define EN_READ(SC,R) ntohl(en_read(SC,R))
287 #define EN_WRITE(SC,R,V) en_write(SC,R, htonl(V))
288
289 #define EN_WRAPADD(START,STOP,CUR,VAL) { \
290 (CUR) = (CUR) + (VAL); \
291 if ((CUR) >= (STOP)) \
292 (CUR) = (START) + ((CUR) - (STOP)); \
293 }
294
295 #define WORD_IDX(START, X) (((X) - (START)) / sizeof(u_int32_t))
296
297 /* we store sc->dtq and sc->drq data in the following format... */
298 #define EN_DQ_MK(SLOT,LEN) (((SLOT) << 20)|(LEN)|(0x80000))
299 /* the 0x80000 ensures we != 0 */
300 #define EN_DQ_SLOT(X) ((X) >> 20)
301 #define EN_DQ_LEN(X) ((X) & 0x3ffff)
302
303 /* format of DTQ/DRQ word 1 differs between ENI and ADP */
304 #if defined(MIDWAY_ENIONLY)
305
306 #define MID_MK_TXQ(SC,CNT,CHAN,END,BCODE) \
307 EN_WRITE((SC), (SC)->dtq_us, \
308 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (BCODE)));
309
310 #define MID_MK_RXQ(SC,CNT,VCI,END,BCODE) \
311 EN_WRITE((SC), (SC)->drq_us, \
312 MID_MK_RXQ_ENI((CNT), (VCI), (END), (BCODE)));
313
314 #elif defined(MIDWAY_ADPONLY)
315
316 #define MID_MK_TXQ(SC,CNT,CHAN,END,JK) \
317 EN_WRITE((SC), (SC)->dtq_us, \
318 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK)));
319
320 #define MID_MK_RXQ(SC,CNT,VCI,END,JK) \
321 EN_WRITE((SC), (SC)->drq_us, \
322 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK)));
323
324 #else
325
326 #define MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE) { \
327 if ((SC)->is_adaptec) \
328 EN_WRITE((SC), (SC)->dtq_us, \
329 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK_OR_BCODE))); \
330 else \
331 EN_WRITE((SC), (SC)->dtq_us, \
332 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (JK_OR_BCODE))); \
333 }
334
335 #define MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE) { \
336 if ((SC)->is_adaptec) \
337 EN_WRITE((SC), (SC)->drq_us, \
338 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK_OR_BCODE))); \
339 else \
340 EN_WRITE((SC), (SC)->drq_us, \
341 MID_MK_RXQ_ENI((CNT), (VCI), (END), (JK_OR_BCODE))); \
342 }
343
344 #endif
345
346 /* add an item to the DTQ */
347 #define EN_DTQADD(SC,CNT,CHAN,JK_OR_BCODE,ADDR,LEN,END) { \
348 if (END) \
349 (SC)->dtq[MID_DTQ_A2REG((SC)->dtq_us)] = EN_DQ_MK(CHAN,LEN); \
350 MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE); \
351 (SC)->dtq_us += 4; \
352 EN_WRITE((SC), (SC)->dtq_us, (ADDR)); \
353 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, (SC)->dtq_us, 4); \
354 (SC)->dtq_free--; \
355 if (END) \
356 EN_WRITE((SC), MID_DMA_WRTX, MID_DTQ_A2REG((SC)->dtq_us)); \
357 }
358
359 /* DRQ add macro */
360 #define EN_DRQADD(SC,CNT,VCI,JK_OR_BCODE,ADDR,LEN,SLOT,END) { \
361 if (END) \
362 (SC)->drq[MID_DRQ_A2REG((SC)->drq_us)] = EN_DQ_MK(SLOT,LEN); \
363 MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE); \
364 (SC)->drq_us += 4; \
365 EN_WRITE((SC), (SC)->drq_us, (ADDR)); \
366 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, (SC)->drq_us, 4); \
367 (SC)->drq_free--; \
368 if (END) \
369 EN_WRITE((SC), MID_DMA_WRRX, MID_DRQ_A2REG((SC)->drq_us)); \
370 }
371
372 /*
373 * the driver code
374 *
375 * the code is arranged in a specific way:
376 * [1] short/inline functions
377 * [2] autoconfig stuff
378 * [3] ioctl stuff
379 * [4] reset -> init -> trasmit -> intr -> receive functions
380 *
381 */
382
383 /***********************************************************************/
384
385 /*
386 * en_read: read a word from the card. this is the only function
387 * that reads from the card.
388 */
389
390 STATIC INLINE u_int32_t
391 en_read(struct en_softc *sc, u_int32_t r)
392 {
393 #ifdef EN_DEBUG_RANGE
394 if (r > MID_MAXOFF || (r % 4))
395 panic("en_read out of range, r=0x%x", r);
396 #endif
397
398 return(bus_space_read_4(sc->en_memt, sc->en_base, r));
399 }
400
401 /*
402 * en_write: write a word to the card. this is the only function that
403 * writes to the card.
404 */
405
406 STATIC INLINE void
407 en_write(struct en_softc *sc, u_int32_t r, u_int32_t v)
408 {
409 #ifdef EN_DEBUG_RANGE
410 if (r > MID_MAXOFF || (r % 4))
411 panic("en_write out of range, r=0x%x", r);
412 #endif
413
414 bus_space_write_4(sc->en_memt, sc->en_base, r, v);
415 }
416
417 /*
418 * en_k2sz: convert KBytes to a size parameter (a log2)
419 */
420
421 STATIC INLINE int
422 en_k2sz(int k)
423 {
424 switch(k) {
425 case 1: return(0);
426 case 2: return(1);
427 case 4: return(2);
428 case 8: return(3);
429 case 16: return(4);
430 case 32: return(5);
431 case 64: return(6);
432 case 128: return(7);
433 default: panic("en_k2sz");
434 }
435 return(0);
436 }
437 #define en_log2(X) en_k2sz(X)
438
439
440 /*
441 * en_b2sz: convert a DMA burst code to its byte size
442 */
443
444 STATIC INLINE int
445 en_b2sz(int b)
446 {
447 switch (b) {
448 case MIDDMA_WORD: return(1*4);
449 case MIDDMA_2WMAYBE:
450 case MIDDMA_2WORD: return(2*4);
451 case MIDDMA_4WMAYBE:
452 case MIDDMA_4WORD: return(4*4);
453 case MIDDMA_8WMAYBE:
454 case MIDDMA_8WORD: return(8*4);
455 case MIDDMA_16WMAYBE:
456 case MIDDMA_16WORD: return(16*4);
457 default: panic("en_b2sz");
458 }
459 return(0);
460 }
461
462
463 /*
464 * en_sz2b: convert a burst size (bytes) to DMA burst code
465 */
466
467 STATIC INLINE int
468 en_sz2b(int sz)
469 {
470 switch (sz) {
471 case 1*4: return(MIDDMA_WORD);
472 case 2*4: return(MIDDMA_2WORD);
473 case 4*4: return(MIDDMA_4WORD);
474 case 8*4: return(MIDDMA_8WORD);
475 case 16*4: return(MIDDMA_16WORD);
476 default: panic("en_sz2b");
477 }
478 return(0);
479 }
480
481
482 /*
483 * en_dqneed: calculate number of DTQ/DRQ's needed for a buffer
484 */
485
486 STATIC INLINE int
487 en_dqneed(struct en_softc *sc, caddr_t data, u_int len, u_int tx)
488 {
489 int result, needalign, sz;
490
491 #if !defined(MIDWAY_ENIONLY)
492 #if !defined(MIDWAY_ADPONLY)
493 if (sc->is_adaptec)
494 #endif /* !MIDWAY_ADPONLY */
495 return(1); /* adaptec can DMA anything in one go */
496 #endif
497
498 #if !defined(MIDWAY_ADPONLY)
499 result = 0;
500 if (len < EN_MINDMA) {
501 if (!tx) /* XXX: conservative */
502 return(1); /* will copy/DMA_JK */
503 }
504
505 if (tx) { /* byte burst? */
506 needalign = (((uintptr_t) (void *) data) % sizeof(u_int32_t));
507 if (needalign) {
508 result++;
509 sz = min(len, sizeof(u_int32_t) - needalign);
510 len -= sz;
511 data += sz;
512 }
513 }
514
515 if (sc->alburst && len) {
516 needalign = (((uintptr_t) (void *) data) & sc->bestburstmask);
517 if (needalign) {
518 result++; /* alburst */
519 sz = min(len, sc->bestburstlen - needalign);
520 len -= sz;
521 }
522 }
523
524 if (len >= sc->bestburstlen) {
525 sz = len / sc->bestburstlen;
526 sz = sz * sc->bestburstlen;
527 len -= sz;
528 result++; /* best shot */
529 }
530
531 if (len) {
532 result++; /* clean up */
533 if (tx && (len % sizeof(u_int32_t)) != 0)
534 result++; /* byte cleanup */
535 }
536
537 return(result);
538 #endif /* !MIDWAY_ADPONLY */
539 }
540
541
542 /*
543 * en_mget: get an mbuf chain that can hold totlen bytes and return it
544 * (for recv) [based on am7990_get from if_le and ieget from if_ie]
545 * after this call the sum of all the m_len's in the chain will be totlen.
546 */
547
548 STATIC INLINE struct mbuf *
549 en_mget(struct en_softc *sc, u_int totlen, u_int *drqneed)
550 {
551 struct mbuf *m;
552 struct mbuf *top, **mp;
553 *drqneed = 0;
554
555 MGETHDR(m, MB_DONTWAIT, MT_DATA);
556 if (m == NULL)
557 return(NULL);
558 m->m_pkthdr.rcvif = &sc->enif;
559 m->m_pkthdr.len = totlen;
560 m->m_len = MHLEN;
561 top = NULL;
562 mp = &top;
563
564 /* if (top != NULL) then we've already got 1 mbuf on the chain */
565 while (totlen > 0) {
566 if (top) {
567 MGET(m, MB_DONTWAIT, MT_DATA);
568 if (!m) {
569 m_freem(top);
570 return(NULL); /* out of mbufs */
571 }
572 m->m_len = MLEN;
573 }
574 if (totlen >= MINCLSIZE) {
575 MCLGET(m, MB_DONTWAIT);
576 if ((m->m_flags & M_EXT) == 0) {
577 m_free(m);
578 m_freem(top);
579 return(NULL); /* out of mbuf clusters */
580 }
581 m->m_len = MCLBYTES;
582 }
583 m->m_len = min(totlen, m->m_len);
584 totlen -= m->m_len;
585 *mp = m;
586 mp = &m->m_next;
587
588 *drqneed += en_dqneed(sc, m->m_data, m->m_len, 0);
589
590 }
591 return(top);
592 }
593
594 /***********************************************************************/
595
596 /*
597 * autoconfig stuff
598 */
599
600 void
601 en_attach(struct en_softc *sc)
602 {
603 struct ifnet *ifp = &sc->enif;
604 int sz;
605 u_int32_t reg, lcv, check, ptr, sav, midvloc;
606
607 /*
608 * probe card to determine memory size. the stupid ENI card always
609 * reports to PCI that it needs 4MB of space (2MB regs and 2MB RAM).
610 * if it has less than 2MB RAM the addresses wrap in the RAM address space.
611 * (i.e. on a 512KB card addresses 0x3ffffc, 0x37fffc, and 0x2ffffc
612 * are aliases for 0x27fffc [note that RAM starts at offset 0x200000]).
613 */
614
615 if (sc->en_busreset)
616 sc->en_busreset(sc);
617 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
618 for (lcv = MID_PROBEOFF; lcv <= MID_MAXOFF ; lcv += MID_PROBSIZE) {
619 EN_WRITE(sc, lcv, lcv); /* data[address] = address */
620 for (check = MID_PROBEOFF ; check < lcv ; check += MID_PROBSIZE) {
621 reg = EN_READ(sc, check);
622 if (reg != check) { /* found an alias! */
623 goto done_probe; /* and quit */
624 }
625 }
626 }
627 done_probe:
628 lcv -= MID_PROBSIZE; /* take one step back */
629 sc->en_obmemsz = (lcv + 4) - MID_RAMOFF;
630
631 /*
632 * determine the largest DMA burst supported
633 */
634
635 en_dmaprobe(sc);
636
637 /*
638 * "hello world"
639 */
640
641 if (sc->en_busreset)
642 sc->en_busreset(sc);
643 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
644 for (lcv = MID_RAMOFF ; lcv < MID_RAMOFF + sc->en_obmemsz ; lcv += 4)
645 EN_WRITE(sc, lcv, 0); /* zero memory */
646
647 reg = EN_READ(sc, MID_RESID);
648
649 kprintf("%s: ATM midway v%d, board IDs %d.%d, %s%s%s, %ldKB on-board RAM\n",
650 sc->sc_dev.dv_xname, MID_VER(reg), MID_MID(reg), MID_DID(reg),
651 (MID_IS_SABRE(reg)) ? "sabre controller, " : "",
652 (MID_IS_SUNI(reg)) ? "SUNI" : "Utopia",
653 (!MID_IS_SUNI(reg) && MID_IS_UPIPE(reg)) ? " (pipelined)" : "",
654 (long)(sc->en_obmemsz / 1024));
655
656 if (sc->is_adaptec) {
657 if (sc->bestburstlen == 64 && sc->alburst == 0)
658 kprintf("%s: passed 64 byte DMA test\n", sc->sc_dev.dv_xname);
659 else
660 kprintf("%s: FAILED DMA TEST: burst=%d, alburst=%d\n",
661 sc->sc_dev.dv_xname, sc->bestburstlen, sc->alburst);
662 } else {
663 kprintf("%s: maximum DMA burst length = %d bytes%s\n", sc->sc_dev.dv_xname,
664 sc->bestburstlen, (sc->alburst) ? " (must align)" : "");
665 }
666
667 /*
668 * link into network subsystem and prepare card
669 */
670
671 sc->enif.if_softc = sc;
672 ifp->if_flags = IFF_SIMPLEX|IFF_NOTRAILERS;
673 ifp->if_ioctl = en_ioctl;
674 ifp->if_output = atm_output;
675 ifp->if_start = en_start;
676
677 /*
678 * init softc
679 */
680
681 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
682 sc->rxvc2slot[lcv] = RX_NONE;
683 sc->txspeed[lcv] = 0; /* full */
684 sc->txvc2slot[lcv] = 0; /* full speed == slot 0 */
685 }
686
687 sz = sc->en_obmemsz - (MID_BUFOFF - MID_RAMOFF);
688 ptr = sav = MID_BUFOFF;
689 ptr = roundup(ptr, EN_TXSZ * 1024); /* align */
690 sz = sz - (ptr - sav);
691 if (EN_TXSZ*1024 * EN_NTX > sz) {
692 kprintf("%s: EN_NTX/EN_TXSZ too big\n", sc->sc_dev.dv_xname);
693 return;
694 }
695 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
696 sc->txslot[lcv].mbsize = 0;
697 sc->txslot[lcv].start = ptr;
698 ptr += (EN_TXSZ * 1024);
699 sz -= (EN_TXSZ * 1024);
700 sc->txslot[lcv].stop = ptr;
701 sc->txslot[lcv].nref = 0;
702 bzero(&sc->txslot[lcv].indma, sizeof(sc->txslot[lcv].indma));
703 bzero(&sc->txslot[lcv].q, sizeof(sc->txslot[lcv].q));
704 #ifdef EN_DEBUG
705 kprintf("%s: tx%d: start 0x%x, stop 0x%x\n", sc->sc_dev.dv_xname, lcv,
706 sc->txslot[lcv].start, sc->txslot[lcv].stop);
707 #endif
708 }
709
710 sav = ptr;
711 ptr = roundup(ptr, EN_RXSZ * 1024); /* align */
712 sz = sz - (ptr - sav);
713 sc->en_nrx = sz / (EN_RXSZ * 1024);
714 if (sc->en_nrx <= 0) {
715 kprintf("%s: EN_NTX/EN_TXSZ/EN_RXSZ too big\n", sc->sc_dev.dv_xname);
716 return;
717 }
718
719 /*
720 * ensure that there is always one VC slot on the service list free
721 * so that we can tell the difference between a full and empty list.
722 */
723 if (sc->en_nrx >= MID_N_VC)
724 sc->en_nrx = MID_N_VC - 1;
725
726 for (lcv = 0 ; lcv < sc->en_nrx ; lcv++) {
727 sc->rxslot[lcv].rxhand = NULL;
728 sc->rxslot[lcv].oth_flags = ENOTHER_FREE;
729 bzero(&sc->rxslot[lcv].indma, sizeof(sc->rxslot[lcv].indma));
730 bzero(&sc->rxslot[lcv].q, sizeof(sc->rxslot[lcv].q));
731 midvloc = sc->rxslot[lcv].start = ptr;
732 ptr += (EN_RXSZ * 1024);
733 sz -= (EN_RXSZ * 1024);
734 sc->rxslot[lcv].stop = ptr;
735 midvloc = midvloc - MID_RAMOFF;
736 midvloc = (midvloc & ~((EN_RXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
737 midvloc = midvloc >> MIDV_LOCTOPSHFT; /* we only want the top 11 bits */
738 midvloc = (midvloc & MIDV_LOCMASK) << MIDV_LOCSHIFT;
739 sc->rxslot[lcv].mode = midvloc |
740 (en_k2sz(EN_RXSZ) << MIDV_SZSHIFT) | MIDV_TRASH;
741
742 #ifdef EN_DEBUG
743 kprintf("%s: rx%d: start 0x%x, stop 0x%x, mode 0x%x\n", sc->sc_dev.dv_xname,
744 lcv, sc->rxslot[lcv].start, sc->rxslot[lcv].stop, sc->rxslot[lcv].mode);
745 #endif
746 }
747
748 #ifdef EN_STAT
749 sc->vtrash = sc->otrash = sc->mfix = sc->txmbovr = sc->dmaovr = 0;
750 sc->txoutspace = sc->txdtqout = sc->launch = sc->lheader = sc->ltail = 0;
751 sc->hwpull = sc->swadd = sc->rxqnotus = sc->rxqus = sc->rxoutboth = 0;
752 sc->rxdrqout = sc->ttrash = sc->rxmbufout = sc->mfixfail = 0;
753 sc->headbyte = sc->tailbyte = sc->tailflush = 0;
754 #endif
755 sc->need_drqs = sc->need_dtqs = 0;
756
757 kprintf("%s: %d %dKB receive buffers, %d %dKB transmit buffers allocated\n",
758 sc->sc_dev.dv_xname, sc->en_nrx, EN_RXSZ, EN_NTX, EN_TXSZ);
759
760 kprintf("%s: End Station Identifier (mac address) %6D\n",
761 sc->sc_dev.dv_xname, sc->macaddr, ":");
762
763 /*
764 * final commit
765 */
766 atm_ifattach(ifp, NULL);
767 }
768
769
770 /*
771 * en_dmaprobe: helper function for en_attach.
772 *
773 * see how the card handles DMA by running a few DMA tests. we need
774 * to figure out the largest number of bytes we can DMA in one burst
775 * ("bestburstlen"), and if the starting address for a burst needs to
776 * be aligned on any sort of boundary or not ("alburst").
777 *
778 * typical findings:
779 * sparc1: bestburstlen=4, alburst=0 (ick, broken DMA!)
780 * sparc2: bestburstlen=64, alburst=1
781 * p166: bestburstlen=64, alburst=0
782 */
783
784 #define NBURSTS 3 /* number of bursts to use for dmaprobe */
785 #define BOUNDARY 1024 /* test misaligned dma crossing the bounday.
786 should be n * 64. at least 64*(NBURSTS+1).
787 dell P6 with EDO DRAM has 1K bounday problem */
788
789 STATIC void
790 en_dmaprobe(struct en_softc *sc)
791 {
792 #ifdef NBURSTS
793 /* be careful. kernel stack is only 8K */
794 u_int8_t buffer[BOUNDARY * 2 + 64 * (NBURSTS + 1)];
795 #else
796 u_int32_t srcbuf[64], dstbuf[64];
797 #endif
798 u_int8_t *sp, *dp;
799 int bestalgn, bestnotalgn, lcv, try;
800
801 sc->alburst = 0;
802
803 #ifdef NBURSTS
804 /* setup src and dst buf at the end of the boundary */
805 sp = (u_int8_t *)roundup((uintptr_t)(void *)buffer, 64);
806 while (((uintptr_t)(void *)sp & (BOUNDARY - 1)) != (BOUNDARY - 64))
807 sp += 64;
808 dp = sp + BOUNDARY;
809
810 /*
811 * we can't dma across page boundary so that, if buf is at a page
812 * boundary, move it to the next page. but still either src or dst
813 * will be at the boundary, which should be ok.
814 */
815 if ((((uintptr_t)(void *)sp + 64) & PAGE_MASK) == 0)
816 sp += 64;
817 if ((((uintptr_t)(void *)dp + 64) & PAGE_MASK) == 0)
818 dp += 64;
819 #else /* !NBURSTS */
820 sp = (u_int8_t *) srcbuf;
821 while ((((unsigned long) sp) % MIDDMA_MAXBURST) != 0)
822 sp += 4;
823 dp = (u_int8_t *) dstbuf;
824 while ((((unsigned long) dp) % MIDDMA_MAXBURST) != 0)
825 dp += 4;
826 #endif /* !NBURSTS */
827
828 bestalgn = bestnotalgn = en_dmaprobe_doit(sc, sp, dp, 0);
829
830 for (lcv = 4 ; lcv < MIDDMA_MAXBURST ; lcv += 4) {
831 try = en_dmaprobe_doit(sc, sp+lcv, dp+lcv, 0);
832 #ifdef NBURSTS
833 if (try < bestnotalgn) {
834 bestnotalgn = try;
835 break;
836 }
837 #else
838 if (try < bestnotalgn)
839 bestnotalgn = try;
840 #endif
841 }
842
843 if (bestalgn != bestnotalgn) /* need bursts aligned */
844 sc->alburst = 1;
845
846 sc->bestburstlen = bestalgn;
847 sc->bestburstshift = en_log2(bestalgn);
848 sc->bestburstmask = sc->bestburstlen - 1; /* must be power of 2 */
849 sc->bestburstcode = en_sz2b(bestalgn);
850
851 /*
852 * correct pci chipsets should be able to handle misaligned-64-byte DMA.
853 * but there are too many broken chipsets around. we try to work around
854 * by finding the best workable dma size, but still some broken machines
855 * exhibit the problem later. so warn it here.
856 */
857 if (bestalgn != 64 || sc->alburst != 0) {
858 kprintf("%s: WARNING: DMA test detects a broken PCI chipset!\n",
859 sc->sc_dev.dv_xname);
860 kprintf(" trying to work around the problem... but if this doesn't\n");
861 kprintf(" work for you, you'd better switch to a newer motherboard.\n");
862 }
863 return;
864 }
865
866
867 /*
868 * en_dmaprobe_doit: do actual testing
869 */
870
871 static int
872 en_dmaprobe_doit(struct en_softc *sc, u_int8_t *sp, u_int8_t *dp, int wmtry)
873 {
874 int lcv, retval = 4, cnt, count;
875 u_int32_t reg, bcode, midvloc;
876
877 /*
878 * set up a 1k buffer at MID_BUFOFF
879 */
880
881 if (sc->en_busreset)
882 sc->en_busreset(sc);
883 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
884
885 midvloc = ((MID_BUFOFF - MID_RAMOFF) / sizeof(u_int32_t)) >> MIDV_LOCTOPSHFT;
886 EN_WRITE(sc, MIDX_PLACE(0), MIDX_MKPLACE(en_k2sz(1), midvloc));
887 EN_WRITE(sc, MID_VC(0), (midvloc << MIDV_LOCSHIFT)
888 | (en_k2sz(1) << MIDV_SZSHIFT) | MIDV_TRASH);
889 EN_WRITE(sc, MID_DST_RP(0), 0);
890 EN_WRITE(sc, MID_WP_ST_CNT(0), 0);
891
892 #ifdef NBURSTS
893 for (lcv = 0 ; lcv < 64*NBURSTS; lcv++) /* set up sample data */
894 #else
895 for (lcv = 0 ; lcv < 68 ; lcv++) /* set up sample data */
896 #endif
897 sp[lcv] = lcv+1;
898 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* enable DMA (only) */
899
900 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
901 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
902
903 /*
904 * try it now . . . DMA it out, then DMA it back in and compare
905 *
906 * note: in order to get the dma stuff to reverse directions it wants
907 * the "end" flag set! since we are not dma'ing valid data we may
908 * get an ident mismatch interrupt (which we will ignore).
909 *
910 * note: we've got two different tests rolled up in the same loop
911 * if (wmtry)
912 * then we are doing a wmaybe test and wmtry is a byte count
913 * else we are doing a burst test
914 */
915
916 for (lcv = 8 ; lcv <= MIDDMA_MAXBURST ; lcv = lcv * 2) {
917
918 #ifdef EN_DEBUG
919 kprintf("DMA test lcv=%d, sp=0x%x, dp=0x%x, wmtry=%d\n",
920 lcv, sp, dp, wmtry);
921 #endif
922
923 /* zero SRAM and dest buffer */
924 for (cnt = 0 ; cnt < 1024; cnt += 4)
925 EN_WRITE(sc, MID_BUFOFF+cnt, 0); /* zero memory */
926 #ifdef NBURSTS
927 for (cnt = 0 ; cnt < 64*NBURSTS; cnt++)
928 #else
929 for (cnt = 0 ; cnt < 68 ; cnt++)
930 #endif
931 dp[cnt] = 0;
932
933 if (wmtry) {
934 count = (sc->bestburstlen - sizeof(u_int32_t)) / sizeof(u_int32_t);
935 bcode = en_dmaplan[count].bcode;
936 count = wmtry >> en_dmaplan[count].divshift;
937 } else {
938 bcode = en_sz2b(lcv);
939 count = 1;
940 }
941 #ifdef NBURSTS
942 /* build lcv-byte-DMA x NBURSTS */
943 if (sc->is_adaptec)
944 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
945 else
946 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
947 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
948 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
949 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip));
950 cnt = 1000;
951 while (EN_READ(sc, MID_DMA_RDTX) != MID_DTQ_A2REG(sc->dtq_chip)) {
952 DELAY(1);
953 cnt--;
954 if (cnt == 0) {
955 kprintf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
956 /*
957 kprintf(" alignment=0x%x, burst size=%d, dma addr reg=0x%x\n",
958 (u_long)sp & 63, lcv, EN_READ(sc, MID_DMA_ADDR));
959 */
960 return(retval); /* timeout, give up */
961 }
962 }
963 #else /* !NBURSTS */
964 if (sc->is_adaptec)
965 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv, 0, MID_DMA_END, 0));
966 else
967 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count, 0, MID_DMA_END, bcode));
968 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
969 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip+8));
970 cnt = 1000;
971 while (EN_READ(sc, MID_DMA_RDTX) == MID_DTQ_A2REG(sc->dtq_chip)) {
972 DELAY(1);
973 cnt--;
974 if (cnt == 0) {
975 kprintf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
976 return(retval); /* timeout, give up */
977 }
978 }
979 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
980 #endif /* !NBURSTS */
981 reg = EN_READ(sc, MID_INTACK);
982 if ((reg & MID_INT_DMA_TX) != MID_INT_DMA_TX) {
983 kprintf("%s: unexpected status in tx DMA test: 0x%x\n",
984 sc->sc_dev.dv_xname, reg);
985 return(retval);
986 }
987 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
988
989 /* "return to sender..." address is known ... */
990
991 #ifdef NBURSTS
992 /* build lcv-byte-DMA x NBURSTS */
993 if (sc->is_adaptec)
994 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
995 else
996 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
997 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
998 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
999 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1000 cnt = 1000;
1001 while (EN_READ(sc, MID_DMA_RDRX) != MID_DRQ_A2REG(sc->drq_chip)) {
1002 DELAY(1);
1003 cnt--;
1004 if (cnt == 0) {
1005 kprintf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1006 return(retval); /* timeout, give up */
1007 }
1008 }
1009 #else /* !NBURSTS */
1010 if (sc->is_adaptec)
1011 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv, 0, MID_DMA_END, 0));
1012 else
1013 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count, 0, MID_DMA_END, bcode));
1014 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1015 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip+8));
1016 cnt = 1000;
1017 while (EN_READ(sc, MID_DMA_RDRX) == MID_DRQ_A2REG(sc->drq_chip)) {
1018 DELAY(1);
1019 cnt--;
1020 if (cnt == 0) {
1021 kprintf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1022 return(retval); /* timeout, give up */
1023 }
1024 }
1025 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1026 #endif /* !NBURSTS */
1027 reg = EN_READ(sc, MID_INTACK);
1028 if ((reg & MID_INT_DMA_RX) != MID_INT_DMA_RX) {
1029 kprintf("%s: unexpected status in rx DMA test: 0x%x\n",
1030 sc->sc_dev.dv_xname, reg);
1031 return(retval);
1032 }
1033 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1034
1035 if (wmtry) {
1036 return(bcmp(sp, dp, wmtry)); /* wmtry always exits here, no looping */
1037 }
1038
1039 #ifdef NBURSTS
1040 if (bcmp(sp, dp, lcv * NBURSTS)) {
1041 /* kprintf("DMA test failed! lcv=%d, sp=0x%x, dp=0x%x\n", lcv, sp, dp); */
1042 return(retval); /* failed, use last value */
1043 }
1044 #else
1045 if (bcmp(sp, dp, lcv))
1046 return(retval); /* failed, use last value */
1047 #endif
1048
1049 retval = lcv;
1050
1051 }
1052 return(retval); /* studly 64 byte DMA present! oh baby!! */
1053 }
1054
1055 /***********************************************************************/
1056
1057 /*
1058 * en_ioctl: handle ioctl requests
1059 *
1060 * NOTE: if you add an ioctl to set txspeed, you should choose a new
1061 * TX channel/slot. Choose the one with the lowest sc->txslot[slot].nref
1062 * value, subtract one from sc->txslot[0].nref, add one to the
1063 * sc->txslot[slot].nref, set sc->txvc2slot[vci] = slot, and then set
1064 * txspeed[vci].
1065 */
1066
1067 STATIC int
1068 en_ioctl(struct ifnet *ifp, EN_IOCTL_CMDT cmd, caddr_t data, struct ucred *cr)
1069 {
1070 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1071 struct ifaddr *ifa = (struct ifaddr *) data;
1072 struct ifreq *ifr = (struct ifreq *) data;
1073 struct atm_pseudoioctl *api = (struct atm_pseudoioctl *)data;
1074 #ifdef NATM
1075 struct atm_rawioctl *ario = (struct atm_rawioctl *)data;
1076 int slot;
1077 #endif
1078 int error = 0;
1079
1080 crit_enter();
1081
1082 switch (cmd) {
1083 case SIOCATMENA: /* enable circuit for recv */
1084 error = en_rxctl(sc, api, 1);
1085 break;
1086
1087 case SIOCATMDIS: /* disable circuit for recv */
1088 error = en_rxctl(sc, api, 0);
1089 break;
1090
1091 #ifdef NATM
1092 case SIOCXRAWATM:
1093 if ((slot = sc->rxvc2slot[ario->npcb->npcb_vci]) == RX_NONE) {
1094 error = EINVAL;
1095 break;
1096 }
1097 if (ario->rawvalue > EN_RXSZ*1024)
1098 ario->rawvalue = EN_RXSZ*1024;
1099 if (ario->rawvalue) {
1100 sc->rxslot[slot].oth_flags |= ENOTHER_RAW;
1101 sc->rxslot[slot].raw_threshold = ario->rawvalue;
1102 } else {
1103 sc->rxslot[slot].oth_flags &= (~ENOTHER_RAW);
1104 sc->rxslot[slot].raw_threshold = 0;
1105 }
1106 #ifdef EN_DEBUG
1107 kprintf("%s: rxvci%d: turn %s raw (boodi) mode\n",
1108 sc->sc_dev.dv_xname, ario->npcb->npcb_vci,
1109 (ario->rawvalue) ? "on" : "off");
1110 #endif
1111 break;
1112 #endif
1113 case SIOCSIFADDR:
1114 ifp->if_flags |= IFF_UP;
1115 #if defined(INET) || defined(INET6)
1116 if (ifa->ifa_addr->sa_family == AF_INET
1117 || ifa->ifa_addr->sa_family == AF_INET6) {
1118 en_reset(sc);
1119 en_init(sc);
1120 ifa->ifa_rtrequest = atm_rtrequest; /* ??? */
1121 break;
1122 }
1123 #endif /* INET */
1124 /* what to do if not INET? */
1125 en_reset(sc);
1126 en_init(sc);
1127 break;
1128
1129 case SIOCGIFADDR:
1130 error = EINVAL;
1131 break;
1132
1133 case SIOCSIFFLAGS:
1134 error = EINVAL;
1135 break;
1136
1137 #if defined(SIOCSIFMTU) /* ??? copied from if_de */
1138 #if !defined(ifr_mtu)
1139 #define ifr_mtu ifr_metric
1140 #endif
1141 case SIOCSIFMTU:
1142 /*
1143 * Set the interface MTU.
1144 */
1145 #ifdef notsure
1146 if (ifr->ifr_mtu > ATMMTU) {
1147 error = EINVAL;
1148 break;
1149 }
1150 #endif
1151 ifp->if_mtu = ifr->ifr_mtu;
1152 /* XXXCDC: do we really need to reset on MTU size change? */
1153 en_reset(sc);
1154 en_init(sc);
1155 break;
1156 #endif /* SIOCSIFMTU */
1157
1158 default:
1159 error = EINVAL;
1160 break;
1161 }
1162 crit_exit();
1163 return error;
1164 }
1165
1166
1167 /*
1168 * en_rxctl: turn on and off VCs for recv.
1169 */
1170
1171 STATIC int
1172 en_rxctl(struct en_softc *sc, struct atm_pseudoioctl *pi, int on)
1173 {
1174 u_int vci, flags, slot;
1175 u_int32_t oldmode, newmode;
1176
1177 vci = ATM_PH_VCI(&pi->aph);
1178 flags = ATM_PH_FLAGS(&pi->aph);
1179
1180 #ifdef EN_DEBUG
1181 kprintf("%s: %s vpi=%d, vci=%d, flags=%d\n", sc->sc_dev.dv_xname,
1182 (on) ? "enable" : "disable", ATM_PH_VPI(&pi->aph), vci, flags);
1183 #endif
1184
1185 if (ATM_PH_VPI(&pi->aph) || vci >= MID_N_VC)
1186 return(EINVAL);
1187
1188 /*
1189 * turn on VCI!
1190 */
1191
1192 if (on) {
1193 if (sc->rxvc2slot[vci] != RX_NONE)
1194 return(EINVAL);
1195 for (slot = 0 ; slot < sc->en_nrx ; slot++)
1196 if (sc->rxslot[slot].oth_flags & ENOTHER_FREE)
1197 break;
1198 if (slot == sc->en_nrx)
1199 return(ENOSPC);
1200 sc->rxvc2slot[vci] = slot;
1201 sc->rxslot[slot].rxhand = NULL;
1202 oldmode = sc->rxslot[slot].mode;
1203 newmode = (flags & ATM_PH_AAL5) ? MIDV_AAL5 : MIDV_NOAAL;
1204 sc->rxslot[slot].mode = MIDV_SETMODE(oldmode, newmode);
1205 sc->rxslot[slot].atm_vci = vci;
1206 sc->rxslot[slot].atm_flags = flags;
1207 sc->rxslot[slot].oth_flags = 0;
1208 sc->rxslot[slot].rxhand = pi->rxhand;
1209 if (sc->rxslot[slot].indma.ifq_head || sc->rxslot[slot].q.ifq_head)
1210 panic("en_rxctl: left over mbufs on enable");
1211 sc->txspeed[vci] = 0; /* full speed to start */
1212 sc->txvc2slot[vci] = 0; /* init value */
1213 sc->txslot[0].nref++; /* bump reference count */
1214 en_loadvc(sc, vci); /* does debug kprintf for us */
1215 return(0);
1216 }
1217
1218 /*
1219 * turn off VCI
1220 */
1221
1222 if (sc->rxvc2slot[vci] == RX_NONE)
1223 return(EINVAL);
1224 slot = sc->rxvc2slot[vci];
1225 if ((sc->rxslot[slot].oth_flags & (ENOTHER_FREE|ENOTHER_DRAIN)) != 0)
1226 return(EINVAL);
1227 crit_enter(); /* block out enintr() */
1228 oldmode = EN_READ(sc, MID_VC(vci));
1229 newmode = MIDV_SETMODE(oldmode, MIDV_TRASH) & ~MIDV_INSERVICE;
1230 EN_WRITE(sc, MID_VC(vci), (newmode | (oldmode & MIDV_INSERVICE)));
1231 /* halt in tracks, be careful to preserve inserivce bit */
1232 DELAY(27);
1233 sc->rxslot[slot].rxhand = NULL;
1234 sc->rxslot[slot].mode = newmode;
1235
1236 sc->txslot[sc->txvc2slot[vci]].nref--;
1237 sc->txspeed[vci] = 0;
1238 sc->txvc2slot[vci] = 0;
1239
1240 /* if stuff is still going on we are going to have to drain it out */
1241 if (sc->rxslot[slot].indma.ifq_head ||
1242 sc->rxslot[slot].q.ifq_head ||
1243 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) != 0) {
1244 sc->rxslot[slot].oth_flags |= ENOTHER_DRAIN;
1245 } else {
1246 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1247 sc->rxslot[slot].atm_vci = RX_NONE;
1248 sc->rxvc2slot[vci] = RX_NONE;
1249 }
1250 crit_exit(); /* enable enintr() */
1251 #ifdef EN_DEBUG
1252 kprintf("%s: rx%d: VCI %d is now %s\n", sc->sc_dev.dv_xname, slot, vci,
1253 (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) ? "draining" : "free");
1254 #endif
1255 return(0);
1256 }
1257
1258 /***********************************************************************/
1259
1260 /*
1261 * en_reset: reset the board, throw away work in progress.
1262 * must en_init to recover.
1263 */
1264
1265 void
1266 en_reset(struct en_softc *sc)
1267 {
1268 struct mbuf *m;
1269 int lcv, slot;
1270
1271 #ifdef EN_DEBUG
1272 kprintf("%s: reset\n", sc->sc_dev.dv_xname);
1273 #endif
1274
1275 if (sc->en_busreset)
1276 sc->en_busreset(sc);
1277 EN_WRITE(sc, MID_RESID, 0x0); /* reset hardware */
1278
1279 /*
1280 * recv: dump any mbufs we are dma'ing into, if DRAINing, then a reset
1281 * will free us!
1282 */
1283
1284 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
1285 if (sc->rxvc2slot[lcv] == RX_NONE)
1286 continue;
1287 slot = sc->rxvc2slot[lcv];
1288 while (1) {
1289 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
1290 if (m == NULL)
1291 break; /* >>> exit 'while(1)' here <<< */
1292 m_freem(m);
1293 }
1294 while (1) {
1295 IF_DEQUEUE(&sc->rxslot[slot].q, m);
1296 if (m == NULL)
1297 break; /* >>> exit 'while(1)' here <<< */
1298 m_freem(m);
1299 }
1300 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
1301 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) {
1302 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1303 sc->rxvc2slot[lcv] = RX_NONE;
1304 #ifdef EN_DEBUG
1305 kprintf("%s: rx%d: VCI %d is now free\n", sc->sc_dev.dv_xname, slot, lcv);
1306 #endif
1307 }
1308 }
1309
1310 /*
1311 * xmit: dump everything
1312 */
1313
1314 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
1315 while (1) {
1316 IF_DEQUEUE(&sc->txslot[lcv].indma, m);
1317 if (m == NULL)
1318 break; /* >>> exit 'while(1)' here <<< */
1319 m_freem(m);
1320 }
1321 while (1) {
1322 IF_DEQUEUE(&sc->txslot[lcv].q, m);
1323 if (m == NULL)
1324 break; /* >>> exit 'while(1)' here <<< */
1325 m_freem(m);
1326 }
1327
1328 sc->txslot[lcv].mbsize = 0;
1329 }
1330
1331 return;
1332 }
1333
1334
1335 /*
1336 * en_init: init board and sync the card with the data in the softc.
1337 */
1338
1339 STATIC void
1340 en_init(struct en_softc *sc)
1341 {
1342 int vc, slot;
1343 u_int32_t loc;
1344
1345 if ((sc->enif.if_flags & IFF_UP) == 0) {
1346 #ifdef EN_DEBUG
1347 kprintf("%s: going down\n", sc->sc_dev.dv_xname);
1348 #endif
1349 en_reset(sc); /* to be safe */
1350 sc->enif.if_flags &= ~IFF_RUNNING; /* disable */
1351 return;
1352 }
1353
1354 #ifdef EN_DEBUG
1355 kprintf("%s: going up\n", sc->sc_dev.dv_xname);
1356 #endif
1357 sc->enif.if_flags |= IFF_RUNNING; /* enable */
1358
1359 if (sc->en_busreset)
1360 sc->en_busreset(sc);
1361 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
1362
1363 /*
1364 * init obmem data structures: vc tab, dma q's, slist.
1365 *
1366 * note that we set drq_free/dtq_free to one less than the total number
1367 * of DTQ/DRQs present. we do this because the card uses the condition
1368 * (drq_chip == drq_us) to mean "list is empty"... but if you allow the
1369 * circular list to be completely full then (drq_chip == drq_us) [i.e.
1370 * the drq_us pointer will wrap all the way around]. by restricting
1371 * the number of active requests to (N - 1) we prevent the list from
1372 * becoming completely full. note that the card will sometimes give
1373 * us an interrupt for a DTQ/DRQ we have already processes... this helps
1374 * keep that interrupt from messing us up.
1375 */
1376
1377 for (vc = 0 ; vc < MID_N_VC ; vc++)
1378 en_loadvc(sc, vc);
1379
1380 bzero(&sc->drq, sizeof(sc->drq));
1381 sc->drq_free = MID_DRQ_N - 1; /* N - 1 */
1382 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
1383 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1384 /* ensure zero queue */
1385 sc->drq_us = sc->drq_chip;
1386
1387 bzero(&sc->dtq, sizeof(sc->dtq));
1388 sc->dtq_free = MID_DTQ_N - 1; /* N - 1 */
1389 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
1390 EN_WRITE(sc, MID_DMA_WRTX, MID_DRQ_A2REG(sc->dtq_chip));
1391 /* ensure zero queue */
1392 sc->dtq_us = sc->dtq_chip;
1393
1394 sc->hwslistp = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
1395 sc->swsl_size = sc->swsl_head = sc->swsl_tail = 0;
1396
1397 #ifdef EN_DEBUG
1398 kprintf("%s: drq free/chip: %d/0x%x, dtq free/chip: %d/0x%x, hwslist: 0x%x\n",
1399 sc->sc_dev.dv_xname, sc->drq_free, sc->drq_chip,
1400 sc->dtq_free, sc->dtq_chip, sc->hwslistp);
1401 #endif
1402
1403 for (slot = 0 ; slot < EN_NTX ; slot++) {
1404 sc->txslot[slot].bfree = EN_TXSZ * 1024;
1405 EN_WRITE(sc, MIDX_READPTR(slot), 0);
1406 EN_WRITE(sc, MIDX_DESCSTART(slot), 0);
1407 loc = sc->txslot[slot].cur = sc->txslot[slot].start;
1408 loc = loc - MID_RAMOFF;
1409 loc = (loc & ~((EN_TXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
1410 loc = loc >> MIDV_LOCTOPSHFT; /* top 11 bits */
1411 EN_WRITE(sc, MIDX_PLACE(slot), MIDX_MKPLACE(en_k2sz(EN_TXSZ), loc));
1412 #ifdef EN_DEBUG
1413 kprintf("%s: tx%d: place 0x%x\n", sc->sc_dev.dv_xname, slot,
1414 EN_READ(sc, MIDX_PLACE(slot)));
1415 #endif
1416 }
1417
1418 /*
1419 * enable!
1420 */
1421
1422 EN_WRITE(sc, MID_INTENA, MID_INT_TX|MID_INT_DMA_OVR|MID_INT_IDENT|
1423 MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_DMA_RX|MID_INT_DMA_TX|
1424 MID_INT_SERVICE| /* >>> MID_INT_SUNI| XXXCDC<<< */ MID_INT_STATS);
1425 EN_WRITE(sc, MID_MAST_CSR, MID_SETIPL(sc->ipl)|MID_MCSR_ENDMA|
1426 MID_MCSR_ENTX|MID_MCSR_ENRX);
1427
1428 }
1429
1430
1431 /*
1432 * en_loadvc: load a vc tab entry from a slot
1433 */
1434
1435 STATIC void
1436 en_loadvc(struct en_softc *sc, int vc)
1437 {
1438 int slot;
1439 u_int32_t reg = EN_READ(sc, MID_VC(vc));
1440
1441 reg = MIDV_SETMODE(reg, MIDV_TRASH);
1442 EN_WRITE(sc, MID_VC(vc), reg);
1443 DELAY(27);
1444
1445 if ((slot = sc->rxvc2slot[vc]) == RX_NONE)
1446 return;
1447
1448 /* no need to set CRC */
1449 EN_WRITE(sc, MID_DST_RP(vc), 0); /* read pointer = 0, desc. start = 0 */
1450 EN_WRITE(sc, MID_WP_ST_CNT(vc), 0); /* write pointer = 0 */
1451 EN_WRITE(sc, MID_VC(vc), sc->rxslot[slot].mode); /* set mode, size, loc */
1452 sc->rxslot[slot].cur = sc->rxslot[slot].start;
1453
1454 #ifdef EN_DEBUG
1455 kprintf("%s: rx%d: assigned to VCI %d\n", sc->sc_dev.dv_xname, slot, vc);
1456 #endif
1457 }
1458
1459
1460 /*
1461 * en_start: start transmitting the next packet that needs to go out
1462 * if there is one. note that atm_output() has already locked us.
1463 */
1464
1465 STATIC void
1466 en_start(struct ifnet *ifp)
1467 {
1468 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1469 struct mbuf *m, *lastm, *prev;
1470 struct atm_pseudohdr *ap, *new_ap;
1471 int txchan, mlen, got, need, toadd, cellcnt, first;
1472 u_int32_t atm_vpi, atm_vci, atm_flags, *dat, aal;
1473 u_int8_t *cp;
1474
1475 if ((ifp->if_flags & IFF_RUNNING) == 0)
1476 return;
1477
1478 /*
1479 * remove everything from interface queue since we handle all queueing
1480 * locally ...
1481 */
1482
1483 while (1) {
1484
1485 IF_DEQUEUE(&ifp->if_snd, m);
1486 if (m == NULL)
1487 return; /* EMPTY: >>> exit here <<< */
1488
1489 /*
1490 * calculate size of packet (in bytes)
1491 * also, if we are not doing transmit DMA we eliminate all stupid
1492 * (non-word) alignments here using en_mfix(). calls to en_mfix()
1493 * seem to be due to tcp retransmits for the most part.
1494 *
1495 * after this loop mlen total length of mbuf chain (including atm_ph),
1496 * and lastm is a pointer to the last mbuf on the chain.
1497 */
1498
1499 lastm = m;
1500 mlen = 0;
1501 prev = NULL;
1502 while (1) {
1503 /* no DMA? */
1504 if ((!sc->is_adaptec && EN_ENIDMAFIX) || EN_NOTXDMA || !en_dma) {
1505 if ( ((uintptr_t)mtod(lastm, void *) % sizeof(u_int32_t)) != 0 ||
1506 ((lastm->m_len % sizeof(u_int32_t)) != 0 && lastm->m_next)) {
1507 first = (lastm == m);
1508 if (en_mfix(sc, &lastm, prev) == 0) { /* failed? */
1509 m_freem(m);
1510 m = NULL;
1511 break;
1512 }
1513 if (first)
1514 m = lastm; /* update */
1515 }
1516 prev = lastm;
1517 }
1518
1519 mlen += lastm->m_len;
1520 if (lastm->m_next == NULL)
1521 break;
1522 lastm = lastm->m_next;
1523 }
1524
1525 if (m == NULL) /* happens only if mfix fails */
1526 continue;
1527
1528 ap = mtod(m, struct atm_pseudohdr *);
1529
1530 atm_vpi = ATM_PH_VPI(ap);
1531 atm_vci = ATM_PH_VCI(ap);
1532 atm_flags = ATM_PH_FLAGS(ap) & ~(EN_OBHDR|EN_OBTRL);
1533 aal = ((atm_flags & ATM_PH_AAL5) != 0)
1534 ? MID_TBD_AAL5 : MID_TBD_NOAAL5;
1535
1536 /*
1537 * check that vpi/vci is one we can use
1538 */
1539
1540 if (atm_vpi || atm_vci > MID_N_VC) {
1541 kprintf("%s: output vpi=%d, vci=%d out of card range, dropping...\n",
1542 sc->sc_dev.dv_xname, atm_vpi, atm_vci);
1543 m_freem(m);
1544 continue;
1545 }
1546
1547 /*
1548 * computing how much padding we need on the end of the mbuf, then
1549 * see if we can put the TBD at the front of the mbuf where the
1550 * link header goes (well behaved protocols will reserve room for us).
1551 * last, check if room for PDU tail.
1552 *
1553 * got = number of bytes of data we have
1554 * cellcnt = number of cells in this mbuf
1555 * need = number of bytes of data + padding we need (excludes TBD)
1556 * toadd = number of bytes of data we need to add to end of mbuf,
1557 * [including AAL5 PDU, if AAL5]
1558 */
1559
1560 got = mlen - sizeof(struct atm_pseudohdr *);
1561 toadd = (aal == MID_TBD_AAL5) ? MID_PDU_SIZE : 0; /* PDU */
1562 cellcnt = (got + toadd + (MID_ATMDATASZ - 1)) / MID_ATMDATASZ;
1563 need = cellcnt * MID_ATMDATASZ;
1564 toadd = need - got; /* recompute, including zero padding */
1565
1566 #ifdef EN_DEBUG
1567 kprintf("%s: txvci%d: mlen=%d, got=%d, need=%d, toadd=%d, cell#=%d\n",
1568 sc->sc_dev.dv_xname, atm_vci, mlen, got, need, toadd, cellcnt);
1569 kprintf(" leading_space=%d, trailing_space=%d\n",
1570 M_LEADINGSPACE(m), M_TRAILINGSPACE(lastm));
1571 #endif
1572
1573 #ifdef EN_MBUF_OPT
1574
1575 /*
1576 * note: external storage (M_EXT) can be shared between mbufs
1577 * to avoid copying (see m_copym()). this means that the same
1578 * data buffer could be shared by several mbufs, and thus it isn't
1579 * a good idea to try and write TBDs or PDUs to M_EXT data areas.
1580 */
1581
1582 if (M_LEADINGSPACE(m) >= MID_TBD_SIZE && (m->m_flags & M_EXT) == 0) {
1583 m->m_data -= MID_TBD_SIZE;
1584 m->m_len += MID_TBD_SIZE;
1585 mlen += MID_TBD_SIZE;
1586 new_ap = mtod(m, struct atm_pseudohdr *);
1587 *new_ap = *ap; /* move it back */
1588 ap = new_ap;
1589 dat = ((u_int32_t *) ap) + 1;
1590 /* make sure the TBD is in proper byte order */
1591 *dat++ = htonl(MID_TBD_MK1(aal, sc->txspeed[atm_vci], cellcnt));
1592 *dat = htonl(MID_TBD_MK2(atm_vci, 0, 0));
1593 atm_flags |= EN_OBHDR;
1594 }
1595
1596 if (toadd && (lastm->m_flags & M_EXT) == 0 &&
1597 M_TRAILINGSPACE(lastm) >= toadd) {
1598 cp = mtod(lastm, u_int8_t *) + lastm->m_len;
1599 lastm->m_len += toadd;
1600 mlen += toadd;
1601 if (aal == MID_TBD_AAL5) {
1602 bzero(cp, toadd - MID_PDU_SIZE);
1603 dat = (u_int32_t *)(cp + toadd - MID_PDU_SIZE);
1604 /* make sure the PDU is in proper byte order */
1605 *dat = htonl(MID_PDU_MK1(0, 0, got));
1606 } else {
1607 bzero(cp, toadd);
1608 }
1609 atm_flags |= EN_OBTRL;
1610 }
1611 ATM_PH_FLAGS(ap) = atm_flags; /* update EN_OBHDR/EN_OBTRL bits */
1612 #endif /* EN_MBUF_OPT */
1613
1614 /*
1615 * get assigned channel (will be zero unless txspeed[atm_vci] is set)
1616 */
1617
1618 txchan = sc->txvc2slot[atm_vci];
1619
1620 if (sc->txslot[txchan].mbsize > EN_TXHIWAT) {
1621 EN_COUNT(sc->txmbovr);
1622 m_freem(m);
1623 #ifdef EN_DEBUG
1624 kprintf("%s: tx%d: buffer space shortage\n", sc->sc_dev.dv_xname,
1625 txchan);
1626 #endif
1627 continue;
1628 }
1629
1630 sc->txslot[txchan].mbsize += mlen;
1631
1632 #ifdef EN_DEBUG
1633 kprintf("%s: tx%d: VPI=%d, VCI=%d, FLAGS=0x%x, speed=0x%x\n",
1634 sc->sc_dev.dv_xname, txchan, atm_vpi, atm_vci, atm_flags,
1635 sc->txspeed[atm_vci]);
1636 kprintf(" adjusted mlen=%d, mbsize=%d\n", mlen,
1637 sc->txslot[txchan].mbsize);
1638 #endif
1639
1640 IF_ENQUEUE(&sc->txslot[txchan].q, m);
1641
1642 en_txdma(sc, txchan);
1643
1644 }
1645 /*NOTREACHED*/
1646 }
1647
1648
1649 /*
1650 * en_mfix: fix a stupid mbuf
1651 */
1652
1653 STATIC int en_makeexclusive(struct en_softc *, struct mbuf **, struct mbuf *);
1654
1655 STATIC int
1656 en_makeexclusive(struct en_softc *sc, struct mbuf **mm, struct mbuf *prev)
1657 {
1658 struct mbuf *m, *new;
1659
1660 m = *mm;
1661
1662 if (m->m_flags & M_EXT) {
1663 if (!(m->m_flags & M_EXT_CLUSTER)) {
1664 /* external buffer isn't an ordinary mbuf cluster! */
1665 kprintf("%s: mfix: special buffer! can't make a copy!\n",
1666 sc->sc_dev.dv_xname);
1667 return (0);
1668 }
1669
1670 if (m_sharecount(m) > 1) {
1671 /* make a real copy of the M_EXT mbuf since it is shared */
1672 new = m_getcl(MB_DONTWAIT, MT_DATA, m->m_flags & M_PKTHDR);
1673 if (new == NULL) {
1674 m_free(new);
1675 EN_COUNT(sc->mfixfail);
1676 return (0);
1677 }
1678 if (m->m_flags & M_PKTHDR)
1679 M_MOVE_PKTHDR(new, m);
1680 bcopy(m->m_data, new->m_data, m->m_len);
1681 new->m_len = m->m_len;
1682 new->m_next = m->m_next;
1683 if (prev)
1684 prev->m_next = new;
1685 m_free(m);
1686 *mm = new;
1687 }
1688 else {
1689 /* the buffer is not shared, align the data offset using
1690 this buffer. */
1691 u_char *d = mtod(m, u_char *);
1692 int off = ((uintptr_t)(void *)d) % sizeof(u_int32_t);
1693
1694 if (off > 0) {
1695 bcopy(d, d - off, m->m_len);
1696 m->m_data = (caddr_t)d - off;
1697 }
1698 }
1699 }
1700 return (1);
1701 }
1702
1703 STATIC int
1704 en_mfix(struct en_softc *sc, struct mbuf **mm, struct mbuf *prev)
1705 {
1706 struct mbuf *m;
1707 u_char *d, *cp;
1708 int off;
1709 struct mbuf *nxt;
1710
1711 m = *mm;
1712
1713 EN_COUNT(sc->mfix); /* count # of calls */
1714 #ifdef EN_DEBUG
1715 kprintf("%s: mfix mbuf m_data=0x%x, m_len=%d\n", sc->sc_dev.dv_xname,
1716 m->m_data, m->m_len);
1717 #endif
1718
1719 d = mtod(m, u_char *);
1720 off = ((uintptr_t) (void *) d) % sizeof(u_int32_t);
1721
1722 if (off) {
1723 if ((m->m_flags & M_EXT) == 0) {
1724 bcopy(d, d - off, m->m_len); /* ALIGN! (with costly data copy...) */
1725 d -= off;
1726 m->m_data = (caddr_t)d;
1727 } else {
1728 /* can't write to an M_EXT mbuf since it may be shared */
1729 if (en_makeexclusive(sc, &m, prev) == 0)
1730 return (0);
1731 *mm = m; /* note: 'd' now invalid */
1732 }
1733 }
1734
1735 off = m->m_len % sizeof(u_int32_t);
1736 if (off == 0)
1737 return(1);
1738
1739 if (m->m_flags & M_EXT) {
1740 /* can't write to an M_EXT mbuf since it may be shared */
1741 if (en_makeexclusive(sc, &m, prev) == 0)
1742 return (0);
1743 *mm = m; /* note: 'd' now invalid */
1744 }
1745
1746 d = mtod(m, u_char *) + m->m_len;
1747 off = sizeof(u_int32_t) - off;
1748
1749 nxt = m->m_next;
1750 while (off--) {
1751 if (nxt != NULL && nxt->m_len == 0) {
1752 /* remove an empty mbuf. this avoids odd byte padding to an empty
1753 last mbuf. */
1754 m->m_next = nxt = m_free(nxt);
1755 }
1756 if (nxt == NULL) { /* out of data, zero fill */
1757 *d++ = 0;
1758 continue; /* next "off" */
1759 }
1760 cp = mtod(nxt, u_char *);
1761 *d++ = *cp++;
1762 m->m_len++;
1763 nxt->m_len--;
1764 nxt->m_data = (caddr_t)cp;
1765 }
1766 if (nxt != NULL && nxt->m_len == 0)
1767 m->m_next = m_free(nxt);
1768 return(1);
1769 }
1770
1771 /*
1772 * en_txdma: start trasmit DMA, if possible
1773 */
1774
1775 STATIC void
1776 en_txdma(struct en_softc *sc, int chan)
1777 {
1778 struct mbuf *tmp;
1779 struct atm_pseudohdr *ap;
1780 struct en_launch launch;
1781 int datalen = 0, dtqneed, len, ncells;
1782 u_int8_t *cp;
1783 struct ifnet *ifp;
1784
1785 #ifdef EN_DEBUG
1786 kprintf("%s: tx%d: starting...\n", sc->sc_dev.dv_xname, chan);
1787 #endif
1788
1789 /*
1790 * note: now that txlaunch handles non-word aligned/sized requests
1791 * the only time you can safely set launch.nodma is if you've en_mfix()'d
1792 * the mbuf chain. this happens only if EN_NOTXDMA || !en_dma.
1793 */
1794
1795 launch.nodma = (EN_NOTXDMA || !en_dma);
1796
1797 again:
1798
1799 /*
1800 * get an mbuf waiting for DMA
1801 */
1802
1803 launch.t = sc->txslot[chan].q.ifq_head; /* peek at head of queue */
1804
1805 if (launch.t == NULL) {
1806 #ifdef EN_DEBUG
1807 kprintf("%s: tx%d: ...done!\n", sc->sc_dev.dv_xname, chan);
1808 #endif
1809 return; /* >>> exit here if no data waiting for DMA <<< */
1810 }
1811
1812 /*
1813 * get flags, vci
1814 *
1815 * note: launch.need = # bytes we need to get on the card
1816 * dtqneed = # of DTQs we need for this packet
1817 * launch.mlen = # of bytes in in mbuf chain (<= launch.need)
1818 */
1819
1820 ap = mtod(launch.t, struct atm_pseudohdr *);
1821 launch.atm_vci = ATM_PH_VCI(ap);
1822 launch.atm_flags = ATM_PH_FLAGS(ap);
1823 launch.aal = ((launch.atm_flags & ATM_PH_AAL5) != 0) ?
1824 MID_TBD_AAL5 : MID_TBD_NOAAL5;
1825
1826 /*
1827 * XXX: have to recompute the length again, even though we already did
1828 * it in en_start(). might as well compute dtqneed here as well, so
1829 * this isn't that bad.
1830 */
1831
1832 if ((launch.atm_flags & EN_OBHDR) == 0) {
1833 dtqneed = 1; /* header still needs to be added */
1834 launch.need = MID_TBD_SIZE; /* not includeded with mbuf */
1835 } else {
1836 dtqneed = 0; /* header on-board, dma with mbuf */
1837 launch.need = 0;
1838 }
1839
1840 launch.mlen = 0;
1841 for (tmp = launch.t ; tmp != NULL ; tmp = tmp->m_next) {
1842 len = tmp->m_len;
1843 launch.mlen += len;
1844 cp = mtod(tmp, u_int8_t *);
1845 if (tmp == launch.t) {
1846 len -= sizeof(struct atm_pseudohdr); /* don't count this! */
1847 cp += sizeof(struct atm_pseudohdr);
1848 }
1849 launch.need += len;
1850 if (len == 0)
1851 continue; /* atm_pseudohdr alone in first mbuf */
1852
1853 dtqneed += en_dqneed(sc, (caddr_t) cp, len, 1);
1854 }
1855
1856 if ((launch.need % sizeof(u_int32_t)) != 0)
1857 dtqneed++; /* need DTQ to FLUSH internal buffer */
1858
1859 if ((launch.atm_flags & EN_OBTRL) == 0) {
1860 if (launch.aal == MID_TBD_AAL5) {
1861 datalen = launch.need - MID_TBD_SIZE;
1862 launch.need += MID_PDU_SIZE; /* AAL5: need PDU tail */
1863 }
1864 dtqneed++; /* need to work on the end a bit */
1865 }
1866
1867 /*
1868 * finish calculation of launch.need (need to figure out how much padding
1869 * we will need). launch.need includes MID_TBD_SIZE, but we need to
1870 * remove that to so we can round off properly. we have to add
1871 * MID_TBD_SIZE back in after calculating ncells.
1872 */
1873
1874 launch.need = roundup(launch.need - MID_TBD_SIZE, MID_ATMDATASZ);
1875 ncells = launch.need / MID_ATMDATASZ;
1876 launch.need += MID_TBD_SIZE;
1877
1878 if (launch.need > EN_TXSZ * 1024) {
1879 kprintf("%s: tx%d: packet larger than xmit buffer (%d > %d)\n",
1880 sc->sc_dev.dv_xname, chan, launch.need, EN_TXSZ * 1024);
1881 goto dequeue_drop;
1882 }
1883
1884 /*
1885 * note: don't use the entire buffer space. if WRTX becomes equal
1886 * to RDTX, the transmitter stops assuming the buffer is empty! --kjc
1887 */
1888 if (launch.need >= sc->txslot[chan].bfree) {
1889 EN_COUNT(sc->txoutspace);
1890 #ifdef EN_DEBUG
1891 kprintf("%s: tx%d: out of transmit space\n", sc->sc_dev.dv_xname, chan);
1892 #endif
1893 return; /* >>> exit here if out of obmem buffer space <<< */
1894 }
1895
1896 /*
1897 * ensure we have enough dtqs to go, if not, wait for more.
1898 */
1899
1900 if (launch.nodma) {
1901 dtqneed = 1;
1902 }
1903 if (dtqneed > sc->dtq_free) {
1904 sc->need_dtqs = 1;
1905 EN_COUNT(sc->txdtqout);
1906 #ifdef EN_DEBUG
1907 kprintf("%s: tx%d: out of transmit DTQs\n", sc->sc_dev.dv_xname, chan);
1908 #endif
1909 return; /* >>> exit here if out of dtqs <<< */
1910 }
1911
1912 /*
1913 * it is a go, commit! dequeue mbuf start working on the xfer.
1914 */
1915
1916 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
1917 #ifdef EN_DIAG
1918 if (launch.t != tmp)
1919 panic("en dequeue");
1920 #endif /* EN_DIAG */
1921
1922 /*
1923 * launch!
1924 */
1925
1926 EN_COUNT(sc->launch);
1927 ifp = &sc->enif;
1928 ifp->if_opackets++;
1929
1930 if ((launch.atm_flags & EN_OBHDR) == 0) {
1931 EN_COUNT(sc->lheader);
1932 /* store tbd1/tbd2 in host byte order */
1933 launch.tbd1 = MID_TBD_MK1(launch.aal, sc->txspeed[launch.atm_vci], ncells);
1934 launch.tbd2 = MID_TBD_MK2(launch.atm_vci, 0, 0);
1935 }
1936 if ((launch.atm_flags & EN_OBTRL) == 0 && launch.aal == MID_TBD_AAL5) {
1937 EN_COUNT(sc->ltail);
1938 launch.pdu1 = MID_PDU_MK1(0, 0, datalen); /* host byte order */
1939 }
1940
1941 en_txlaunch(sc, chan, &launch);
1942
1943 if (ifp->if_bpf) {
1944 /*
1945 * adjust the top of the mbuf to skip the pseudo atm header
1946 * (and TBD, if present) before passing the packet to bpf,
1947 * restore it afterwards.
1948 */
1949 int size = sizeof(struct atm_pseudohdr);
1950 if (launch.atm_flags & EN_OBHDR)
1951 size += MID_TBD_SIZE;
1952
1953 launch.t->m_data += size;
1954 launch.t->m_len -= size;
1955
1956 BPF_MTAP(ifp, launch.t);
1957
1958 launch.t->m_data -= size;
1959 launch.t->m_len += size;
1960 }
1961 /*
1962 * do some housekeeping and get the next packet
1963 */
1964
1965 sc->txslot[chan].bfree -= launch.need;
1966 IF_ENQUEUE(&sc->txslot[chan].indma, launch.t);
1967 goto again;
1968
1969 /*
1970 * END of txdma loop!
1971 */
1972
1973 /*
1974 * error handles
1975 */
1976
1977 dequeue_drop:
1978 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
1979 if (launch.t != tmp)
1980 panic("en dequeue drop");
1981 m_freem(launch.t);
1982 sc->txslot[chan].mbsize -= launch.mlen;
1983 goto again;
1984 }
1985
1986
1987 /*
1988 * en_txlaunch: launch an mbuf into the dma pool!
1989 */
1990
1991 STATIC void
1992 en_txlaunch(struct en_softc *sc, int chan, struct en_launch *l)
1993 {
1994 struct mbuf *tmp;
1995 u_int32_t cur = sc->txslot[chan].cur,
1996 start = sc->txslot[chan].start,
1997 stop = sc->txslot[chan].stop,
1998 dma, *data, *datastop, count, bcode;
1999 int pad, addtail, need, len, needalign, cnt, end, mx;
2000
2001
2002 /*
2003 * vars:
2004 * need = # bytes card still needs (decr. to zero)
2005 * len = # of bytes left in current mbuf
2006 * cur = our current pointer
2007 * dma = last place we programmed into the DMA
2008 * data = pointer into data area of mbuf that needs to go next
2009 * cnt = # of bytes to transfer in this DTQ
2010 * bcode/count = DMA burst code, and chip's version of cnt
2011 *
2012 * a single buffer can require up to 5 DTQs depending on its size
2013 * and alignment requirements. the 5 possible requests are:
2014 * [1] 1, 2, or 3 byte DMA to align src data pointer to word boundary
2015 * [2] alburst DMA to align src data pointer to bestburstlen
2016 * [3] 1 or more bestburstlen DMAs
2017 * [4] clean up burst (to last word boundary)
2018 * [5] 1, 2, or 3 byte final clean up DMA
2019 */
2020
2021 need = l->need;
2022 dma = cur;
2023 addtail = (l->atm_flags & EN_OBTRL) == 0; /* add a tail? */
2024
2025 #ifdef EN_DIAG
2026 if ((need - MID_TBD_SIZE) % MID_ATMDATASZ)
2027 kprintf("%s: tx%d: bogus trasmit needs (%d)\n", sc->sc_dev.dv_xname, chan,
2028 need);
2029 #endif
2030 #ifdef EN_DEBUG
2031 kprintf("%s: tx%d: launch mbuf %p! cur=0x%x[%d], need=%d, addtail=%d\n",
2032 sc->sc_dev.dv_xname, chan, l->t, cur, (cur-start)/4, need, addtail);
2033 count = EN_READ(sc, MIDX_PLACE(chan));
2034 kprintf(" HW: base_address=0x%x, size=%d, read=%d, descstart=%d\n",
2035 MIDX_BASE(count), MIDX_SZ(count), EN_READ(sc, MIDX_READPTR(chan)),
2036 EN_READ(sc, MIDX_DESCSTART(chan)));
2037 #endif
2038
2039 /*
2040 * do we need to insert the TBD by hand?
2041 * note that tbd1/tbd2/pdu1 are in host byte order.
2042 */
2043
2044 if ((l->atm_flags & EN_OBHDR) == 0) {
2045 #ifdef EN_DEBUG
2046 kprintf("%s: tx%d: insert header 0x%x 0x%x\n", sc->sc_dev.dv_xname,
2047 chan, l->tbd1, l->tbd2);
2048 #endif
2049 EN_WRITE(sc, cur, l->tbd1);
2050 EN_WRAPADD(start, stop, cur, 4);
2051 EN_WRITE(sc, cur, l->tbd2);
2052 EN_WRAPADD(start, stop, cur, 4);
2053 need -= 8;
2054 }
2055
2056 /*
2057 * now do the mbufs...
2058 */
2059
2060 for (tmp = l->t ; tmp != NULL ; tmp = tmp->m_next) {
2061
2062 /* get pointer to data and length */
2063 data = mtod(tmp, u_int32_t *);
2064 len = tmp->m_len;
2065 if (tmp == l->t) {
2066 data += sizeof(struct atm_pseudohdr)/sizeof(u_int32_t);
2067 len -= sizeof(struct atm_pseudohdr);
2068 }
2069
2070 /* now, determine if we should copy it */
2071 if (l->nodma || (len < EN_MINDMA &&
2072 (len % 4) == 0 && ((uintptr_t) (void *) data % 4) == 0 &&
2073 (cur % 4) == 0)) {
2074
2075 /*
2076 * roundup len: the only time this will change the value of len
2077 * is when l->nodma is true, tmp is the last mbuf, and there is
2078 * a non-word number of bytes to transmit. in this case it is
2079 * safe to round up because we've en_mfix'd the mbuf (so the first
2080 * byte is word aligned there must be enough free bytes at the end
2081 * to round off to the next word boundary)...
2082 */
2083 len = roundup(len, sizeof(u_int32_t));
2084 datastop = data + (len / sizeof(u_int32_t));
2085 /* copy loop: preserve byte order!!! use WRITEDAT */
2086 while (data != datastop) {
2087 EN_WRITEDAT(sc, cur, *data);
2088 data++;
2089 EN_WRAPADD(start, stop, cur, 4);
2090 }
2091 need -= len;
2092 #ifdef EN_DEBUG
2093 kprintf("%s: tx%d: copied %d bytes (%d left, cur now 0x%x)\n",
2094 sc->sc_dev.dv_xname, chan, len, need, cur);
2095 #endif
2096 continue; /* continue on to next mbuf */
2097 }
2098
2099 /* going to do DMA, first make sure the dtq is in sync. */
2100 if (dma != cur) {
2101 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0, 0, 0);
2102 #ifdef EN_DEBUG
2103 kprintf("%s: tx%d: dtq_sync: advance pointer to %d\n",
2104 sc->sc_dev.dv_xname, chan, cur);
2105 #endif
2106 }
2107
2108 /*
2109 * if this is the last buffer, and it looks like we are going to need to
2110 * flush the internal buffer, can we extend the length of this mbuf to
2111 * avoid the FLUSH?
2112 */
2113
2114 if (tmp->m_next == NULL) {
2115 cnt = (need - len) % sizeof(u_int32_t);
2116 if (cnt && M_TRAILINGSPACE(tmp) >= cnt)
2117 len += cnt; /* pad for FLUSH */
2118 }
2119
2120 #if !defined(MIDWAY_ENIONLY)
2121
2122 /*
2123 * the adaptec DMA engine is smart and handles everything for us.
2124 */
2125
2126 if (sc->is_adaptec) {
2127 /* need to DMA "len" bytes out to card */
2128 need -= len;
2129 EN_WRAPADD(start, stop, cur, len);
2130 #ifdef EN_DEBUG
2131 kprintf("%s: tx%d: adp_dma %d bytes (%d left, cur now 0x%x)\n",
2132 sc->sc_dev.dv_xname, chan, len, need, cur);
2133 #endif
2134 end = (need == 0) ? MID_DMA_END : 0;
2135 EN_DTQADD(sc, len, chan, 0, vtophys(data), l->mlen, end);
2136 if (end)
2137 goto done;
2138 dma = cur; /* update dma pointer */
2139 continue;
2140 }
2141 #endif /* !MIDWAY_ENIONLY */
2142
2143 #if !defined(MIDWAY_ADPONLY)
2144
2145 /*
2146 * the ENI DMA engine is not so smart and need more help from us
2147 */
2148
2149 /* do we need to do a DMA op to align to word boundary? */
2150 needalign = (uintptr_t) (void *) data % sizeof(u_int32_t);
2151 if (needalign) {
2152 EN_COUNT(sc->headbyte);
2153 cnt = sizeof(u_int32_t) - needalign;
2154 if (cnt == 2 && len >= cnt) {
2155 count = 1;
2156 bcode = MIDDMA_2BYTE;
2157 } else {
2158 cnt = min(cnt, len); /* prevent overflow */
2159 count = cnt;
2160 bcode = MIDDMA_BYTE;
2161 }
2162 need -= cnt;
2163 EN_WRAPADD(start, stop, cur, cnt);
2164 #ifdef EN_DEBUG
2165 kprintf("%s: tx%d: small al_dma %d bytes (%d left, cur now 0x%x)\n",
2166 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2167 #endif
2168 len -= cnt;
2169 end = (need == 0) ? MID_DMA_END : 0;
2170 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2171 if (end)
2172 goto done;
2173 data = (u_int32_t *) ((u_char *)data + cnt);
2174 }
2175
2176 /* do we need to do a DMA op to align? */
2177 if (sc->alburst &&
2178 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0
2179 && len >= sizeof(u_int32_t)) {
2180 cnt = sc->bestburstlen - needalign;
2181 mx = len & ~(sizeof(u_int32_t)-1); /* don't go past end */
2182 if (cnt > mx) {
2183 cnt = mx;
2184 count = cnt / sizeof(u_int32_t);
2185 bcode = MIDDMA_WORD;
2186 } else {
2187 count = cnt / sizeof(u_int32_t);
2188 bcode = en_dmaplan[count].bcode;
2189 count = cnt >> en_dmaplan[count].divshift;
2190 }
2191 need -= cnt;
2192 EN_WRAPADD(start, stop, cur, cnt);
2193 #ifdef EN_DEBUG
2194 kprintf("%s: tx%d: al_dma %d bytes (%d left, cur now 0x%x)\n",
2195 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2196 #endif
2197 len -= cnt;
2198 end = (need == 0) ? MID_DMA_END : 0;
2199 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2200 if (end)
2201 goto done;
2202 data = (u_int32_t *) ((u_char *)data + cnt);
2203 }
2204
2205 /* do we need to do a max-sized burst? */
2206 if (len >= sc->bestburstlen) {
2207 count = len >> sc->bestburstshift;
2208 cnt = count << sc->bestburstshift;
2209 bcode = sc->bestburstcode;
2210 need -= cnt;
2211 EN_WRAPADD(start, stop, cur, cnt);
2212 #ifdef EN_DEBUG
2213 kprintf("%s: tx%d: best_dma %d bytes (%d left, cur now 0x%x)\n",
2214 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2215 #endif
2216 len -= cnt;
2217 end = (need == 0) ? MID_DMA_END : 0;
2218 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2219 if (end)
2220 goto done;
2221 data = (u_int32_t *) ((u_char *)data + cnt);
2222 }
2223
2224 /* do we need to do a cleanup burst? */
2225 cnt = len & ~(sizeof(u_int32_t)-1);
2226 if (cnt) {
2227 count = cnt / sizeof(u_int32_t);
2228 bcode = en_dmaplan[count].bcode;
2229 count = cnt >> en_dmaplan[count].divshift;
2230 need -= cnt;
2231 EN_WRAPADD(start, stop, cur, cnt);
2232 #ifdef EN_DEBUG
2233 kprintf("%s: tx%d: cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2234 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2235 #endif
2236 len -= cnt;
2237 end = (need == 0) ? MID_DMA_END : 0;
2238 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2239 if (end)
2240 goto done;
2241 data = (u_int32_t *) ((u_char *)data + cnt);
2242 }
2243
2244 /* any word fragments left? */
2245 if (len) {
2246 EN_COUNT(sc->tailbyte);
2247 if (len == 2) {
2248 count = 1;
2249 bcode = MIDDMA_2BYTE; /* use 2byte mode */
2250 } else {
2251 count = len;
2252 bcode = MIDDMA_BYTE; /* use 1 byte mode */
2253 }
2254 need -= len;
2255 EN_WRAPADD(start, stop, cur, len);
2256 #ifdef EN_DEBUG
2257 kprintf("%s: tx%d: byte cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2258 sc->sc_dev.dv_xname, chan, len, need, cur);
2259 #endif
2260 end = (need == 0) ? MID_DMA_END : 0;
2261 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2262 if (end)
2263 goto done;
2264 }
2265
2266 dma = cur; /* update dma pointer */
2267 #endif /* !MIDWAY_ADPONLY */
2268
2269 } /* next mbuf, please */
2270
2271 /*
2272 * all mbuf data has been copied out to the obmem (or set up to be DMAd).
2273 * if the trailer or padding needs to be put in, do it now.
2274 *
2275 * NOTE: experimental results reveal the following fact:
2276 * if you DMA "X" bytes to the card, where X is not a multiple of 4,
2277 * then the card will internally buffer the last (X % 4) bytes (in
2278 * hopes of getting (4 - (X % 4)) more bytes to make a complete word).
2279 * it is imporant to make sure we don't leave any important data in
2280 * this internal buffer because it is discarded on the last (end) DTQ.
2281 * one way to do this is to DMA in (4 - (X % 4)) more bytes to flush
2282 * the darn thing out.
2283 */
2284
2285 if (addtail) {
2286
2287 pad = need % sizeof(u_int32_t);
2288 if (pad) {
2289 /*
2290 * FLUSH internal data buffer. pad out with random data from the front
2291 * of the mbuf chain...
2292 */
2293 bcode = (sc->is_adaptec) ? 0 : MIDDMA_BYTE;
2294 EN_COUNT(sc->tailflush);
2295 EN_WRAPADD(start, stop, cur, pad);
2296 EN_DTQADD(sc, pad, chan, bcode, vtophys(l->t->m_data), 0, 0);
2297 need -= pad;
2298 #ifdef EN_DEBUG
2299 kprintf("%s: tx%d: pad/FLUSH dma %d bytes (%d left, cur now 0x%x)\n",
2300 sc->sc_dev.dv_xname, chan, pad, need, cur);
2301 #endif
2302 }
2303
2304 /* copy data */
2305 pad = need / sizeof(u_int32_t); /* round *down* */
2306 if (l->aal == MID_TBD_AAL5)
2307 pad -= 2;
2308 #ifdef EN_DEBUG
2309 kprintf("%s: tx%d: padding %d bytes (cur now 0x%x)\n",
2310 sc->sc_dev.dv_xname, chan, pad * sizeof(u_int32_t), cur);
2311 #endif
2312 while (pad--) {
2313 EN_WRITEDAT(sc, cur, 0); /* no byte order issues with zero */
2314 EN_WRAPADD(start, stop, cur, 4);
2315 }
2316 if (l->aal == MID_TBD_AAL5) {
2317 EN_WRITE(sc, cur, l->pdu1); /* in host byte order */
2318 EN_WRAPADD(start, stop, cur, 8);
2319 }
2320 }
2321
2322 if (addtail || dma != cur) {
2323 /* write final descritor */
2324 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0,
2325 l->mlen, MID_DMA_END);
2326 /* dma = cur; */ /* not necessary since we are done */
2327 }
2328
2329 done:
2330 /* update current pointer */
2331 sc->txslot[chan].cur = cur;
2332 #ifdef EN_DEBUG
2333 kprintf("%s: tx%d: DONE! cur now = 0x%x\n",
2334 sc->sc_dev.dv_xname, chan, cur);
2335 #endif
2336
2337 return;
2338 }
2339
2340
2341 /*
2342 * interrupt handler
2343 */
2344
2345 EN_INTR_TYPE
2346 en_intr(void *arg)
2347 {
2348 struct en_softc *sc = (struct en_softc *) arg;
2349 struct mbuf *m;
2350 struct atm_pseudohdr ah;
2351 struct ifnet *ifp;
2352 u_int32_t reg, kick, val, mask, chip, vci, slot, dtq, drq;
2353 int lcv, idx, need_softserv = 0;
2354
2355 reg = EN_READ(sc, MID_INTACK);
2356
2357 if ((reg & MID_INT_ANY) == 0)
2358 EN_INTR_RET(0); /* not us */
2359
2360 #ifdef EN_DEBUG
2361 kprintf("%s: interrupt=0x%b\n", sc->sc_dev.dv_xname, reg, MID_INTBITS);
2362 #endif
2363
2364 /*
2365 * unexpected errors that need a reset
2366 */
2367
2368 if ((reg & (MID_INT_IDENT|MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_SUNI)) != 0) {
2369 kprintf("%s: unexpected interrupt=0x%b, resetting card\n",
2370 sc->sc_dev.dv_xname, reg, MID_INTBITS);
2371 #ifdef EN_DEBUG
2372 #ifdef DDB
2373 Debugger("en: unexpected error");
2374 #endif /* DDB */
2375 sc->enif.if_flags &= ~IFF_RUNNING; /* FREEZE! */
2376 #else
2377 en_reset(sc);
2378 en_init(sc);
2379 #endif
2380 EN_INTR_RET(1); /* for us */
2381 }
2382
2383 /*******************
2384 * xmit interrupts *
2385 ******************/
2386
2387 kick = 0; /* bitmask of channels to kick */
2388 if (reg & MID_INT_TX) { /* TX done! */
2389
2390 /*
2391 * check for tx complete, if detected then this means that some space
2392 * has come free on the card. we must account for it and arrange to
2393 * kick the channel to life (in case it is stalled waiting on the card).
2394 */
2395 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2396 if (reg & MID_TXCHAN(lcv)) {
2397 kick = kick | mask; /* want to kick later */
2398 val = EN_READ(sc, MIDX_READPTR(lcv)); /* current read pointer */
2399 val = (val * sizeof(u_int32_t)) + sc->txslot[lcv].start;
2400 /* convert to offset */
2401 if (val > sc->txslot[lcv].cur)
2402 sc->txslot[lcv].bfree = val - sc->txslot[lcv].cur;
2403 else
2404 sc->txslot[lcv].bfree = (val + (EN_TXSZ*1024)) - sc->txslot[lcv].cur;
2405 #ifdef EN_DEBUG
2406 kprintf("%s: tx%d: trasmit done. %d bytes now free in buffer\n",
2407 sc->sc_dev.dv_xname, lcv, sc->txslot[lcv].bfree);
2408 #endif
2409 }
2410 }
2411 }
2412
2413 if (reg & MID_INT_DMA_TX) { /* TX DMA done! */
2414
2415 /*
2416 * check for TX DMA complete, if detected then this means that some DTQs
2417 * are now free. it also means some indma mbufs can be freed.
2418 * if we needed DTQs, kick all channels.
2419 */
2420 val = EN_READ(sc, MID_DMA_RDTX); /* chip's current location */
2421 idx = MID_DTQ_A2REG(sc->dtq_chip);/* where we last saw chip */
2422 if (sc->need_dtqs) {
2423 kick = MID_NTX_CH - 1; /* assume power of 2, kick all! */
2424 sc->need_dtqs = 0; /* recalculated in "kick" loop below */
2425 #ifdef EN_DEBUG
2426 kprintf("%s: cleared need DTQ condition\n", sc->sc_dev.dv_xname);
2427 #endif
2428 }
2429 while (idx != val) {
2430 sc->dtq_free++;
2431 if ((dtq = sc->dtq[idx]) != 0) {
2432 sc->dtq[idx] = 0; /* don't forget to zero it out when done */
2433 slot = EN_DQ_SLOT(dtq);
2434 IF_DEQUEUE(&sc->txslot[slot].indma, m);
2435 if (!m) panic("enintr: dtqsync");
2436 sc->txslot[slot].mbsize -= EN_DQ_LEN(dtq);
2437 #ifdef EN_DEBUG
2438 kprintf("%s: tx%d: free %d dma bytes, mbsize now %d\n",
2439 sc->sc_dev.dv_xname, slot, EN_DQ_LEN(dtq),
2440 sc->txslot[slot].mbsize);
2441 #endif
2442 m_freem(m);
2443 }
2444 EN_WRAPADD(0, MID_DTQ_N, idx, 1);
2445 };
2446 sc->dtq_chip = MID_DTQ_REG2A(val); /* sync softc */
2447 }
2448
2449
2450 /*
2451 * kick xmit channels as needed
2452 */
2453
2454 if (kick) {
2455 #ifdef EN_DEBUG
2456 kprintf("%s: tx kick mask = 0x%x\n", sc->sc_dev.dv_xname, kick);
2457 #endif
2458 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2459 if ((kick & mask) && sc->txslot[lcv].q.ifq_head) {
2460 en_txdma(sc, lcv); /* kick it! */
2461 }
2462 } /* for each slot */
2463 } /* if kick */
2464
2465
2466 /*******************
2467 * recv interrupts *
2468 ******************/
2469
2470 /*
2471 * check for RX DMA complete, and pass the data "upstairs"
2472 */
2473
2474 if (reg & MID_INT_DMA_RX) {
2475 val = EN_READ(sc, MID_DMA_RDRX); /* chip's current location */
2476 idx = MID_DRQ_A2REG(sc->drq_chip);/* where we last saw chip */
2477 while (idx != val) {
2478 sc->drq_free++;
2479 if ((drq = sc->drq[idx]) != 0) {
2480 sc->drq[idx] = 0; /* don't forget to zero it out when done */
2481 slot = EN_DQ_SLOT(drq);
2482 if (EN_DQ_LEN(drq) == 0) { /* "JK" trash DMA? */
2483 m = NULL;
2484 } else {
2485 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
2486 if (!m)
2487 panic("enintr: drqsync: %s: lost mbuf in slot %d!",
2488 sc->sc_dev.dv_xname, slot);
2489 }
2490 /* do something with this mbuf */
2491 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) { /* drain? */
2492 if (m)
2493 m_freem(m);
2494 vci = sc->rxslot[slot].atm_vci;
2495 if (sc->rxslot[slot].indma.ifq_head == NULL &&
2496 sc->rxslot[slot].q.ifq_head == NULL &&
2497 (EN_READ(sc, MID_VC(vci)) & MIDV_INSERVICE) == 0 &&
2498 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2499 sc->rxslot[slot].oth_flags = ENOTHER_FREE; /* done drain */
2500 sc->rxslot[slot].atm_vci = RX_NONE;
2501 sc->rxvc2slot[vci] = RX_NONE;
2502 #ifdef EN_DEBUG
2503 kprintf("%s: rx%d: VCI %d now free\n", sc->sc_dev.dv_xname,
2504 slot, vci);
2505 #endif
2506 }
2507 } else if (m != NULL) {
2508 ATM_PH_FLAGS(&ah) = sc->rxslot[slot].atm_flags;
2509 ATM_PH_VPI(&ah) = 0;
2510 ATM_PH_SETVCI(&ah, sc->rxslot[slot].atm_vci);
2511 #ifdef EN_DEBUG
2512 kprintf("%s: rx%d: rxvci%d: atm_input, mbuf %p, len %d, hand %p\n",
2513 sc->sc_dev.dv_xname, slot, sc->rxslot[slot].atm_vci, m,
2514 EN_DQ_LEN(drq), sc->rxslot[slot].rxhand);
2515 #endif
2516
2517 ifp = &sc->enif;
2518 ifp->if_ipackets++;
2519
2520 BPF_MTAP(ifp, m);
2521
2522 atm_input(ifp, &ah, m, sc->rxslot[slot].rxhand);
2523 }
2524
2525 }
2526 EN_WRAPADD(0, MID_DRQ_N, idx, 1);
2527 };
2528 sc->drq_chip = MID_DRQ_REG2A(val); /* sync softc */
2529
2530 if (sc->need_drqs) { /* true if we had a DRQ shortage */
2531 need_softserv = 1;
2532 sc->need_drqs = 0;
2533 #ifdef EN_DEBUG
2534 kprintf("%s: cleared need DRQ condition\n", sc->sc_dev.dv_xname);
2535 #endif
2536 }
2537 }
2538
2539 /*
2540 * handle service interrupts
2541 */
2542
2543 if (reg & MID_INT_SERVICE) {
2544 chip = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
2545
2546 while (sc->hwslistp != chip) {
2547
2548 /* fetch and remove it from hardware service list */
2549 vci = EN_READ(sc, sc->hwslistp);
2550 EN_WRAPADD(MID_SLOFF, MID_SLEND, sc->hwslistp, 4);/* advance hw ptr */
2551 slot = sc->rxvc2slot[vci];
2552 if (slot == RX_NONE) {
2553 #ifdef EN_DEBUG
2554 kprintf("%s: unexpected rx interrupt on VCI %d\n",
2555 sc->sc_dev.dv_xname, vci);
2556 #endif
2557 EN_WRITE(sc, MID_VC(vci), MIDV_TRASH); /* rx off, damn it! */
2558 continue; /* next */
2559 }
2560 EN_WRITE(sc, MID_VC(vci), sc->rxslot[slot].mode); /* remove from hwsl */
2561 EN_COUNT(sc->hwpull);
2562
2563 #ifdef EN_DEBUG
2564 kprintf("%s: pulled VCI %d off hwslist\n", sc->sc_dev.dv_xname, vci);
2565 #endif
2566
2567 /* add it to the software service list (if needed) */
2568 if ((sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2569 EN_COUNT(sc->swadd);
2570 need_softserv = 1;
2571 sc->rxslot[slot].oth_flags |= ENOTHER_SWSL;
2572 sc->swslist[sc->swsl_tail] = slot;
2573 EN_WRAPADD(0, MID_SL_N, sc->swsl_tail, 1);
2574 sc->swsl_size++;
2575 #ifdef EN_DEBUG
2576 kprintf("%s: added VCI %d to swslist\n", sc->sc_dev.dv_xname, vci);
2577 #endif
2578 }
2579 };
2580 }
2581
2582 /*
2583 * now service (function too big to include here)
2584 */
2585
2586 if (need_softserv)
2587 en_service(sc);
2588
2589 /*
2590 * keep our stats
2591 */
2592
2593 if (reg & MID_INT_DMA_OVR) {
2594 EN_COUNT(sc->dmaovr);
2595 #ifdef EN_DEBUG
2596 kprintf("%s: MID_INT_DMA_OVR\n", sc->sc_dev.dv_xname);
2597 #endif
2598 }
2599 reg = EN_READ(sc, MID_STAT);
2600 #ifdef EN_STAT
2601 sc->otrash += MID_OTRASH(reg);
2602 sc->vtrash += MID_VTRASH(reg);
2603 #endif
2604
2605 EN_INTR_RET(1); /* for us */
2606 }
2607
2608
2609 /*
2610 * en_service: handle a service interrupt
2611 *
2612 * Q: why do we need a software service list?
2613 *
2614 * A: if we remove a VCI from the hardware list and we find that we are
2615 * out of DRQs we must defer processing until some DRQs become free.
2616 * so we must remember to look at this RX VCI/slot later, but we can't
2617 * put it back on the hardware service list (since that isn't allowed).
2618 * so we instead save it on the software service list. it would be nice
2619 * if we could peek at the VCI on top of the hwservice list without removing
2620 * it, however this leads to a race condition: if we peek at it and
2621 * decide we are done with it new data could come in before we have a
2622 * chance to remove it from the hwslist. by the time we get it out of
2623 * the list the interrupt for the new data will be lost. oops!
2624 *
2625 */
2626
2627 STATIC void
2628 en_service(struct en_softc *sc)
2629 {
2630 struct mbuf *m, *tmp;
2631 u_int32_t cur, dstart, rbd, pdu, *sav, dma, bcode, count, *data, *datastop;
2632 u_int32_t start, stop, cnt, needalign;
2633 int slot, raw, aal5, llc, vci, fill, mlen, tlen, drqneed, need, needfill, end;
2634
2635 aal5 = 0; /* Silence gcc */
2636 next_vci:
2637 if (sc->swsl_size == 0) {
2638 #ifdef EN_DEBUG
2639 kprintf("%s: en_service done\n", sc->sc_dev.dv_xname);
2640 #endif
2641 return; /* >>> exit here if swsl now empty <<< */
2642 }
2643
2644 /*
2645 * get slot/vci to service
2646 */
2647
2648 slot = sc->swslist[sc->swsl_head];
2649 vci = sc->rxslot[slot].atm_vci;
2650 #ifdef EN_DIAG
2651 if (sc->rxvc2slot[vci] != slot) panic("en_service rx slot/vci sync");
2652 #endif
2653
2654 /*
2655 * determine our mode and if we've got any work to do
2656 */
2657
2658 raw = sc->rxslot[slot].oth_flags & ENOTHER_RAW;
2659 start= sc->rxslot[slot].start;
2660 stop= sc->rxslot[slot].stop;
2661 cur = sc->rxslot[slot].cur;
2662
2663 #ifdef EN_DEBUG
2664 kprintf("%s: rx%d: service vci=%d raw=%d start/stop/cur=0x%x 0x%x 0x%x\n",
2665 sc->sc_dev.dv_xname, slot, vci, raw, start, stop, cur);
2666 #endif
2667
2668 same_vci:
2669 dstart = MIDV_DSTART(EN_READ(sc, MID_DST_RP(vci)));
2670 dstart = (dstart * sizeof(u_int32_t)) + start;
2671
2672 /* check to see if there is any data at all */
2673 if (dstart == cur) {
2674 defer: /* defer processing */
2675 EN_WRAPADD(0, MID_SL_N, sc->swsl_head, 1);
2676 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
2677 sc->swsl_size--;
2678 /* >>> remove from swslist <<< */
2679 #ifdef EN_DEBUG
2680 kprintf("%s: rx%d: remove vci %d from swslist\n",
2681 sc->sc_dev.dv_xname, slot, vci);
2682 #endif
2683 goto next_vci;
2684 }
2685
2686 /*
2687 * figure out how many bytes we need
2688 * [mlen = # bytes to go in mbufs, fill = # bytes to dump (MIDDMA_JK)]
2689 */
2690
2691 if (raw) {
2692
2693 /* raw mode (aka boodi mode) */
2694 fill = 0;
2695 if (dstart > cur)
2696 mlen = dstart - cur;
2697 else
2698 mlen = (dstart + (EN_RXSZ*1024)) - cur;
2699
2700 if (mlen < sc->rxslot[slot].raw_threshold)
2701 goto defer; /* too little data to deal with */
2702
2703 } else {
2704
2705 /* normal mode */
2706 aal5 = (sc->rxslot[slot].atm_flags & ATM_PH_AAL5);
2707 llc = (aal5 && (sc->rxslot[slot].atm_flags & ATM_PH_LLCSNAP)) ? 1 : 0;
2708 rbd = EN_READ(sc, cur);
2709 if (MID_RBD_ID(rbd) != MID_RBD_STDID)
2710 panic("en_service: id mismatch");
2711
2712 if (rbd & MID_RBD_T) {
2713 mlen = 0; /* we've got trash */
2714 fill = MID_RBD_SIZE;
2715 EN_COUNT(sc->ttrash);
2716 #ifdef EN_DEBUG
2717 kprintf("RX overflow lost %d cells!\n", MID_RBD_CNT(rbd));
2718 #endif
2719 } else if (!aal5) {
2720 mlen = MID_RBD_SIZE + MID_CHDR_SIZE + MID_ATMDATASZ; /* 1 cell (ick!) */
2721 fill = 0;
2722 } else {
2723 struct ifnet *ifp;
2724
2725 tlen = (MID_RBD_CNT(rbd) * MID_ATMDATASZ) + MID_RBD_SIZE;
2726 pdu = cur + tlen - MID_PDU_SIZE;
2727 if (pdu >= stop)
2728 pdu -= (EN_RXSZ*1024);
2729 pdu = EN_READ(sc, pdu); /* get PDU in correct byte order */
2730 fill = tlen - MID_RBD_SIZE - MID_PDU_LEN(pdu);
2731 if (fill < 0 || (rbd & MID_RBD_CRCERR) != 0) {
2732 static int first = 1;
2733
2734 if (first) {
2735 kprintf("%s: %s, dropping frame\n", sc->sc_dev.dv_xname,
2736 (rbd & MID_RBD_CRCERR) ?
2737 "CRC error" : "invalid AAL5 PDU length");
2738 kprintf("%s: got %d cells (%d bytes), AAL5 len is %d bytes (pdu=0x%x)\n",
2739 sc->sc_dev.dv_xname, MID_RBD_CNT(rbd),
2740 tlen - MID_RBD_SIZE, MID_PDU_LEN(pdu), pdu);
2741 #ifndef EN_DEBUG
2742 kprintf("CRC error report disabled from now on!\n");
2743 first = 0;
2744 #endif
2745 }
2746 fill = tlen;
2747
2748 ifp = &sc->enif;
2749 ifp->if_ierrors++;
2750
2751 }
2752 mlen = tlen - fill;
2753 }
2754
2755 }
2756
2757 /*
2758 * now allocate mbufs for mlen bytes of data, if out of mbufs, trash all
2759 *
2760 * notes:
2761 * 1. it is possible that we've already allocated an mbuf for this pkt
2762 * but ran out of DRQs, in which case we saved the allocated mbuf on
2763 * "q".
2764 * 2. if we save an mbuf in "q" we store the "cur" (pointer) in the front
2765 * of the mbuf as an identity (that we can check later), and we also
2766 * store drqneed (so we don't have to recompute it).
2767 * 3. after this block of code, if m is still NULL then we ran out of mbufs
2768 */
2769
2770 m = sc->rxslot[slot].q.ifq_head;
2771 drqneed = 1;
2772 if (m) {
2773 sav = mtod(m, u_int32_t *);
2774 if (sav[0] != cur) {
2775 #ifdef EN_DEBUG
2776 kprintf("%s: rx%d: q'ed mbuf %p not ours\n",
2777 sc->sc_dev.dv_xname, slot, m);
2778 #endif
2779 m = NULL; /* wasn't ours */
2780 EN_COUNT(sc->rxqnotus);
2781 } else {
2782 EN_COUNT(sc->rxqus);
2783 IF_DEQUEUE(&sc->rxslot[slot].q, m);
2784 drqneed = sav[1];
2785 #ifdef EN_DEBUG
2786 kprintf("%s: rx%d: recovered q'ed mbuf %p (drqneed=%d)\n",
2787 sc->sc_dev.dv_xname, slot, m, drqneed);
2788 #endif
2789 }
2790 }
2791
2792 if (mlen != 0 && m == NULL) {
2793 m = en_mget(sc, mlen, &drqneed); /* allocate! */
2794 if (m == NULL) {
2795 fill += mlen;
2796 mlen = 0;
2797 EN_COUNT(sc->rxmbufout);
2798 #ifdef EN_DEBUG
2799 kprintf("%s: rx%d: out of mbufs\n", sc->sc_dev.dv_xname, slot);
2800 #endif
2801 }
2802 #ifdef EN_DEBUG
2803 kprintf("%s: rx%d: allocate mbuf %p, mlen=%d, drqneed=%d\n",
2804 sc->sc_dev.dv_xname, slot, m, mlen, drqneed);
2805 #endif
2806 }
2807
2808 #ifdef EN_DEBUG
2809 kprintf("%s: rx%d: VCI %d, mbuf_chain %p, mlen %d, fill %d\n",
2810 sc->sc_dev.dv_xname, slot, vci, m, mlen, fill);
2811 #endif
2812
2813 /*
2814 * now check to see if we've got the DRQs needed. if we are out of
2815 * DRQs we must quit (saving our mbuf, if we've got one).
2816 */
2817
2818 needfill = (fill) ? 1 : 0;
2819 if (drqneed + needfill > sc->drq_free) {
2820 sc->need_drqs = 1; /* flag condition */
2821 if (m == NULL) {
2822 EN_COUNT(sc->rxoutboth);
2823 #ifdef EN_DEBUG
2824 kprintf("%s: rx%d: out of DRQs *and* mbufs!\n", sc->sc_dev.dv_xname, slot);
2825 #endif
2826 return; /* >>> exit here if out of both mbufs and DRQs <<< */
2827 }
2828 sav = mtod(m, u_int32_t *);
2829 sav[0] = cur;
2830 sav[1] = drqneed;
2831 IF_ENQUEUE(&sc->rxslot[slot].q, m);
2832 EN_COUNT(sc->rxdrqout);
2833 #ifdef EN_DEBUG
2834 kprintf("%s: rx%d: out of DRQs\n", sc->sc_dev.dv_xname, slot);
2835 #endif
2836 return; /* >>> exit here if out of DRQs <<< */
2837 }
2838
2839 /*
2840 * at this point all resources have been allocated and we are commited
2841 * to servicing this slot.
2842 *
2843 * dma = last location we told chip about
2844 * cur = current location
2845 * mlen = space in the mbuf we want
2846 * need = bytes to xfer in (decrs to zero)
2847 * fill = how much fill we need
2848 * tlen = how much data to transfer to this mbuf
2849 * cnt/bcode/count = <same as xmit>
2850 *
2851 * 'needfill' not used after this point
2852 */
2853
2854 dma = cur; /* dma = last location we told chip about */
2855 need = roundup(mlen, sizeof(u_int32_t));
2856 fill = fill - (need - mlen); /* note: may invalidate 'needfill' */
2857
2858 for (tmp = m ; tmp != NULL && need > 0 ; tmp = tmp->m_next) {
2859 tlen = roundup(tmp->m_len, sizeof(u_int32_t)); /* m_len set by en_mget */
2860 data = mtod(tmp, u_int32_t *);
2861
2862 #ifdef EN_DEBUG
2863 kprintf("%s: rx%d: load mbuf %p, m_len=%d, m_data=%p, tlen=%d\n",
2864 sc->sc_dev.dv_xname, slot, tmp, tmp->m_len, tmp->m_data, tlen);
2865 #endif
2866
2867 /* copy data */
2868 if (EN_NORXDMA || !en_dma || tlen < EN_MINDMA) {
2869 datastop = (u_int32_t *)((u_char *) data + tlen);
2870 /* copy loop: preserve byte order!!! use READDAT */
2871 while (data != datastop) {
2872 *data = EN_READDAT(sc, cur);
2873 data++;
2874 EN_WRAPADD(start, stop, cur, 4);
2875 }
2876 need -= tlen;
2877 #ifdef EN_DEBUG
2878 kprintf("%s: rx%d: vci%d: copied %d bytes (%d left)\n",
2879 sc->sc_dev.dv_xname, slot, vci, tlen, need);
2880 #endif
2881 continue;
2882 }
2883
2884 /* DMA data (check to see if we need to sync DRQ first) */
2885 if (dma != cur) {
2886 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, 0, 0, 0);
2887 #ifdef EN_DEBUG
2888 kprintf("%s: rx%d: vci%d: drq_sync: advance pointer to %d\n",
2889 sc->sc_dev.dv_xname, slot, vci, cur);
2890 #endif
2891 }
2892
2893 #if !defined(MIDWAY_ENIONLY)
2894
2895 /*
2896 * the adaptec DMA engine is smart and handles everything for us.
2897 */
2898
2899 if (sc->is_adaptec) {
2900 need -= tlen;
2901 EN_WRAPADD(start, stop, cur, tlen);
2902 #ifdef EN_DEBUG
2903 kprintf("%s: rx%d: vci%d: adp_dma %d bytes (%d left)\n",
2904 sc->sc_dev.dv_xname, slot, vci, tlen, need);
2905 #endif
2906 end = (need == 0 && !fill) ? MID_DMA_END : 0;
2907 EN_DRQADD(sc, tlen, vci, 0, vtophys(data), mlen, slot, end);
2908 if (end)
2909 goto done;
2910 dma = cur; /* update dma pointer */
2911 continue;
2912 }
2913 #endif /* !MIDWAY_ENIONLY */
2914
2915
2916 #if !defined(MIDWAY_ADPONLY)
2917
2918 /*
2919 * the ENI DMA engine is not so smart and need more help from us
2920 */
2921
2922 /* do we need to do a DMA op to align? */
2923 if (sc->alburst &&
2924 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0) {
2925 cnt = sc->bestburstlen - needalign;
2926 if (cnt > tlen) {
2927 cnt = tlen;
2928 count = cnt / sizeof(u_int32_t);
2929 bcode = MIDDMA_WORD;
2930 } else {
2931 count = cnt / sizeof(u_int32_t);
2932 bcode = en_dmaplan[count].bcode;
2933 count = cnt >> en_dmaplan[count].divshift;
2934 }
2935 need -= cnt;
2936 EN_WRAPADD(start, stop, cur, cnt);
2937 #ifdef EN_DEBUG
2938 kprintf("%s: rx%d: vci%d: al_dma %d bytes (%d left)\n",
2939 sc->sc_dev.dv_xname, slot, vci, cnt, need);
2940 #endif
2941 tlen -= cnt;
2942 end = (need == 0 && !fill) ? MID_DMA_END : 0;
2943 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
2944 if (end)
2945 goto done;
2946 data = (u_int32_t *)((u_char *) data + cnt);
2947 }
2948
2949 /* do we need a max-sized burst? */
2950 if (tlen >= sc->bestburstlen) {
2951 count = tlen >> sc->bestburstshift;
2952 cnt = count << sc->bestburstshift;
2953 bcode = sc->bestburstcode;
2954 need -= cnt;
2955 EN_WRAPADD(start, stop, cur, cnt);
2956 #ifdef EN_DEBUG
2957 kprintf("%s: rx%d: vci%d: best_dma %d bytes (%d left)\n",
2958 sc->sc_dev.dv_xname, slot, vci, cnt, need);
2959 #endif
2960 tlen -= cnt;
2961 end = (need == 0 && !fill) ? MID_DMA_END : 0;
2962 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
2963 if (end)
2964 goto done;
2965 data = (u_int32_t *)((u_char *) data + cnt);
2966 }
2967
2968 /* do we need to do a cleanup burst? */
2969 if (tlen) {
2970 count = tlen / sizeof(u_int32_t);
2971 bcode = en_dmaplan[count].bcode;
2972 count = tlen >> en_dmaplan[count].divshift;
2973 need -= tlen;
2974 EN_WRAPADD(start, stop, cur, tlen);
2975 #ifdef EN_DEBUG
2976 kprintf("%s: rx%d: vci%d: cleanup_dma %d bytes (%d left)\n",
2977 sc->sc_dev.dv_xname, slot, vci, tlen, need);
2978 #endif
2979 end = (need == 0 && !fill) ? MID_DMA_END : 0;
2980 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
2981 if (end)
2982 goto done;
2983 }
2984
2985 dma = cur; /* update dma pointer */
2986
2987 #endif /* !MIDWAY_ADPONLY */
2988
2989 }
2990
2991 /* skip the end */
2992 if (fill || dma != cur) {
2993 #ifdef EN_DEBUG
2994 if (fill)
2995 kprintf("%s: rx%d: vci%d: skipping %d bytes of fill\n",
2996 sc->sc_dev.dv_xname, slot, vci, fill);
2997 else
2998 kprintf("%s: rx%d: vci%d: syncing chip from 0x%x to 0x%x [cur]\n",
2999 sc->sc_dev.dv_xname, slot, vci, dma, cur);
3000 #endif
3001 EN_WRAPADD(start, stop, cur, fill);
3002 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, mlen,
3003 slot, MID_DMA_END);
3004 /* dma = cur; */ /* not necessary since we are done */
3005 }
3006
3007 /*
3008 * done, remove stuff we don't want to pass up:
3009 * raw mode (boodi mode): pass everything up for later processing
3010 * aal5: remove RBD
3011 * aal0: remove RBD + cell header
3012 */
3013
3014 done:
3015 if (m) {
3016 if (!raw) {
3017 cnt = MID_RBD_SIZE;
3018 if (!aal5) cnt += MID_CHDR_SIZE;
3019 m->m_len -= cnt; /* chop! */
3020 m->m_pkthdr.len -= cnt;
3021 m->m_data += cnt;
3022 }
3023 IF_ENQUEUE(&sc->rxslot[slot].indma, m);
3024 }
3025 sc->rxslot[slot].cur = cur; /* update master copy of 'cur' */
3026
3027 #ifdef EN_DEBUG
3028 kprintf("%s: rx%d: vci%d: DONE! cur now =0x%x\n",
3029 sc->sc_dev.dv_xname, slot, vci, cur);
3030 #endif
3031
3032 goto same_vci; /* get next packet in this slot */
3033 }
3034
3035
3036 #ifdef EN_DDBHOOK
3037 /*
3038 * functions we can call from ddb
3039 */
3040
3041 /*
3042 * en_dump: dump the state
3043 */
3044
3045 #define END_SWSL 0x00000040 /* swsl state */
3046 #define END_DRQ 0x00000020 /* drq state */
3047 #define END_DTQ 0x00000010 /* dtq state */
3048 #define END_RX 0x00000008 /* rx state */
3049 #define END_TX 0x00000004 /* tx state */
3050 #define END_MREGS 0x00000002 /* registers */
3051 #define END_STATS 0x00000001 /* dump stats */
3052
3053 #define END_BITS "\20\7SWSL\6DRQ\5DTQ\4RX\3TX\2MREGS\1STATS"
3054
3055 /* Do not staticize - meant for calling from DDB! */
3056 int
3057 en_dump(int unit, int level)
3058 {
3059 struct en_softc *sc;
3060 int lcv, cnt, slot;
3061 u_int32_t ptr, reg;
3062
3063 for (lcv = 0 ; lcv < en_cd.cd_ndevs ; lcv++) {
3064 sc = (struct en_softc *) en_cd.cd_devs[lcv];
3065 if (sc == NULL) continue;
3066 if (unit != -1 && unit != lcv)
3067 continue;
3068
3069 kprintf("dumping device %s at level 0x%b\n", sc->sc_dev.dv_xname, level,
3070 END_BITS);
3071
3072 if (sc->dtq_us == 0) {
3073 kprintf("<hasn't been en_init'd yet>\n");
3074 continue;
3075 }
3076
3077 if (level & END_STATS) {
3078 kprintf(" en_stats:\n");
3079 kprintf(" %d mfix (%d failed); %d/%d head/tail byte DMAs, %d flushes\n",
3080 sc->mfix, sc->mfixfail, sc->headbyte, sc->tailbyte, sc->tailflush);
3081 kprintf(" %d rx dma overflow interrupts\n", sc->dmaovr);
3082 kprintf(" %d times we ran out of TX space and stalled\n",
3083 sc->txoutspace);
3084 kprintf(" %d times we ran out of DTQs\n", sc->txdtqout);
3085 kprintf(" %d times we launched a packet\n", sc->launch);
3086 kprintf(" %d times we launched without on-board header\n", sc->lheader);
3087 kprintf(" %d times we launched without on-board tail\n", sc->ltail);
3088 kprintf(" %d times we pulled the hw service list\n", sc->hwpull);
3089 kprintf(" %d times we pushed a vci on the sw service list\n",
3090 sc->swadd);
3091 kprintf(" %d times RX pulled an mbuf from Q that wasn't ours\n",
3092 sc->rxqnotus);
3093 kprintf(" %d times RX pulled a good mbuf from Q\n", sc->rxqus);
3094 kprintf(" %d times we ran out of mbufs *and* DRQs\n", sc->rxoutboth);
3095 kprintf(" %d times we ran out of DRQs\n", sc->rxdrqout);
3096
3097 kprintf(" %d trasmit packets dropped due to mbsize\n", sc->txmbovr);
3098 kprintf(" %d cells trashed due to turned off rxvc\n", sc->vtrash);
3099 kprintf(" %d cells trashed due to totally full buffer\n", sc->otrash);
3100 kprintf(" %d cells trashed due almost full buffer\n", sc->ttrash);
3101 kprintf(" %d rx mbuf allocation failures\n", sc->rxmbufout);
3102 #if defined(NATM) && defined(NATM_STAT)
3103 kprintf(" natmintr so_rcv: ok/drop cnt: %d/%d, ok/drop bytes: %d/%d\n",
3104 natm_sookcnt, natm_sodropcnt, natm_sookbytes, natm_sodropbytes);
3105 #endif
3106 }
3107
3108 if (level & END_MREGS) {
3109 kprintf("mregs:\n");
3110 kprintf("resid = 0x%lx\n", (u_long)EN_READ(sc, MID_RESID));
3111 kprintf("interrupt status = 0x%b\n",
3112 (int)EN_READ(sc, MID_INTSTAT), MID_INTBITS);
3113 kprintf("interrupt enable = 0x%b\n",
3114 (int)EN_READ(sc, MID_INTENA), MID_INTBITS);
3115 kprintf("mcsr = 0x%b\n", (int)EN_READ(sc, MID_MAST_CSR), MID_MCSRBITS);
3116 kprintf("serv_write = [chip=%ld] [us=%d]\n",
3117 (long)EN_READ(sc, MID_SERV_WRITE),
3118 MID_SL_A2REG(sc->hwslistp));
3119 kprintf("dma addr = 0x%lx\n", (u_long)EN_READ(sc, MID_DMA_ADDR));
3120 kprintf("DRQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3121 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX)),
3122 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_WRRX)),
3123 sc->drq_chip, sc->drq_us);
3124 kprintf("DTQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3125 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX)),
3126 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_WRTX)),
3127 sc->dtq_chip, sc->dtq_us);
3128
3129 kprintf(" unusual txspeeds: ");
3130 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3131 if (sc->txspeed[cnt])
3132 kprintf(" vci%d=0x%x", cnt, sc->txspeed[cnt]);
3133 kprintf("\n");
3134
3135 kprintf(" rxvc slot mappings: ");
3136 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3137 if (sc->rxvc2slot[cnt] != RX_NONE)
3138 kprintf(" %d->%d", cnt, sc->rxvc2slot[cnt]);
3139 kprintf("\n");
3140
3141 }
3142
3143 if (level & END_TX) {
3144 kprintf("tx:\n");
3145 for (slot = 0 ; slot < EN_NTX; slot++) {
3146 kprintf("tx%d: start/stop/cur=0x%x/0x%x/0x%x [%d] ", slot,
3147 sc->txslot[slot].start, sc->txslot[slot].stop, sc->txslot[slot].cur,
3148 (sc->txslot[slot].cur - sc->txslot[slot].start)/4);
3149 kprintf("mbsize=%d, bfree=%d\n", sc->txslot[slot].mbsize,
3150 sc->txslot[slot].bfree);
3151 kprintf("txhw: base_address=0x%lx, size=%ld, read=%ld, descstart=%ld\n",
3152 (u_long)MIDX_BASE(EN_READ(sc, MIDX_PLACE(slot))),
3153 (u_long)MIDX_SZ(EN_READ(sc, MIDX_PLACE(slot))),
3154 (long)EN_READ(sc, MIDX_READPTR(slot)),
3155 (long)EN_READ(sc, MIDX_DESCSTART(slot)));
3156 }
3157 }
3158
3159 if (level & END_RX) {
3160 kprintf(" recv slots:\n");
3161 for (slot = 0 ; slot < sc->en_nrx; slot++) {
3162 kprintf("rx%d: vci=%d: start/stop/cur=0x%x/0x%x/0x%x ", slot,
3163 sc->rxslot[slot].atm_vci, sc->rxslot[slot].start,
3164 sc->rxslot[slot].stop, sc->rxslot[slot].cur);
3165 kprintf("mode=0x%x, atm_flags=0x%x, oth_flags=0x%x\n",
3166 sc->rxslot[slot].mode, sc->rxslot[slot].atm_flags,
3167 sc->rxslot[slot].oth_flags);
3168 kprintf("RXHW: mode=0x%lx, DST_RP=0x%lx, WP_ST_CNT=0x%lx\n",
3169 (u_long)EN_READ(sc, MID_VC(sc->rxslot[slot].atm_vci)),
3170 (u_long)EN_READ(sc, MID_DST_RP(sc->rxslot[slot].atm_vci)),
3171 (u_long)EN_READ(sc, MID_WP_ST_CNT(sc->rxslot[slot].atm_vci)));
3172 }
3173 }
3174
3175 if (level & END_DTQ) {
3176 kprintf(" dtq [need_dtqs=%d,dtq_free=%d]:\n",
3177 sc->need_dtqs, sc->dtq_free);
3178 ptr = sc->dtq_chip;
3179 while (ptr != sc->dtq_us) {
3180 reg = EN_READ(sc, ptr);
3181 kprintf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3182 sc->dtq[MID_DTQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_TXCHAN(reg),
3183 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3184 (u_long)EN_READ(sc, ptr+4));
3185 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, ptr, 8);
3186 }
3187 }
3188
3189 if (level & END_DRQ) {
3190 kprintf(" drq [need_drqs=%d,drq_free=%d]:\n",
3191 sc->need_drqs, sc->drq_free);
3192 ptr = sc->drq_chip;
3193 while (ptr != sc->drq_us) {
3194 reg = EN_READ(sc, ptr);
3195 kprintf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3196 sc->drq[MID_DRQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_RXVCI(reg),
3197 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3198 (u_long)EN_READ(sc, ptr+4));
3199 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, ptr, 8);
3200 }
3201 }
3202
3203 if (level & END_SWSL) {
3204 kprintf(" swslist [size=%d]: ", sc->swsl_size);
3205 for (cnt = sc->swsl_head ; cnt != sc->swsl_tail ;
3206 cnt = (cnt + 1) % MID_SL_N)
3207 kprintf("0x%x ", sc->swslist[cnt]);
3208 kprintf("\n");
3209 }
3210 }
3211 return(0);
3212 }
3213
3214 /*
3215 * en_dumpmem: dump the memory
3216 */
3217
3218 /* Do not staticize - meant for calling from DDB! */
3219 int
3220 en_dumpmem(int unit, int addr, int len)
3221 {
3222 struct en_softc *sc;
3223 u_int32_t reg;
3224
3225 if (unit < 0 || unit > en_cd.cd_ndevs ||
3226 (sc = (struct en_softc *) en_cd.cd_devs[unit]) == NULL) {
3227 kprintf("invalid unit number: %d\n", unit);
3228 return(0);
3229 }
3230 addr = addr & ~3;
3231 if (addr < MID_RAMOFF || addr + len*4 > MID_MAXOFF || len <= 0) {
3232 kprintf("invalid addr/len number: %d, %d\n", addr, len);
3233 return(0);
3234 }
3235 kprintf("dumping %d words starting at offset 0x%x\n", len, addr);
3236 while (len--) {
3237 reg = EN_READ(sc, addr);
3238 kprintf("mem[0x%x] = 0x%x\n", addr, reg);
3239 addr += 4;
3240 }
3241 return(0);
3242 }
3243 #endif
DragonFly BSD