2 10 second timeout in CAM
7 DELAY's might tsleep, so interrupts might run. fix poll loop to detect
8 completion via other interrupts.
10 Locking serialize_enter/exit. Lots of recursion. Needs help. Use
11 lockmgr()? Needs to be converted to per-port locking, also.
13 Port multiplier support (basics are now in)
15 Simulate various mode pages (serial number access and so forth).
17 NOTE RACE: When stopping a port explicitly which has not self stopped,
18 i.e. CR is still on, we can race command completion and not have a good
19 idea what bits to reload into CI etc to restart the commands that
20 were running. This should only be done if we intend to reset the port.
22 NOTE RACE: A transient IFS interrupt (fatal phy/protocol error) can occur
23 when soft-resetting through a port multiplier, between the first and second
24 FISes. We need to be able to lock access to the port.
26 ------ serial number -----------
30 name type serialnumber
36 ------ Misc probe info --------
39 <S64A,NCQ,SSNTF,SALP,SAL,SCLO,PMD,SSC,PSC,CCCS,EMS>,
40 6 ports, 32 tags/port, gen 1 (1.5Gbps) and 2 (3Gbps)
42 ahci0: AHCI 1.2 capabilities 0xe3229f05
43 <S64A,NCQ,SSNTF,SAL,SCLO,SPM,PMD>, 6 ports, 32 tags/port, gen 1 (1.5Gbps) and 2 (3Gbps)
45 0xf722ff83<S64A,NCQ,SSNTF,SMPS,SALP,SAL,SCLO,SPM,PMD,SSC,PSC,CCCS> 4 ports, 32
48 Chipsets supporting FBSS (FIS-Based Switching):
52 ---------------------------
56 EEEEEEEE HHHHLLLL NIRxxxxx FFFFFFFF
57 rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr (reserved)
63 H4 Status hi (bit 3 is 'r' bit?)
64 L4 Status Lo (bit 3 is 'r' bit?)
67 ATAPI/DISK notification: Word78 of IDENTIFY,
68 Use SET FEATURES to set.
70 IDENTIFY DEVICE Changed in SATA 2:
72 Word 75 4:0 Max Queue depth
74 Word 76 9 Supports IPM requests
82 Word 78 4 supports in-order data delivery
83 3 supports IPMfrom device
84 2 supports DMA setup AA opt
85 1 supports non-zero buffer offssets in DMA setup
88 Word 79 (sata features enabled)
91 Device configuration overlay
92 Word 0-7 Defined by ATA
93 Word 8 3 suports async notification
95 1 supports nz buffer offsets in DMA setup FIS
97 Word 9 reserved for SATA
98 10-255 as defined by ATA
102 Feature 10h Enable use of SATA feature
103 feature 90h Disable use of SATA feature
105 sector count register contains specific feature to enable
107 01 No zero buffer offset in DMA setup fis
108 02 DMA setup fis AA opt
109 03 device initated power state transitions
110 04 guaranteed in-order data delivery
111 05 Asynchronous notification
120 4 SNotification <----