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[dragonfly.git] / sys / dev / drm / i915_drv.h
blobaea71d94219fefdcf7ef42511bc9e90133b78d02
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 * $DragonFly: src/sys/dev/drm/i915_drv.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
29 */
30
31 #ifndef _I915_DRV_H_
32 #define _I915_DRV_H_
33
34 /* General customization:
35 */
36
37 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
38
39 #define DRIVER_NAME "i915"
40 #define DRIVER_DESC "Intel Graphics"
41 #define DRIVER_DATE "20070209"
42
43 #if defined(__linux__)
44 #define I915_HAVE_FENCE
45 #define I915_HAVE_BUFFER
46 #endif
47
48 /* Interface history:
49 *
50 * 1.1: Original.
51 * 1.2: Add Power Management
52 * 1.3: Add vblank support
53 * 1.4: Fix cmdbuffer path, add heap destroy
54 * 1.5: Add vblank pipe configuration
55 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
56 * - Support vertical blank on secondary display pipe
57 * 1.8: New ioctl for ARB_Occlusion_Query
58 * 1.9: Usable page flipping and triple buffering
59 * 1.10: Plane/pipe disentangling
60 * 1.11: TTM superioctl
61 * 1.12: TTM relocation optimization
62 */
63 #define DRIVER_MAJOR 1
64 #if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER)
65 #define DRIVER_MINOR 12
66 #else
67 #define DRIVER_MINOR 6
68 #endif
69 #define DRIVER_PATCHLEVEL 0
70
71 #ifdef I915_HAVE_BUFFER
72 #define I915_MAX_VALIDATE_BUFFERS 4096
73 #endif
74
75 typedef struct _drm_i915_ring_buffer {
76 int tail_mask;
77 unsigned long Start;
78 unsigned long End;
79 unsigned long Size;
80 u8 *virtual_start;
81 int head;
82 int tail;
83 int space;
84 drm_local_map_t map;
85 } drm_i915_ring_buffer_t;
86
87 struct mem_block {
88 struct mem_block *next;
89 struct mem_block *prev;
90 int start;
91 int size;
92 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
93 };
94
95 typedef struct _drm_i915_vbl_swap {
96 struct list_head head;
97 drm_drawable_t drw_id;
98 unsigned int plane;
99 unsigned int sequence;
100 int flip;
101 } drm_i915_vbl_swap_t;
102
103 typedef struct drm_i915_private {
104 drm_local_map_t *sarea;
105 drm_local_map_t *mmio_map;
106
107 drm_i915_sarea_t *sarea_priv;
108 drm_i915_ring_buffer_t ring;
109
110 drm_dma_handle_t *status_page_dmah;
111 void *hw_status_page;
112 dma_addr_t dma_status_page;
113 uint32_t counter;
114 unsigned int status_gfx_addr;
115 drm_local_map_t hws_map;
116
117 unsigned int cpp;
118 int use_mi_batchbuffer_start;
119
120 wait_queue_head_t irq_queue;
121 atomic_t irq_received;
122 atomic_t irq_emitted;
123
124 int tex_lru_log_granularity;
125 int allow_batchbuffer;
126 struct mem_block *agp_heap;
127 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
128 int vblank_pipe;
129 DRM_SPINTYPE user_irq_lock;
130 int user_irq_refcount;
131 int fence_irq_on;
132 uint32_t irq_enable_reg;
133 int irq_enabled;
134
135 #ifdef I915_HAVE_FENCE
136 uint32_t flush_sequence;
137 uint32_t flush_flags;
138 uint32_t flush_pending;
139 uint32_t saved_flush_status;
140 #endif
141 #ifdef I915_HAVE_BUFFER
142 void *agp_iomap;
143 unsigned int max_validate_buffers;
144 struct mutex cmdbuf_mutex;
145 #endif
146
147 DRM_SPINTYPE swaps_lock;
148 drm_i915_vbl_swap_t vbl_swaps;
149 unsigned int swaps_pending;
150
151 /* Register state */
152 u8 saveLBB;
153 u32 saveDSPACNTR;
154 u32 saveDSPBCNTR;
155 u32 savePIPEACONF;
156 u32 savePIPEBCONF;
157 u32 savePIPEASRC;
158 u32 savePIPEBSRC;
159 u32 saveFPA0;
160 u32 saveFPA1;
161 u32 saveDPLL_A;
162 u32 saveDPLL_A_MD;
163 u32 saveHTOTAL_A;
164 u32 saveHBLANK_A;
165 u32 saveHSYNC_A;
166 u32 saveVTOTAL_A;
167 u32 saveVBLANK_A;
168 u32 saveVSYNC_A;
169 u32 saveBCLRPAT_A;
170 u32 saveDSPASTRIDE;
171 u32 saveDSPASIZE;
172 u32 saveDSPAPOS;
173 u32 saveDSPABASE;
174 u32 saveDSPASURF;
175 u32 saveDSPATILEOFF;
176 u32 savePFIT_PGM_RATIOS;
177 u32 saveBLC_PWM_CTL;
178 u32 saveBLC_PWM_CTL2;
179 u32 saveFPB0;
180 u32 saveFPB1;
181 u32 saveDPLL_B;
182 u32 saveDPLL_B_MD;
183 u32 saveHTOTAL_B;
184 u32 saveHBLANK_B;
185 u32 saveHSYNC_B;
186 u32 saveVTOTAL_B;
187 u32 saveVBLANK_B;
188 u32 saveVSYNC_B;
189 u32 saveBCLRPAT_B;
190 u32 saveDSPBSTRIDE;
191 u32 saveDSPBSIZE;
192 u32 saveDSPBPOS;
193 u32 saveDSPBBASE;
194 u32 saveDSPBSURF;
195 u32 saveDSPBTILEOFF;
196 u32 saveVCLK_DIVISOR_VGA0;
197 u32 saveVCLK_DIVISOR_VGA1;
198 u32 saveVCLK_POST_DIV;
199 u32 saveVGACNTRL;
200 u32 saveADPA;
201 u32 saveLVDS;
202 u32 saveLVDSPP_ON;
203 u32 saveLVDSPP_OFF;
204 u32 saveDVOA;
205 u32 saveDVOB;
206 u32 saveDVOC;
207 u32 savePP_ON;
208 u32 savePP_OFF;
209 u32 savePP_CONTROL;
210 u32 savePP_CYCLE;
211 u32 savePFIT_CONTROL;
212 u32 save_palette_a[256];
213 u32 save_palette_b[256];
214 u32 saveFBC_CFB_BASE;
215 u32 saveFBC_LL_BASE;
216 u32 saveFBC_CONTROL;
217 u32 saveFBC_CONTROL2;
218 u32 saveSWF0[16];
219 u32 saveSWF1[16];
220 u32 saveSWF2[3];
221 u8 saveMSR;
222 u8 saveSR[8];
223 u8 saveGR[24];
224 u8 saveAR_INDEX;
225 u8 saveAR[20];
226 u8 saveDACMASK;
227 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
228 u8 saveCR[36];
229 } drm_i915_private_t;
230
231 enum intel_chip_family {
232 CHIP_I8XX = 0x01,
233 CHIP_I9XX = 0x02,
234 CHIP_I915 = 0x04,
235 CHIP_I965 = 0x08,
236 };
237
238 extern struct drm_ioctl_desc i915_ioctls[];
239 extern int i915_max_ioctl;
240
241 /* i915_dma.c */
242 extern void i915_kernel_lost_context(struct drm_device * dev);
243 extern int i915_driver_load(struct drm_device *, unsigned long flags);
244 extern int i915_driver_unload(struct drm_device *);
245 extern void i915_driver_lastclose(struct drm_device * dev);
246 extern void i915_driver_preclose(struct drm_device *dev,
247 struct drm_file *file_priv);
248 extern int i915_driver_device_is_agp(struct drm_device * dev);
249 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
250 unsigned long arg);
251 extern void i915_emit_breadcrumb(struct drm_device *dev);
252 extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync);
253 extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush);
254 extern int i915_driver_firstopen(struct drm_device *dev);
255
256 /* i915_irq.c */
257 extern int i915_irq_emit(struct drm_device *dev, void *data,
258 struct drm_file *file_priv);
259 extern int i915_irq_wait(struct drm_device *dev, void *data,
260 struct drm_file *file_priv);
261
262 extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
263 extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
264 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
265 extern void i915_driver_irq_preinstall(struct drm_device * dev);
266 extern void i915_driver_irq_postinstall(struct drm_device * dev);
267 extern void i915_driver_irq_uninstall(struct drm_device * dev);
268 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
269 struct drm_file *file_priv);
270 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
271 struct drm_file *file_priv);
272 extern int i915_emit_irq(struct drm_device *dev);
273 extern void i915_user_irq_on(drm_i915_private_t *dev_priv);
274 extern void i915_user_irq_off(drm_i915_private_t *dev_priv);
275 extern int i915_vblank_swap(struct drm_device *dev, void *data,
276 struct drm_file *file_priv);
277
278 /* i915_mem.c */
279 extern int i915_mem_alloc(struct drm_device *dev, void *data,
280 struct drm_file *file_priv);
281 extern int i915_mem_free(struct drm_device *dev, void *data,
282 struct drm_file *file_priv);
283 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
284 struct drm_file *file_priv);
285 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
286 struct drm_file *file_priv);
287 extern void i915_mem_takedown(struct mem_block **heap);
288 extern void i915_mem_release(struct drm_device * dev,
289 struct drm_file *file_priv,
290 struct mem_block *heap);
291 #ifdef I915_HAVE_FENCE
292 /* i915_fence.c */
293
294
295 extern void i915_fence_handler(struct drm_device *dev);
296 extern int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class,
297 uint32_t flags,
298 uint32_t *sequence,
299 uint32_t *native_type);
300 extern void i915_poke_flush(struct drm_device *dev, uint32_t class);
301 extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);
302 #endif
303
304 #ifdef I915_HAVE_BUFFER
305 /* i915_buffer.c */
306 extern struct drm_ttm_backend *i915_create_ttm_backend_entry(struct drm_device *dev);
307 extern int i915_fence_type(struct drm_buffer_object *bo, uint32_t *fclass,
308 uint32_t *type);
309 extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
310 extern int i915_init_mem_type(struct drm_device *dev, uint32_t type,
311 struct drm_mem_type_manager *man);
312 extern uint64_t i915_evict_flags(struct drm_buffer_object *bo);
313 extern int i915_move(struct drm_buffer_object *bo, int evict,
314 int no_wait, struct drm_bo_mem_reg *new_mem);
315 void i915_flush_ttm(struct drm_ttm *ttm);
316 #endif
317
318 #ifdef __linux__
319 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
320 extern void intel_init_chipset_flush_compat(struct drm_device *dev);
321 extern void intel_fini_chipset_flush_compat(struct drm_device *dev);
322 #endif
323 #endif
324
325 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
326 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
327 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
328 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
329
330 #define I915_VERBOSE 0
331
332 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
333 volatile char *virt;
334
335 #define BEGIN_LP_RING(n) do { \
336 if (I915_VERBOSE) \
337 DRM_DEBUG("BEGIN_LP_RING(%d)\n", \
338 (n)); \
339 if (dev_priv->ring.space < (n)*4) \
340 i915_wait_ring(dev, (n)*4, __FUNCTION__); \
341 outcount = 0; \
342 outring = dev_priv->ring.tail; \
343 ringmask = dev_priv->ring.tail_mask; \
344 virt = dev_priv->ring.virtual_start; \
345 } while (0)
346
347 #define OUT_RING(n) do { \
348 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
349 *(volatile unsigned int *)(virt + outring) = (n); \
350 outcount++; \
351 outring += 4; \
352 outring &= ringmask; \
353 } while (0)
354
355 #define ADVANCE_LP_RING() do { \
356 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
357 dev_priv->ring.tail = outring; \
358 dev_priv->ring.space -= outcount * 4; \
359 I915_WRITE(LP_RING + RING_TAIL, outring); \
360 } while(0)
361
362 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
363
364 /* Extended config space */
365 #define LBB 0xf4
366
367 /* VGA stuff */
368
369 #define VGA_ST01_MDA 0x3ba
370 #define VGA_ST01_CGA 0x3da
371
372 #define VGA_MSR_WRITE 0x3c2
373 #define VGA_MSR_READ 0x3cc
374 #define VGA_MSR_MEM_EN (1<<1)
375 #define VGA_MSR_CGA_MODE (1<<0)
376
377 #define VGA_SR_INDEX 0x3c4
378 #define VGA_SR_DATA 0x3c5
379
380 #define VGA_AR_INDEX 0x3c0
381 #define VGA_AR_VID_EN (1<<5)
382 #define VGA_AR_DATA_WRITE 0x3c0
383 #define VGA_AR_DATA_READ 0x3c1
384
385 #define VGA_GR_INDEX 0x3ce
386 #define VGA_GR_DATA 0x3cf
387 /* GR05 */
388 #define VGA_GR_MEM_READ_MODE_SHIFT 3
389 #define VGA_GR_MEM_READ_MODE_PLANE 1
390 /* GR06 */
391 #define VGA_GR_MEM_MODE_MASK 0xc
392 #define VGA_GR_MEM_MODE_SHIFT 2
393 #define VGA_GR_MEM_A0000_AFFFF 0
394 #define VGA_GR_MEM_A0000_BFFFF 1
395 #define VGA_GR_MEM_B0000_B7FFF 2
396 #define VGA_GR_MEM_B0000_BFFFF 3
397
398 #define VGA_DACMASK 0x3c6
399 #define VGA_DACRX 0x3c7
400 #define VGA_DACWX 0x3c8
401 #define VGA_DACDATA 0x3c9
402
403 #define VGA_CR_INDEX_MDA 0x3b4
404 #define VGA_CR_DATA_MDA 0x3b5
405 #define VGA_CR_INDEX_CGA 0x3d4
406 #define VGA_CR_DATA_CGA 0x3d5
407
408 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
409 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
410 #define CMD_REPORT_HEAD (7<<23)
411 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
412 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
413
414 #define CMD_MI_FLUSH (0x04 << 23)
415 #define MI_NO_WRITE_FLUSH (1 << 2)
416 #define MI_READ_FLUSH (1 << 0)
417 #define MI_EXE_FLUSH (1 << 1)
418 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
419 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
420
421 /* Packet to load a register value from the ring/batch command stream:
422 */
423 #define CMD_MI_LOAD_REGISTER_IMM ((0x22 << 23)|0x1)
424
425 #define BB1_START_ADDR_MASK (~0x7)
426 #define BB1_PROTECTED (1<<0)
427 #define BB1_UNPROTECTED (0<<0)
428 #define BB2_END_ADDR_MASK (~0x7)
429
430 /* Framebuffer compression */
431 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
432 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
433 #define FBC_CONTROL 0x03208
434 #define FBC_CTL_EN (1<<31)
435 #define FBC_CTL_PERIODIC (1<<30)
436 #define FBC_CTL_INTERVAL_SHIFT (16)
437 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
438 #define FBC_CTL_STRIDE_SHIFT (5)
439 #define FBC_CTL_FENCENO (1<<0)
440 #define FBC_COMMAND 0x0320c
441 #define FBC_CMD_COMPRESS (1<<0)
442 #define FBC_STATUS 0x03210
443 #define FBC_STAT_COMPRESSING (1<<31)
444 #define FBC_STAT_COMPRESSED (1<<30)
445 #define FBC_STAT_MODIFIED (1<<29)
446 #define FBC_STAT_CURRENT_LINE (1<<0)
447 #define FBC_CONTROL2 0x03214
448 #define FBC_CTL_FENCE_DBL (0<<4)
449 #define FBC_CTL_IDLE_IMM (0<<2)
450 #define FBC_CTL_IDLE_FULL (1<<2)
451 #define FBC_CTL_IDLE_LINE (2<<2)
452 #define FBC_CTL_IDLE_DEBUG (3<<2)
453 #define FBC_CTL_CPU_FENCE (1<<1)
454 #define FBC_CTL_PLANEA (0<<0)
455 #define FBC_CTL_PLANEB (1<<0)
456 #define FBC_FENCE_OFF 0x0321b
457
458 #define FBC_LL_SIZE (1536)
459 #define FBC_LL_PAD (32)
460
461 /* Interrupt bits:
462 */
463 #define USER_INT_FLAG (1<<1)
464 #define VSYNC_PIPEB_FLAG (1<<5)
465 #define VSYNC_PIPEA_FLAG (1<<7)
466 #define HWB_OOM_FLAG (1<<13) /* binner out of memory */
467
468 #define I915REG_HWSTAM 0x02098
469 #define I915REG_INT_IDENTITY_R 0x020a4
470 #define I915REG_INT_MASK_R 0x020a8
471 #define I915REG_INT_ENABLE_R 0x020a0
472 #define I915REG_INSTPM 0x020c0
473
474 #define I915REG_PIPEASTAT 0x70024
475 #define I915REG_PIPEBSTAT 0x71024
476
477 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
478 #define I915_VBLANK_CLEAR (1UL<<1)
479
480 #define SRX_INDEX 0x3c4
481 #define SRX_DATA 0x3c5
482 #define SR01 1
483 #define SR01_SCREEN_OFF (1<<5)
484
485 #define PPCR 0x61204
486 #define PPCR_ON (1<<0)
487
488 #define DVOB 0x61140
489 #define DVOB_ON (1<<31)
490 #define DVOC 0x61160
491 #define DVOC_ON (1<<31)
492 #define LVDS 0x61180
493 #define LVDS_ON (1<<31)
494
495 #define ADPA 0x61100
496 #define ADPA_DPMS_MASK (~(3<<10))
497 #define ADPA_DPMS_ON (0<<10)
498 #define ADPA_DPMS_SUSPEND (1<<10)
499 #define ADPA_DPMS_STANDBY (2<<10)
500 #define ADPA_DPMS_OFF (3<<10)
501
502 #define NOPID 0x2094
503 #define LP_RING 0x2030
504 #define HP_RING 0x2040
505 /* The binner has its own ring buffer:
506 */
507 #define HWB_RING 0x2400
508
509 #define RING_TAIL 0x00
510 #define TAIL_ADDR 0x001FFFF8
511 #define RING_HEAD 0x04
512 #define HEAD_WRAP_COUNT 0xFFE00000
513 #define HEAD_WRAP_ONE 0x00200000
514 #define HEAD_ADDR 0x001FFFFC
515 #define RING_START 0x08
516 #define START_ADDR 0x0xFFFFF000
517 #define RING_LEN 0x0C
518 #define RING_NR_PAGES 0x001FF000
519 #define RING_REPORT_MASK 0x00000006
520 #define RING_REPORT_64K 0x00000002
521 #define RING_REPORT_128K 0x00000004
522 #define RING_NO_REPORT 0x00000000
523 #define RING_VALID_MASK 0x00000001
524 #define RING_VALID 0x00000001
525 #define RING_INVALID 0x00000000
526
527 /* Instruction parser error reg:
528 */
529 #define IPEIR 0x2088
530
531 /* Scratch pad debug 0 reg:
532 */
533 #define SCPD0 0x209c
534
535 /* Error status reg:
536 */
537 #define ESR 0x20b8
538
539 /* Secondary DMA fetch address debug reg:
540 */
541 #define DMA_FADD_S 0x20d4
542
543 /* Cache mode 0 reg.
544 * - Manipulating render cache behaviour is central
545 * to the concept of zone rendering, tuning this reg can help avoid
546 * unnecessary render cache reads and even writes (for z/stencil)
547 * at beginning and end of scene.
548 *
549 * - To change a bit, write to this reg with a mask bit set and the
550 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
551 */
552 #define Cache_Mode_0 0x2120
553 #define CM0_MASK_SHIFT 16
554 #define CM0_IZ_OPT_DISABLE (1<<6)
555 #define CM0_ZR_OPT_DISABLE (1<<5)
556 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
557 #define CM0_COLOR_EVICT_DISABLE (1<<3)
558 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
559 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
560
561
562 /* Graphics flush control. A CPU write flushes the GWB of all writes.
563 * The data is discarded.
564 */
565 #define GFX_FLSH_CNTL 0x2170
566
567 /* Binner control. Defines the location of the bin pointer list:
568 */
569 #define BINCTL 0x2420
570 #define BC_MASK (1 << 9)
571
572 /* Binned scene info.
573 */
574 #define BINSCENE 0x2428
575 #define BS_OP_LOAD (1 << 8)
576 #define BS_MASK (1 << 22)
577
578 /* Bin command parser debug reg:
579 */
580 #define BCPD 0x2480
581
582 /* Bin memory control debug reg:
583 */
584 #define BMCD 0x2484
585
586 /* Bin data cache debug reg:
587 */
588 #define BDCD 0x2488
589
590 /* Binner pointer cache debug reg:
591 */
592 #define BPCD 0x248c
593
594 /* Binner scratch pad debug reg:
595 */
596 #define BINSKPD 0x24f0
597
598 /* HWB scratch pad debug reg:
599 */
600 #define HWBSKPD 0x24f4
601
602 /* Binner memory pool reg:
603 */
604 #define BMP_BUFFER 0x2430
605 #define BMP_PAGE_SIZE_4K (0 << 10)
606 #define BMP_BUFFER_SIZE_SHIFT 1
607 #define BMP_ENABLE (1 << 0)
608
609 /* Get/put memory from the binner memory pool:
610 */
611 #define BMP_GET 0x2438
612 #define BMP_PUT 0x2440
613 #define BMP_OFFSET_SHIFT 5
614
615 /* 3D state packets:
616 */
617 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
618
619 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
620 #define SC_UPDATE_SCISSOR (0x1<<1)
621 #define SC_ENABLE_MASK (0x1<<0)
622 #define SC_ENABLE (0x1<<0)
623
624 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
625
626 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
627 #define SCI_YMIN_MASK (0xffff<<16)
628 #define SCI_XMIN_MASK (0xffff<<0)
629 #define SCI_YMAX_MASK (0xffff<<16)
630 #define SCI_XMAX_MASK (0xffff<<0)
631
632 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
633 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
634 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
635 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
636 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
637 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
638 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
639
640 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
641
642 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
643 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
644 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
645 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
646
647 #define MI_BATCH_BUFFER ((0x30<<23)|1)
648 #define MI_BATCH_BUFFER_START (0x31<<23)
649 #define MI_BATCH_BUFFER_END (0xA<<23)
650 #define MI_BATCH_NON_SECURE (1)
651
652 #define MI_BATCH_NON_SECURE_I965 (1<<8)
653
654 #define MI_WAIT_FOR_EVENT ((0x3<<23))
655 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
656 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
657 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
658
659 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
660
661 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
662 #define ASYNC_FLIP (1<<22)
663 #define DISPLAY_PLANE_A (0<<20)
664 #define DISPLAY_PLANE_B (1<<20)
665
666 /* Display regs */
667 #define DSPACNTR 0x70180
668 #define DSPBCNTR 0x71180
669 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
670
671 /* Define the region of interest for the binner:
672 */
673 #define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
674
675 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
676
677 #define BREADCRUMB_BITS 31
678 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
679
680 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
681 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
682
683 #define BLC_PWM_CTL 0x61254
684 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
685
686 #define BLC_PWM_CTL2 0x61250
687 /**
688 * This is the most significant 15 bits of the number of backlight cycles in a
689 * complete cycle of the modulated backlight control.
690 *
691 * The actual value is this field multiplied by two.
692 */
693 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
694 #define BLM_LEGACY_MODE (1 << 16)
695 /**
696 * This is the number of cycles out of the backlight modulation cycle for which
697 * the backlight is on.
698 *
699 * This field must be no greater than the number of cycles in the complete
700 * backlight modulation cycle.
701 */
702 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
703 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
704
705 #define I915_GCFGC 0xf0
706 #define I915_LOW_FREQUENCY_ENABLE (1 << 7)
707 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
708 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
709 #define I915_DISPLAY_CLOCK_MASK (7 << 4)
710
711 #define I855_HPLLCC 0xc0
712 #define I855_CLOCK_CONTROL_MASK (3 << 0)
713 #define I855_CLOCK_133_200 (0 << 0)
714 #define I855_CLOCK_100_200 (1 << 0)
715 #define I855_CLOCK_100_133 (2 << 0)
716 #define I855_CLOCK_166_250 (3 << 0)
717
718 /* p317, 319
719 */
720 #define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
721 #define VCLK2_VCO_N 0x600a
722 #define VCLK2_VCO_DIV_SEL 0x6012
723
724 #define VCLK_DIVISOR_VGA0 0x6000
725 #define VCLK_DIVISOR_VGA1 0x6004
726 #define VCLK_POST_DIV 0x6010
727 /** Selects a post divisor of 4 instead of 2. */
728 # define VGA1_PD_P2_DIV_4 (1 << 15)
729 /** Overrides the p2 post divisor field */
730 # define VGA1_PD_P1_DIV_2 (1 << 13)
731 # define VGA1_PD_P1_SHIFT 8
732 /** P1 value is 2 greater than this field */
733 # define VGA1_PD_P1_MASK (0x1f << 8)
734 /** Selects a post divisor of 4 instead of 2. */
735 # define VGA0_PD_P2_DIV_4 (1 << 7)
736 /** Overrides the p2 post divisor field */
737 # define VGA0_PD_P1_DIV_2 (1 << 5)
738 # define VGA0_PD_P1_SHIFT 0
739 /** P1 value is 2 greater than this field */
740 # define VGA0_PD_P1_MASK (0x1f << 0)
741
742 /* I830 CRTC registers */
743 #define HTOTAL_A 0x60000
744 #define HBLANK_A 0x60004
745 #define HSYNC_A 0x60008
746 #define VTOTAL_A 0x6000c
747 #define VBLANK_A 0x60010
748 #define VSYNC_A 0x60014
749 #define PIPEASRC 0x6001c
750 #define BCLRPAT_A 0x60020
751 #define VSYNCSHIFT_A 0x60028
752
753 #define HTOTAL_B 0x61000
754 #define HBLANK_B 0x61004
755 #define HSYNC_B 0x61008
756 #define VTOTAL_B 0x6100c
757 #define VBLANK_B 0x61010
758 #define VSYNC_B 0x61014
759 #define PIPEBSRC 0x6101c
760 #define BCLRPAT_B 0x61020
761 #define VSYNCSHIFT_B 0x61028
762
763 #define PP_STATUS 0x61200
764 # define PP_ON (1 << 31)
765 /**
766 * Indicates that all dependencies of the panel are on:
767 *
768 * - PLL enabled
769 * - pipe enabled
770 * - LVDS/DVOB/DVOC on
771 */
772 # define PP_READY (1 << 30)
773 # define PP_SEQUENCE_NONE (0 << 28)
774 # define PP_SEQUENCE_ON (1 << 28)
775 # define PP_SEQUENCE_OFF (2 << 28)
776 # define PP_SEQUENCE_MASK 0x30000000
777 #define PP_CONTROL 0x61204
778 # define POWER_TARGET_ON (1 << 0)
779
780 #define LVDSPP_ON 0x61208
781 #define LVDSPP_OFF 0x6120c
782 #define PP_CYCLE 0x61210
783
784 #define PFIT_CONTROL 0x61230
785 # define PFIT_ENABLE (1 << 31)
786 # define PFIT_PIPE_MASK (3 << 29)
787 # define PFIT_PIPE_SHIFT 29
788 # define VERT_INTERP_DISABLE (0 << 10)
789 # define VERT_INTERP_BILINEAR (1 << 10)
790 # define VERT_INTERP_MASK (3 << 10)
791 # define VERT_AUTO_SCALE (1 << 9)
792 # define HORIZ_INTERP_DISABLE (0 << 6)
793 # define HORIZ_INTERP_BILINEAR (1 << 6)
794 # define HORIZ_INTERP_MASK (3 << 6)
795 # define HORIZ_AUTO_SCALE (1 << 5)
796 # define PANEL_8TO6_DITHER_ENABLE (1 << 3)
797
798 #define PFIT_PGM_RATIOS 0x61234
799 # define PFIT_VERT_SCALE_MASK 0xfff00000
800 # define PFIT_HORIZ_SCALE_MASK 0x0000fff0
801
802 #define PFIT_AUTO_RATIOS 0x61238
803
804
805 #define DPLL_A 0x06014
806 #define DPLL_B 0x06018
807 # define DPLL_VCO_ENABLE (1 << 31)
808 # define DPLL_DVO_HIGH_SPEED (1 << 30)
809 # define DPLL_SYNCLOCK_ENABLE (1 << 29)
810 # define DPLL_VGA_MODE_DIS (1 << 28)
811 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
812 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */
813 # define DPLL_MODE_MASK (3 << 26)
814 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
815 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
816 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
817 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
818 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
819 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
820 /**
821 * The i830 generation, in DAC/serial mode, defines p1 as two plus this
822 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
823 */
824 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
825 /**
826 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
827 * this field (only one bit may be set).
828 */
829 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
830 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16
831 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
832 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
833 # define PLL_REF_INPUT_DREFCLK (0 << 13)
834 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
835 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
836 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
837 # define PLL_REF_INPUT_MASK (3 << 13)
838 # define PLL_LOAD_PULSE_PHASE_SHIFT 9
839 /*
840 * Parallel to Serial Load Pulse phase selection.
841 * Selects the phase for the 10X DPLL clock for the PCIe
842 * digital display port. The range is 4 to 13; 10 or more
843 * is just a flip delay. The default is 6
844 */
845 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
846 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
847
848 /**
849 * SDVO multiplier for 945G/GM. Not used on 965.
850 *
851 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
852 */
853 # define SDVO_MULTIPLIER_MASK 0x000000ff
854 # define SDVO_MULTIPLIER_SHIFT_HIRES 4
855 # define SDVO_MULTIPLIER_SHIFT_VGA 0
856
857 /** @defgroup DPLL_MD
858 * @{
859 */
860 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
861 #define DPLL_A_MD 0x0601c
862 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
863 #define DPLL_B_MD 0x06020
864 /**
865 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
866 *
867 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
868 */
869 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
870 # define DPLL_MD_UDI_DIVIDER_SHIFT 24
871 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
872 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
873 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
874 /**
875 * SDVO/UDI pixel multiplier.
876 *
877 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
878 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
879 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
880 * dummy bytes in the datastream at an increased clock rate, with both sides of
881 * the link knowing how many bytes are fill.
882 *
883 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
884 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
885 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
886 * through an SDVO command.
887 *
888 * This register field has values of multiplication factor minus 1, with
889 * a maximum multiplier of 5 for SDVO.
890 */
891 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
892 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
893 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
894 * This best be set to the default value (3) or the CRT won't work. No,
895 * I don't entirely understand what this does...
896 */
897 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
898 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
899 /** @} */
900
901 #define DPLL_TEST 0x606c
902 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
903 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
904 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
905 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
906 # define DPLLB_TEST_N_BYPASS (1 << 19)
907 # define DPLLB_TEST_M_BYPASS (1 << 18)
908 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
909 # define DPLLA_TEST_N_BYPASS (1 << 3)
910 # define DPLLA_TEST_M_BYPASS (1 << 2)
911 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
912
913 #define ADPA 0x61100
914 #define ADPA_DAC_ENABLE (1<<31)
915 #define ADPA_DAC_DISABLE 0
916 #define ADPA_PIPE_SELECT_MASK (1<<30)
917 #define ADPA_PIPE_A_SELECT 0
918 #define ADPA_PIPE_B_SELECT (1<<30)
919 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
920 #define ADPA_SETS_HVPOLARITY 0
921 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
922 #define ADPA_VSYNC_CNTL_ENABLE 0
923 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
924 #define ADPA_HSYNC_CNTL_ENABLE 0
925 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
926 #define ADPA_VSYNC_ACTIVE_LOW 0
927 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
928 #define ADPA_HSYNC_ACTIVE_LOW 0
929
930 #define FPA0 0x06040
931 #define FPA1 0x06044
932 #define FPB0 0x06048
933 #define FPB1 0x0604c
934 # define FP_N_DIV_MASK 0x003f0000
935 # define FP_N_DIV_SHIFT 16
936 # define FP_M1_DIV_MASK 0x00003f00
937 # define FP_M1_DIV_SHIFT 8
938 # define FP_M2_DIV_MASK 0x0000003f
939 # define FP_M2_DIV_SHIFT 0
940
941
942 #define PORT_HOTPLUG_EN 0x61110
943 # define SDVOB_HOTPLUG_INT_EN (1 << 26)
944 # define SDVOC_HOTPLUG_INT_EN (1 << 25)
945 # define TV_HOTPLUG_INT_EN (1 << 18)
946 # define CRT_HOTPLUG_INT_EN (1 << 9)
947 # define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
948
949 #define PORT_HOTPLUG_STAT 0x61114
950 # define CRT_HOTPLUG_INT_STATUS (1 << 11)
951 # define TV_HOTPLUG_INT_STATUS (1 << 10)
952 # define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
953 # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
954 # define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
955 # define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
956 # define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
957 # define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
958
959 #define SDVOB 0x61140
960 #define SDVOC 0x61160
961 #define SDVO_ENABLE (1 << 31)
962 #define SDVO_PIPE_B_SELECT (1 << 30)
963 #define SDVO_STALL_SELECT (1 << 29)
964 #define SDVO_INTERRUPT_ENABLE (1 << 26)
965 /**
966 * 915G/GM SDVO pixel multiplier.
967 *
968 * Programmed value is multiplier - 1, up to 5x.
969 *
970 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
971 */
972 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
973 #define SDVO_PORT_MULTIPLY_SHIFT 23
974 #define SDVO_PHASE_SELECT_MASK (15 << 19)
975 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
976 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
977 #define SDVOC_GANG_MODE (1 << 16)
978 #define SDVO_BORDER_ENABLE (1 << 7)
979 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
980 #define SDVO_DETECTED (1 << 2)
981 /* Bits to be preserved when writing */
982 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
983 #define SDVOC_PRESERVE_MASK (1 << 17)
984
985 /** @defgroup LVDS
986 * @{
987 */
988 /**
989 * This register controls the LVDS output enable, pipe selection, and data
990 * format selection.
991 *
992 * All of the clock/data pairs are force powered down by power sequencing.
993 */
994 #define LVDS 0x61180
995 /**
996 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
997 * the DPLL semantics change when the LVDS is assigned to that pipe.
998 */
999 # define LVDS_PORT_EN (1 << 31)
1000 /** Selects pipe B for LVDS data. Must be set on pre-965. */
1001 # define LVDS_PIPEB_SELECT (1 << 30)
1002
1003 /**
1004 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1005 * pixel.
1006 */
1007 # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1008 # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1009 # define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1010 /**
1011 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1012 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1013 * on.
1014 */
1015 # define LVDS_A3_POWER_MASK (3 << 6)
1016 # define LVDS_A3_POWER_DOWN (0 << 6)
1017 # define LVDS_A3_POWER_UP (3 << 6)
1018 /**
1019 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1020 * is set.
1021 */
1022 # define LVDS_CLKB_POWER_MASK (3 << 4)
1023 # define LVDS_CLKB_POWER_DOWN (0 << 4)
1024 # define LVDS_CLKB_POWER_UP (3 << 4)
1025
1026 /**
1027 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1028 * setting for whether we are in dual-channel mode. The B3 pair will
1029 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1030 */
1031 # define LVDS_B0B3_POWER_MASK (3 << 2)
1032 # define LVDS_B0B3_POWER_DOWN (0 << 2)
1033 # define LVDS_B0B3_POWER_UP (3 << 2)
1034
1035 #define PIPEACONF 0x70008
1036 #define PIPEACONF_ENABLE (1<<31)
1037 #define PIPEACONF_DISABLE 0
1038 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1039 #define I965_PIPECONF_ACTIVE (1<<30)
1040 #define PIPEACONF_SINGLE_WIDE 0
1041 #define PIPEACONF_PIPE_UNLOCKED 0
1042 #define PIPEACONF_PIPE_LOCKED (1<<25)
1043 #define PIPEACONF_PALETTE 0
1044 #define PIPEACONF_GAMMA (1<<24)
1045 #define PIPECONF_FORCE_BORDER (1<<25)
1046 #define PIPECONF_PROGRESSIVE (0 << 21)
1047 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1048 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1049
1050 #define PIPEBCONF 0x71008
1051 #define PIPEBCONF_ENABLE (1<<31)
1052 #define PIPEBCONF_DISABLE 0
1053 #define PIPEBCONF_DOUBLE_WIDE (1<<30)
1054 #define PIPEBCONF_DISABLE 0
1055 #define PIPEBCONF_GAMMA (1<<24)
1056 #define PIPEBCONF_PALETTE 0
1057
1058 #define PIPEBGCMAXRED 0x71010
1059 #define PIPEBGCMAXGREEN 0x71014
1060 #define PIPEBGCMAXBLUE 0x71018
1061 #define PIPEBSTAT 0x71024
1062 #define PIPEBFRAMEHIGH 0x71040
1063 #define PIPEBFRAMEPIXEL 0x71044
1064
1065 #define DSPACNTR 0x70180
1066 #define DSPBCNTR 0x71180
1067 #define DISPLAY_PLANE_ENABLE (1<<31)
1068 #define DISPLAY_PLANE_DISABLE 0
1069 #define DISPPLANE_GAMMA_ENABLE (1<<30)
1070 #define DISPPLANE_GAMMA_DISABLE 0
1071 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1072 #define DISPPLANE_8BPP (0x2<<26)
1073 #define DISPPLANE_15_16BPP (0x4<<26)
1074 #define DISPPLANE_16BPP (0x5<<26)
1075 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1076 #define DISPPLANE_32BPP (0x7<<26)
1077 #define DISPPLANE_STEREO_ENABLE (1<<25)
1078 #define DISPPLANE_STEREO_DISABLE 0
1079 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
1080 #define DISPPLANE_SEL_PIPE_A 0
1081 #define DISPPLANE_SEL_PIPE_B (1<<24)
1082 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1083 #define DISPPLANE_SRC_KEY_DISABLE 0
1084 #define DISPPLANE_LINE_DOUBLE (1<<20)
1085 #define DISPPLANE_NO_LINE_DOUBLE 0
1086 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1087 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1088 /* plane B only */
1089 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1090 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1091 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
1092 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1093
1094 #define DSPABASE 0x70184
1095 #define DSPASTRIDE 0x70188
1096
1097 #define DSPBBASE 0x71184
1098 #define DSPBADDR DSPBBASE
1099 #define DSPBSTRIDE 0x71188
1100
1101 #define DSPAKEYVAL 0x70194
1102 #define DSPAKEYMASK 0x70198
1103
1104 #define DSPAPOS 0x7018C /* reserved */
1105 #define DSPASIZE 0x70190
1106 #define DSPBPOS 0x7118C
1107 #define DSPBSIZE 0x71190
1108
1109 #define DSPASURF 0x7019C
1110 #define DSPATILEOFF 0x701A4
1111
1112 #define DSPBSURF 0x7119C
1113 #define DSPBTILEOFF 0x711A4
1114
1115 #define VGACNTRL 0x71400
1116 # define VGA_DISP_DISABLE (1 << 31)
1117 # define VGA_2X_MODE (1 << 30)
1118 # define VGA_PIPE_B_SELECT (1 << 29)
1119
1120 /*
1121 * Some BIOS scratch area registers. The 845 (and 830?) store the amount
1122 * of video memory available to the BIOS in SWF1.
1123 */
1124
1125 #define SWF0 0x71410
1126
1127 /*
1128 * 855 scratch registers.
1129 */
1130 #define SWF10 0x70410
1131
1132 #define SWF30 0x72414
1133
1134 /*
1135 * Overlay registers. These are overlay registers accessed via MMIO.
1136 * Those loaded via the overlay register page are defined in i830_video.c.
1137 */
1138 #define OVADD 0x30000
1139
1140 #define DOVSTA 0x30008
1141 #define OC_BUF (0x3<<20)
1142
1143 #define OGAMC5 0x30010
1144 #define OGAMC4 0x30014
1145 #define OGAMC3 0x30018
1146 #define OGAMC2 0x3001c
1147 #define OGAMC1 0x30020
1148 #define OGAMC0 0x30024
1149 /*
1150 * Palette registers
1151 */
1152 #define PALETTE_A 0x0a000
1153 #define PALETTE_B 0x0a800
1154
1155 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1156 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1157 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1158 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
1159 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1160
1161 #define IS_I915G(dev) (dev->pci_device == 0x2582)/* || dev->pci_device == PCI_DEVICE_ID_INTELPCI_CHIP_E7221_G)*/
1162 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1163 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1164 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2)
1165
1166 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
1167 (dev)->pci_device == 0x2982 || \
1168 (dev)->pci_device == 0x2992 || \
1169 (dev)->pci_device == 0x29A2 || \
1170 (dev)->pci_device == 0x2A02 || \
1171 (dev)->pci_device == 0x2A12)
1172
1173 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
1174
1175 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1176 (dev)->pci_device == 0x29B2 || \
1177 (dev)->pci_device == 0x29D2)
1178
1179 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1180 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
1181
1182 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1183 IS_I945GM(dev) || IS_I965GM(dev))
1184
1185 #define PRIMARY_RINGBUFFER_SIZE (128*1024)
1186
1187 #endif
DragonFly BSD