Add riscv-sim.exp
commit8c367b5ca4a79e8ab732ef7f237ab0153ce196bb
authorKito Cheng <kito.cheng@sifive.com>
Tue, 14 Jul 2020 03:24:47 +0000 (14 11:24 +0800)
committerJacob Bachmeyer <jcb@gnu.org>
Tue, 11 Aug 2020 03:12:48 +0000 (10 22:12 -0500)
treee81bd41a69515790ea82a582e279efd263a2b67f
parent480ac301abef92c6b7701b3e846a2cb5e59f33af
Add riscv-sim.exp
Makefile.am
Makefile.in
baseboards/riscv-sim.exp [new file with mode: 0644]