5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
8 * This software may be used and distributed according to the terms of
9 * the GNU Public License, incorporated herein by reference.
12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include:
15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA)
19 * LVS Lawrence V. Stefani
22 * The author may be reached at:
24 * Inet: stefani@lkg.dec.com
25 * Mail: Digital Equipment Corporation
31 * I'd like to thank Patricia Cross for helping me get started with
32 * Linux, David Davies for a lot of help upgrading and configuring
33 * my development system and for answering many OS and driver
34 * development questions, and Alan Cox for recommendations and
35 * integration help on getting FDDI support into Linux. LVS
37 * Driver Architecture:
38 * The driver architecture is largely based on previous driver work
39 * for other operating systems. The upper edge interface and
40 * functions were largely taken from existing Linux device drivers
41 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
45 * The driver scans for supported EISA adapters by reading the
46 * SLOT ID register for each EISA slot and making a match
47 * against the expected value. The supported PCI adapters are
48 * discovered using successive calls to pcibios_find_device.
49 * The first time the probe routine is called, all supported
50 * devices are discovered and initialized. The adapters aren't
51 * brought up to an operational state until the open routine is
54 * Bus-Specific Initialization -
55 * This driver currently supports both EISA and PCI controller
56 * families. While the custom DMA chip and FDDI logic is similar
57 * or identical, the bus logic is very different. After
58 * initialization, the only bus-specific differences is in how the
59 * driver enables and disables interrupts. Other than that, the
60 * run-time critical code behaves the same on both families.
61 * It's important to note that both adapter families are configured
62 * to I/O map, rather than memory map, the adapter registers.
65 * In the driver open routine, the driver ISR (interrupt service
66 * routine) is registered and the adapter is brought to an
67 * operational state. In the driver close routine, the opposite
68 * occurs; the driver ISR is deregistered and the adapter is
69 * brought to a safe, but closed state. Users may use consecutive
70 * commands to bring the adapter up and down as in the following
77 * Apparently, there is no shutdown or halt routine support under
78 * Linux. This routine would be called during "reboot" or
79 * "shutdown" to allow the driver to place the adapter in a safe
80 * state before a warm reboot occurs. To be really safe, the user
81 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
82 * to ensure that the adapter DMA engine is taken off-line. However,
83 * the current driver code anticipates this problem and always issues
84 * a soft reset of the adapter at the beginning of driver initialization.
85 * A future driver enhancement in this area may occur in 2.1.X where
86 * Alan indicated that a shutdown handler may be implemented.
88 * Interrupt Service Routine -
89 * The driver supports shared interrupts, so the ISR is registered for
90 * each board with the appropriate flag and the pointer to that board's
91 * device structure. This provides the context during interrupt
92 * processing to support shared interrupts and multiple boards.
94 * Interrupt enabling/disabling can occur at many levels. At the host
95 * end, you can disable system interrupts, or disable interrupts at the
96 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
97 * have a bus-logic chip interrupt enable/disable as well as a DMA
98 * controller interrupt enable/disable.
100 * The driver currently enables and disables adapter interrupts at the
101 * bus-logic chip and assumes that Linux will take care of clearing or
102 * acknowledging any host-based interrupt chips.
104 * Control Functions -
105 * Control functions are those used to support functions such as adding
106 * or deleting multicast addresses, enabling or disabling packet
107 * reception filters, or other custom/proprietary commands. Presently,
108 * the driver supports the "get statistics", "set multicast list", and
109 * "set mac address" functions defined by Linux. A list of possible
110 * enhancements include:
112 * - Custom ioctl interface for executing port interface commands
113 * - Custom ioctl interface for adding unicast addresses to
114 * adapter CAM (to support bridge functions).
115 * - Custom ioctl interface for supporting firmware upgrades.
117 * Hardware (port interface) Support Routines -
118 * The driver function names that start with "dfx_hw_" represent
119 * low-level port interface routines that are called frequently. They
120 * include issuing a DMA or port control command to the adapter,
121 * resetting the adapter, or reading the adapter state. Since the
122 * driver initialization and run-time code must make calls into the
123 * port interface, these routines were written to be as generic and
124 * usable as possible.
127 * The adapter DMA engine supports a 256 entry receive descriptor block
128 * of which up to 255 entries can be used at any given time. The
129 * architecture is a standard producer, consumer, completion model in
130 * which the driver "produces" receive buffers to the adapter, the
131 * adapter "consumes" the receive buffers by DMAing incoming packet data,
132 * and the driver "completes" the receive buffers by servicing the
133 * incoming packet, then "produces" a new buffer and starts the cycle
134 * again. Receive buffers can be fragmented in up to 16 fragments
135 * (descriptor entries). For simplicity, this driver posts
136 * single-fragment receive buffers of 4608 bytes, then allocates a
137 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
138 * utilization, a better approach would be to pass up the receive
139 * buffer (no extra copy) then allocate and post a replacement buffer.
140 * This is a performance enhancement that should be looked into at
144 * Like the receive path, the adapter DMA engine supports a 256 entry
145 * transmit descriptor block of which up to 255 entries can be used at
146 * any given time. Transmit buffers can be fragmented in up to 255
147 * fragments (descriptor entries). This driver always posts one
148 * fragment per transmit packet request.
150 * The fragment contains the entire packet from FC to end of data.
151 * Before posting the buffer to the adapter, the driver sets a three-byte
152 * packet request header (PRH) which is required by the Motorola MAC chip
153 * used on the adapters. The PRH tells the MAC the type of token to
154 * receive/send, whether or not to generate and append the CRC, whether
155 * synchronous or asynchronous framing is used, etc. Since the PRH
156 * definition is not necessarily consistent across all FDDI chipsets,
157 * the driver, rather than the common FDDI packet handler routines,
160 * To reduce the amount of descriptor fetches needed per transmit request,
161 * the driver takes advantage of the fact that there are at least three
162 * bytes available before the skb->data field on the outgoing transmit
163 * request. This is guaranteed by having fddi_setup() in net_init.c set
164 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
165 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
166 * bytes which we'll use to store the PRH.
168 * There's a subtle advantage to adding these pad bytes to the
169 * hard_header_len, it ensures that the data portion of the packet for
170 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
171 * implementations may not need the extra padding and can start copying
172 * or DMAing directly from the FC byte which starts at skb->data. Should
173 * another driver implementation need ADDITIONAL padding, the net_init.c
174 * module should be updated and dev->hard_header_len should be increased.
175 * NOTE: To maintain the alignment on the data portion of the packet,
176 * dev->hard_header_len should always be evenly divisible by 4 and at
177 * least 24 bytes in size.
179 * Modification History:
180 * Date Name Description
181 * 16-Aug-96 LVS Created.
182 * 20-Aug-96 LVS Updated dfx_probe so that version information
183 * string is only displayed if 1 or more cards are
184 * found. Changed dfx_rcv_queue_process to copy
185 * 3 NULL bytes before FC to ensure that data is
186 * longword aligned in receive buffer.
187 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
188 * LLC group promiscuous mode if multicast list
189 * is too large. LLC individual/group promiscuous
190 * mode is now disabled if IFF_PROMISC flag not set.
191 * dfx_xmt_queue_pkt no longer checks for NULL skb
192 * on Alan Cox recommendation. Added node address
194 * 12-Sep-96 LVS Reset current address to factory address during
195 * device open. Updated transmit path to post a
196 * single fragment which includes PRH->end of data.
199 /* Version information string - should be updated prior to each new release!!! */
201 static const char *version
= "defxx.c:v1.04 09/16/96 Lawrence V. Stefani (stefani@lkg.dec.com)\n";
205 #include <linux/module.h>
207 #include <linux/kernel.h>
208 #include <linux/sched.h>
209 #include <linux/string.h>
210 #include <linux/ptrace.h>
211 #include <linux/errno.h>
212 #include <linux/ioport.h>
213 #include <linux/malloc.h>
214 #include <linux/interrupt.h>
215 #include <linux/pci.h>
216 #include <linux/bios32.h>
217 #include <linux/delay.h>
218 #include <linux/init.h>
219 #include <asm/byteorder.h>
220 #include <asm/bitops.h>
223 #include <linux/netdevice.h>
224 #include <linux/fddidevice.h>
225 #include <linux/skbuff.h>
229 /* Define global routines */
231 int dfx_probe(struct device
*dev
);
233 /* Define module-wide (static) routines */
235 static struct device
*dfx_alloc_device(struct device
*dev
, u16 iobase
);
237 static void dfx_bus_init(struct device
*dev
);
238 static void dfx_bus_config_check(DFX_board_t
*bp
);
240 static int dfx_driver_init(struct device
*dev
);
241 static int dfx_adap_init(DFX_board_t
*bp
);
243 static int dfx_open(struct device
*dev
);
244 static int dfx_close(struct device
*dev
);
246 static void dfx_int_pr_halt_id(DFX_board_t
*bp
);
247 static void dfx_int_type_0_process(DFX_board_t
*bp
);
248 static void dfx_int_common(DFX_board_t
*bp
);
249 static void dfx_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
);
251 static struct net_device_stats
*dfx_ctl_get_stats(struct device
*dev
);
252 static void dfx_ctl_set_multicast_list(struct device
*dev
);
253 static int dfx_ctl_set_mac_address(struct device
*dev
, void *addr
);
254 static int dfx_ctl_update_cam(DFX_board_t
*bp
);
255 static int dfx_ctl_update_filters(DFX_board_t
*bp
);
257 static int dfx_hw_dma_cmd_req(DFX_board_t
*bp
);
258 static int dfx_hw_port_ctrl_req(DFX_board_t
*bp
, PI_UINT32 command
, PI_UINT32 data_a
, PI_UINT32 data_b
, PI_UINT32
*host_data
);
259 static void dfx_hw_adap_reset(DFX_board_t
*bp
, PI_UINT32 type
);
260 static int dfx_hw_adap_state_rd(DFX_board_t
*bp
);
261 static int dfx_hw_dma_uninit(DFX_board_t
*bp
, PI_UINT32 type
);
263 static void dfx_rcv_init(DFX_board_t
*bp
);
264 static void dfx_rcv_queue_process(DFX_board_t
*bp
);
266 static int dfx_xmt_queue_pkt(struct sk_buff
*skb
, struct device
*dev
);
267 static void dfx_xmt_done(DFX_board_t
*bp
);
268 static void dfx_xmt_flush(DFX_board_t
*bp
);
270 /* Define module-wide (static) variables */
272 static int num_boards
= 0; /* total number of adapters configured */
273 static int already_probed
= 0; /* have we already entered dfx_probe? */
277 * =======================
278 * = dfx_port_write_byte =
279 * = dfx_port_read_byte =
280 * = dfx_port_write_long =
281 * = dfx_port_read_long =
282 * =======================
285 * Routines for reading and writing values from/to adapter
291 * bp - pointer to board information
292 * offset - register offset from base I/O address
293 * data - for dfx_port_write_byte and dfx_port_write_long, this
294 * is a value to write.
295 * for dfx_port_read_byte and dfx_port_read_byte, this
296 * is a pointer to store the read value.
298 * Functional Description:
299 * These routines perform the correct operation to read or write
300 * the adapter register.
302 * EISA port block base addresses are based on the slot number in which the
303 * controller is installed. For example, if the EISA controller is installed
304 * in slot 4, the port block base address is 0x4000. If the controller is
305 * installed in slot 2, the port block base address is 0x2000, and so on.
306 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
307 * registers using the register offsets defined in DEFXX.H.
309 * PCI port block base addresses are assigned by the PCI BIOS or system
310 * firmware. There is one 128 byte port block which can be accessed. It
311 * allows for I/O mapping of both PDQ and PFI registers using the register
312 * offsets defined in DEFXX.H.
318 * bp->base_addr is a valid base I/O address for this adapter.
319 * offset is a valid register offset for this adapter.
322 * Rather than produce macros for these functions, these routines
323 * are defined using "inline" to ensure that the compiler will
324 * generate inline code and not waste a procedure call and return.
325 * This provides all the benefits of macros, but with the
326 * advantage of strict data type checking.
329 static inline void dfx_port_write_byte(
336 u16 port
= bp
->base_addr
+ offset
;
342 static inline void dfx_port_read_byte(
349 u16 port
= bp
->base_addr
+ offset
;
355 static inline void dfx_port_write_long(
362 u16 port
= bp
->base_addr
+ offset
;
368 static inline void dfx_port_read_long(
375 u16 port
= bp
->base_addr
+ offset
;
388 * Probes for supported FDDI EISA and PCI controllers
394 * dev - pointer to device information
396 * Functional Description:
397 * This routine is called by the OS for each FDDI device name (fddi0,
398 * fddi1,...,fddi6, fddi7) specified in drivers/net/Space.c. Since
399 * the DEFXX.C driver currently does not support being loaded as a
400 * module, dfx_probe() will initialize all devices the first time
403 * Let's say that dfx_probe() is getting called to initialize fddi0.
404 * Furthermore, let's say there are three supported controllers in the
405 * system. Before dfx_probe() leaves, devices fddi0, fddi1, and fddi2
406 * will be initialized and a global flag will be set to indicate that
407 * dfx_probe() has already been called.
409 * However...the OS doesn't know that we've already initialized
410 * devices fddi1 and fddi2 so dfx_probe() gets called again and again
411 * until it reaches the end of the device list for FDDI (presently,
412 * fddi7). It's important that the driver "pretend" to probe for
413 * devices fddi1 and fddi2 and return success. Devices fddi3
414 * through fddi7 will return failure since they weren't initialized.
416 * This algorithm seems to work for the time being. As other FDDI
417 * drivers are written for Linux, a more generic approach (perhaps
418 * similar to the Ethernet card approach) may need to be implemented.
421 * 0 - This device (fddi0, fddi1, etc) configured successfully
422 * -ENODEV - No devices present, or no Digital FDDI EISA or PCI device
423 * present for this device name
426 * For the time being, DEFXX.C is the only FDDI driver under Linux.
427 * As this assumption changes, this routine will likely be impacted.
428 * Also, it is assumed that no more than eight (8) FDDI controllers
429 * will be configured in the system (fddi0 through fddi7). This
430 * routine will not allocate new device structures. If more than
431 * eight FDDI controllers need to be configured, drivers/net/Space.c
432 * should be updated as well as the DFX_MAX_NUM_BOARDS constant in
436 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
437 * initialized and the board resources are read and stored in
438 * the device structure.
441 __initfunc(int dfx_probe(
446 int i
; /* used in for loops */
447 int version_disp
; /* was version info string already displayed? */
448 int port_len
; /* length of port address range (in bytes) */
449 u8 pci_bus
; /* PCI bus number (0-255) */
450 u8 pci_dev_fun
; /* PCI device and function numbers (0-255) */
451 u16 port
; /* temporary I/O (port) address */
452 u16 command
; /* PCI Configuration space Command register val */
453 u32 slot_id
; /* EISA hardware (slot) ID read from adapter */
454 DFX_board_t
*bp
; /* board pointer */
456 DBG_printk("In dfx_probe...\n");
459 * Verify whether we're going through dfx_probe() again
461 * If so, see if we're going through for a subsequent fddi device that
462 * we've already initialized. If we are, return success (0). If not,
463 * return failure (-ENODEV).
466 version_disp
= 0; /* default to version string not displayed */
469 DBG_printk("Already entered dfx_probe\n");
471 if ((strncmp(dev
->name
, "fddi", 4) == 0) && (dev
->base_addr
!= 0))
473 DBG_printk("In dfx_probe for fddi adapter (%s) we've already initialized it, so return success\n", dev
->name
);
478 already_probed
= 1; /* set global flag */
480 /* Scan for FDDI EISA controllers */
482 for (i
=0; i
< DFX_MAX_EISA_SLOTS
; i
++) /* only scan for up to 16 EISA slots */
484 port
= (i
<< 12) + PI_ESIC_K_SLOT_ID
; /* port = I/O address for reading slot ID */
485 slot_id
= inl(port
); /* read EISA HW (slot) ID */
486 if ((slot_id
& 0xF0FFFFFF) == DEFEA_PRODUCT_ID
)
488 if (!version_disp
) /* display version info if adapter is found */
490 version_disp
= 1; /* set display flag to TRUE so that */
491 printk(version
); /* we only display this string ONCE */
494 port
= (i
<< 12); /* recalc base addr */
496 /* Verify port address range is not already being used */
498 port_len
= PI_ESIC_K_CSR_IO_LEN
;
499 if (check_region(port
, port_len
) == 0)
501 /* Allocate a new device structure for this adapter */
503 dev
= dfx_alloc_device(dev
, port
);
506 /* Initialize board structure with bus-specific info */
508 bp
= (DFX_board_t
*) dev
->priv
;
510 bp
->bus_type
= DFX_BUS_TYPE_EISA
;
511 if (dfx_driver_init(dev
) == DFX_K_SUCCESS
)
512 num_boards
++; /* only increment global board count on success */
514 dev
->base_addr
= 0; /* clear port address field in device structure on failure */
518 printk("I/O range allocated to adapter (0x%X-0x%X) is already being used!\n", port
, (port
+ port_len
-1));
522 /* Scan for FDDI PCI controllers */
524 if (pcibios_present()) /* is PCI BIOS even present? */
525 for (i
=0; i
< DFX_MAX_NUM_BOARDS
; i
++) /* scan for up to 8 PCI cards */
526 if (pcibios_find_device(PCI_VENDOR_ID_DEC
, PCI_DEVICE_ID_DEC_FDDI
, i
, &pci_bus
, &pci_dev_fun
) == 0)
528 if (!version_disp
) /* display version info if adapter is found */
530 version_disp
= 1; /* set display flag to TRUE so that */
531 printk(version
); /* we only display this string ONCE */
534 /* Verify that I/O enable bit is set (PCI slot is enabled) */
536 pcibios_read_config_word(pci_bus
, pci_dev_fun
, PCI_COMMAND
, &command
);
537 if ((command
& PCI_COMMAND_IO
) == 0)
538 printk("I/O enable bit not set! Verify that slot is enabled\n");
541 /* Turn off memory mapped space and enable mastering */
543 command
|= PCI_COMMAND_MASTER
;
544 command
&= ~PCI_COMMAND_MEMORY
;
545 pcibios_write_config_word(pci_bus
, pci_dev_fun
, PCI_COMMAND
, command
);
547 /* Read I/O base address from PCI Configuration Space */
549 pcibios_read_config_word(pci_bus
, pci_dev_fun
, PCI_BASE_ADDRESS_1
, &port
);
550 port
&= PCI_BASE_ADDRESS_IO_MASK
; /* clear I/O bit (bit 0) */
552 /* Verify port address range is not already being used */
554 port_len
= PFI_K_CSR_IO_LEN
;
555 if (check_region(port
, port_len
) == 0)
557 /* Allocate a new device structure for this adapter */
559 dev
= dfx_alloc_device(dev
, port
);
562 /* Initialize board structure with bus-specific info */
564 bp
= (DFX_board_t
*) dev
->priv
;
566 bp
->bus_type
= DFX_BUS_TYPE_PCI
;
567 bp
->pci_bus
= pci_bus
;
568 bp
->pci_dev_fun
= pci_dev_fun
;
569 if (dfx_driver_init(dev
) == DFX_K_SUCCESS
)
570 num_boards
++; /* only increment global board count on success */
572 dev
->base_addr
= 0; /* clear port address field in device structure on failure */
576 printk("I/O range allocated to adapter (0x%X-0x%X) is already being used!\n", port
, (port
+ port_len
-1));
581 * If we're at this point we're going through dfx_probe() for the first
582 * time. Return success (0) if we've initialized 1 or more boards.
583 * Otherwise, return failure (-ENODEV).
594 * ====================
595 * = dfx_alloc_device =
596 * ====================
599 * Allocate new device structure for adapter
602 * Pointer to device structure for this adapter or NULL if
603 * none are available or could not allocate memory for
604 * private board structure.
607 * dev - pointer to device information for last device
608 * iobase - base I/O address of new adapter
610 * Functional Description:
611 * The algorithm for allocating a new device structure is
612 * fairly simple. Since we're presently the only FDDI driver
613 * under Linux, we'll find the first device structure with an
614 * "fddi*" device name that's free. If we run out of devices,
615 * we'll fail on error. This is simpler than trying to
616 * allocate the memory for a new device structure, determine
617 * the next free number (beyond 7) and link it into the chain
618 * of devices. A user can always modify drivers/net/Space.c
619 * to add new FDDI device structures if necessary.
621 * Beyond finding a free FDDI device structure, this routine
622 * initializes most of the fields, resource tags, and dispatch
623 * pointers in the device structure and calls the common
624 * fddi_setup() routine to perform the rest of the device
625 * structure initialization.
631 * If additional FDDI drivers are integrated into Linux,
632 * we'll likely need to use a different approach to
633 * allocate a device structure. Perhaps one that is
634 * similar to what the Ethernet drivers use.
640 __initfunc(struct device
*dfx_alloc_device(
646 struct device
*tmp_dev
; /* pointer to a device structure */
648 DBG_printk("In dfx_alloc_device...\n");
650 /* Find next free fddi entry */
652 for (tmp_dev
= dev
; tmp_dev
!= NULL
; tmp_dev
= tmp_dev
->next
)
653 if ((strncmp(tmp_dev
->name
, "fddi", 4) == 0) && (tmp_dev
->base_addr
== 0))
657 printk("Could not find free FDDI device structure for this adapter!\n");
660 DBG_printk("Device entry free, device name = %s\n", tmp_dev
->name
);
662 /* Allocate space for private board structure */
664 tmp_dev
->priv
= (void *) kmalloc(sizeof(DFX_board_t
), GFP_KERNEL
);
665 if (tmp_dev
->priv
== NULL
)
667 printk("Could not allocate memory for private board structure!\n");
670 memset(tmp_dev
->priv
, 0, sizeof(DFX_board_t
)); /* clear structure */
672 /* Initialize new device structure */
674 tmp_dev
->rmem_end
= 0; /* shared memory isn't used */
675 tmp_dev
->rmem_start
= 0; /* shared memory isn't used */
676 tmp_dev
->mem_end
= 0; /* shared memory isn't used */
677 tmp_dev
->mem_start
= 0; /* shared memory isn't used */
678 tmp_dev
->base_addr
= iobase
; /* save port (I/O) base address */
679 tmp_dev
->irq
= 0; /* set in dfx_bus_init() */
680 tmp_dev
->if_port
= 0; /* not applicable to FDDI adapters */
681 tmp_dev
->dma
= 0; /* Bus Master DMA doesn't require channel */
683 tmp_dev
->get_stats
= &dfx_ctl_get_stats
;
684 tmp_dev
->open
= &dfx_open
;
685 tmp_dev
->stop
= &dfx_close
;
686 tmp_dev
->hard_start_xmit
= &dfx_xmt_queue_pkt
;
687 tmp_dev
->hard_header
= NULL
; /* set in fddi_setup() */
688 tmp_dev
->rebuild_header
= NULL
; /* set in fddi_setup() */
689 tmp_dev
->set_multicast_list
= &dfx_ctl_set_multicast_list
;
690 tmp_dev
->set_mac_address
= &dfx_ctl_set_mac_address
;
691 tmp_dev
->do_ioctl
= NULL
; /* not supported for now &&& */
692 tmp_dev
->set_config
= NULL
; /* not supported for now &&& */
693 tmp_dev
->hard_header_cache
= NULL
; /* not supported */
694 tmp_dev
->header_cache_update
= NULL
; /* not supported */
695 tmp_dev
->change_mtu
= NULL
; /* set in fddi_setup() */
697 /* Initialize remaining device structure information */
710 * Initializes EISA and PCI controller bus-specific logic.
716 * dev - pointer to device information
718 * Functional Description:
719 * Determine and save adapter IRQ in device table,
720 * then perform bus-specific logic initialization.
726 * dev->base_addr has already been set with the proper
727 * base I/O address for this device.
730 * Interrupts are enabled at the adapter bus-specific logic.
731 * Note: Interrupts at the DMA engine (PDQ chip) are not
735 __initfunc(void dfx_bus_init(
740 DFX_board_t
*bp
= (DFX_board_t
*)dev
->priv
;
741 u8 val
; /* used for I/O read/writes */
743 DBG_printk("In dfx_bus_init...\n");
746 * Initialize base I/O address field in bp structure
748 * Note: bp->base_addr is the same as dev->base_addr.
749 * It's useful because often we'll need to read
750 * or write registers where we already have the
751 * bp pointer instead of the dev pointer. Having
752 * the base address in the bp structure will
753 * save a pointer dereference.
755 * IMPORTANT!! This field must be defined before
756 * any of the dfx_port_* inline functions are
760 bp
->base_addr
= dev
->base_addr
;
762 /* Initialize adapter based on bus type */
764 if (bp
->bus_type
== DFX_BUS_TYPE_EISA
)
766 /* Get the interrupt level from the ESIC chip */
768 dfx_port_read_byte(bp
, PI_ESIC_K_IO_CONFIG_STAT_0
, &val
);
769 switch ((val
& PI_CONFIG_STAT_0_M_IRQ
) >> PI_CONFIG_STAT_0_V_IRQ
)
771 case PI_CONFIG_STAT_0_IRQ_K_9
:
775 case PI_CONFIG_STAT_0_IRQ_K_10
:
779 case PI_CONFIG_STAT_0_IRQ_K_11
:
783 case PI_CONFIG_STAT_0_IRQ_K_15
:
788 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
790 dfx_port_write_byte(bp
, PI_ESIC_K_FUNCTION_CNTRL
, PI_ESIC_K_FUNCTION_CNTRL_IO_ENB
);
792 /* Set the I/O decode range of the board */
794 val
= ((dev
->base_addr
>> 12) << PI_IO_CMP_V_SLOT
);
795 dfx_port_write_byte(bp
, PI_ESIC_K_IO_CMP_0_1
, val
);
796 dfx_port_write_byte(bp
, PI_ESIC_K_IO_CMP_1_1
, val
);
798 /* Enable access to rest of module (including PDQ and packet memory) */
800 dfx_port_write_byte(bp
, PI_ESIC_K_SLOT_CNTRL
, PI_SLOT_CNTRL_M_ENB
);
803 * Map PDQ registers into I/O space. This is done by clearing a bit
804 * in Burst Holdoff register.
807 dfx_port_read_byte(bp
, PI_ESIC_K_BURST_HOLDOFF
, &val
);
808 dfx_port_write_byte(bp
, PI_ESIC_K_BURST_HOLDOFF
, (val
& ~PI_BURST_HOLDOFF_M_MEM_MAP
));
810 /* Enable interrupts at EISA bus interface chip (ESIC) */
812 dfx_port_read_byte(bp
, PI_ESIC_K_IO_CONFIG_STAT_0
, &val
);
813 dfx_port_write_byte(bp
, PI_ESIC_K_IO_CONFIG_STAT_0
, (val
| PI_CONFIG_STAT_0_M_INT_ENB
));
817 /* Get the interrupt level from the PCI Configuration Table */
819 pcibios_read_config_byte(bp
->pci_bus
, bp
->pci_dev_fun
, PCI_INTERRUPT_LINE
, &val
);
820 dev
->irq
= val
; /* save IRQ value in device table */
822 /* Check Latency Timer and set if less than minimal */
824 pcibios_read_config_byte(bp
->pci_bus
, bp
->pci_dev_fun
, PCI_LATENCY_TIMER
, &val
);
825 if (val
< PFI_K_LAT_TIMER_MIN
) /* if less than min, override with default */
827 val
= PFI_K_LAT_TIMER_DEF
;
828 pcibios_write_config_byte(bp
->pci_bus
, bp
->pci_dev_fun
, PCI_LATENCY_TIMER
, val
);
831 /* Enable interrupts at PCI bus interface chip (PFI) */
833 dfx_port_write_long(bp
, PFI_K_REG_MODE_CTRL
, (PFI_MODE_M_PDQ_INT_ENB
| PFI_MODE_M_DMA_ENB
));
840 * ========================
841 * = dfx_bus_config_check =
842 * ========================
845 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
846 * are illegal, then this routine will set new defaults.
852 * bp - pointer to board information
854 * Functional Description:
855 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
856 * PDQ, and all FDDI PCI controllers, all values are legal.
862 * dfx_adap_init has NOT been called yet so burst size and other items have
869 __initfunc(void dfx_bus_config_check(
874 int status
; /* return code from adapter port control call */
875 u32 slot_id
; /* EISA-bus hardware id (DEC3001, DEC3002,...) */
876 u32 host_data
; /* LW data returned from port control call */
878 DBG_printk("In dfx_bus_config_check...\n");
880 /* Configuration check only valid for EISA adapter */
882 if (bp
->bus_type
== DFX_BUS_TYPE_EISA
)
884 dfx_port_read_long(bp
, PI_ESIC_K_SLOT_ID
, &slot_id
);
887 * First check if revision 2 EISA controller. Rev. 1 cards used
888 * PDQ revision B, so no workaround needed in this case. Rev. 3
889 * cards used PDQ revision E, so no workaround needed in this
890 * case, either. Only Rev. 2 cards used either Rev. D or E
891 * chips, so we must verify the chip revision on Rev. 2 cards.
894 if (slot_id
== DEFEA_PROD_ID_2
)
897 * Revision 2 FDDI EISA controller found, so let's check PDQ
898 * revision of adapter.
901 status
= dfx_hw_port_ctrl_req(bp
,
903 PI_SUB_CMD_K_PDQ_REV_GET
,
906 if ((status
!= DFX_K_SUCCESS
) || (host_data
== 2))
909 * Either we couldn't determine the PDQ revision, or
910 * we determined that it is at revision D. In either case,
911 * we need to implement the workaround.
914 /* Ensure that the burst size is set to 8 longwords or less */
916 switch (bp
->burst_size
)
918 case PI_PDATA_B_DMA_BURST_SIZE_32
:
919 case PI_PDATA_B_DMA_BURST_SIZE_16
:
920 bp
->burst_size
= PI_PDATA_B_DMA_BURST_SIZE_8
;
927 /* Ensure that full-duplex mode is not enabled */
929 bp
->full_duplex_enb
= PI_SNMP_K_FALSE
;
938 * ===================
939 * = dfx_driver_init =
940 * ===================
943 * Initializes remaining adapter board structure information
944 * and makes sure adapter is in a safe state prior to dfx_open().
950 * dev - pointer to device information
952 * Functional Description:
953 * This function allocates additional resources such as the host memory
954 * blocks needed by the adapter (eg. descriptor and consumer blocks).
955 * Remaining bus initialization steps are also completed. The adapter
956 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
957 * must call dfx_open() to open the adapter and bring it on-line.
960 * DFX_K_SUCCESS - initialization succeeded
961 * DFX_K_FAILURE - initialization failed - could not allocate memory
962 * or read adapter MAC address
965 * Memory allocated from kmalloc() call is physically contiguous, locked
966 * memory whose physical address equals its virtual address.
969 * Adapter is reset and should be in DMA_UNAVAILABLE state before
970 * returning from this routine.
973 __initfunc(int dfx_driver_init(
978 DFX_board_t
*bp
= (DFX_board_t
*)dev
->priv
;
979 int alloc_size
; /* total buffer size needed */
980 char *top_v
, *curr_v
; /* virtual addrs into memory block */
981 u32 top_p
, curr_p
; /* physical addrs into memory block */
982 u32 data
; /* host data register value */
984 DBG_printk("In dfx_driver_init...\n");
986 /* Initialize bus-specific hardware registers */
991 * Initialize default values for configurable parameters
993 * Note: All of these parameters are ones that a user may
994 * want to customize. It'd be nice to break these
995 * out into Space.c or someplace else that's more
996 * accessible/understandable than this file.
999 bp
->full_duplex_enb
= PI_SNMP_K_FALSE
;
1000 bp
->req_ttrt
= 8 * 12500; /* 8ms in 80 nanosec units */
1001 bp
->burst_size
= PI_PDATA_B_DMA_BURST_SIZE_DEF
;
1002 bp
->rcv_bufs_to_post
= RCV_BUFS_DEF
;
1005 * Ensure that HW configuration is OK
1007 * Note: Depending on the hardware revision, we may need to modify
1008 * some of the configurable parameters to workaround hardware
1009 * limitations. We'll perform this configuration check AFTER
1010 * setting the parameters to their default values.
1013 dfx_bus_config_check(bp
);
1015 /* Disable PDQ interrupts first */
1017 dfx_port_write_long(bp
, PI_PDQ_K_REG_HOST_INT_ENB
, PI_HOST_INT_K_DISABLE_ALL_INTS
);
1019 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1021 (void) dfx_hw_dma_uninit(bp
, PI_PDATA_A_RESET_M_SKIP_ST
);
1023 /* Read the factory MAC address from the adapter then save it */
1025 if (dfx_hw_port_ctrl_req(bp
,
1027 PI_PDATA_A_MLA_K_LO
,
1029 &data
) != DFX_K_SUCCESS
)
1031 printk("%s: Could not read adapter factory MAC address!\n", dev
->name
);
1032 return(DFX_K_FAILURE
);
1034 memcpy(&bp
->factory_mac_addr
[0], &data
, sizeof(u32
));
1036 if (dfx_hw_port_ctrl_req(bp
,
1038 PI_PDATA_A_MLA_K_HI
,
1040 &data
) != DFX_K_SUCCESS
)
1042 printk("%s: Could not read adapter factory MAC address!\n", dev
->name
);
1043 return(DFX_K_FAILURE
);
1045 memcpy(&bp
->factory_mac_addr
[4], &data
, sizeof(u16
));
1048 * Set current address to factory address
1050 * Note: Node address override support is handled through
1051 * dfx_ctl_set_mac_address.
1054 memcpy(dev
->dev_addr
, bp
->factory_mac_addr
, FDDI_K_ALEN
);
1055 if (bp
->bus_type
== DFX_BUS_TYPE_EISA
)
1056 printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
1067 printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
1079 * Get memory for descriptor block, consumer block, and other buffers
1080 * that need to be DMA read or written to by the adapter.
1083 alloc_size
= sizeof(PI_DESCR_BLOCK
) +
1084 PI_CMD_REQ_K_SIZE_MAX
+
1085 PI_CMD_RSP_K_SIZE_MAX
+
1086 (bp
->rcv_bufs_to_post
* PI_RCV_DATA_K_SIZE_MAX
) +
1087 sizeof(PI_CONSUMER_BLOCK
) +
1088 (PI_ALIGN_K_DESC_BLK
- 1);
1089 top_v
= (char *) kmalloc(alloc_size
, GFP_KERNEL
);
1092 printk("%s: Could not allocate memory for host buffers and structures!\n", dev
->name
);
1093 return(DFX_K_FAILURE
);
1095 memset(top_v
, 0, alloc_size
); /* zero out memory before continuing */
1096 top_p
= virt_to_bus(top_v
); /* get physical address of buffer */
1099 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
1100 * plus the amount of memory needed was allocated. The physical address
1101 * is now 8K aligned. By carving up the memory in a specific order,
1102 * we'll guarantee the alignment requirements for all other structures.
1104 * Note: If the assumptions change regarding the non-paged, non-cached,
1105 * physically contiguous nature of the memory block or the address
1106 * alignments, then we'll need to implement a different algorithm
1107 * for allocating the needed memory.
1110 curr_p
= (u32
) (ALIGN(top_p
, PI_ALIGN_K_DESC_BLK
));
1111 curr_v
= top_v
+ (curr_p
- top_p
);
1113 /* Reserve space for descriptor block */
1115 bp
->descr_block_virt
= (PI_DESCR_BLOCK
*) curr_v
;
1116 bp
->descr_block_phys
= curr_p
;
1117 curr_v
+= sizeof(PI_DESCR_BLOCK
);
1118 curr_p
+= sizeof(PI_DESCR_BLOCK
);
1120 /* Reserve space for command request buffer */
1122 bp
->cmd_req_virt
= (PI_DMA_CMD_REQ
*) curr_v
;
1123 bp
->cmd_req_phys
= curr_p
;
1124 curr_v
+= PI_CMD_REQ_K_SIZE_MAX
;
1125 curr_p
+= PI_CMD_REQ_K_SIZE_MAX
;
1127 /* Reserve space for command response buffer */
1129 bp
->cmd_rsp_virt
= (PI_DMA_CMD_RSP
*) curr_v
;
1130 bp
->cmd_rsp_phys
= curr_p
;
1131 curr_v
+= PI_CMD_RSP_K_SIZE_MAX
;
1132 curr_p
+= PI_CMD_RSP_K_SIZE_MAX
;
1134 /* Reserve space for the LLC host receive queue buffers */
1136 bp
->rcv_block_virt
= curr_v
;
1137 bp
->rcv_block_phys
= curr_p
;
1138 curr_v
+= (bp
->rcv_bufs_to_post
* PI_RCV_DATA_K_SIZE_MAX
);
1139 curr_p
+= (bp
->rcv_bufs_to_post
* PI_RCV_DATA_K_SIZE_MAX
);
1141 /* Reserve space for the consumer block */
1143 bp
->cons_block_virt
= (PI_CONSUMER_BLOCK
*) curr_v
;
1144 bp
->cons_block_phys
= curr_p
;
1146 /* Display virtual and physical addresses if debug driver */
1148 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", dev
->name
, (long)bp
->descr_block_virt
, bp
->descr_block_phys
);
1149 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", dev
->name
, (long)bp
->cmd_req_virt
, bp
->cmd_req_phys
);
1150 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", dev
->name
, (long)bp
->cmd_rsp_virt
, bp
->cmd_rsp_phys
);
1151 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", dev
->name
, (long)bp
->rcv_block_virt
, bp
->rcv_block_phys
);
1152 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", dev
->name
, (long)bp
->cons_block_virt
, bp
->cons_block_phys
);
1154 return(DFX_K_SUCCESS
);
1164 * Brings the adapter to the link avail/link unavailable state.
1170 * bp - pointer to board information
1172 * Functional Description:
1173 * Issues the low-level firmware/hardware calls necessary to bring
1174 * the adapter up, or to properly reset and restore adapter during
1178 * DFX_K_SUCCESS - Adapter brought up successfully
1179 * DFX_K_FAILURE - Adapter initialization failed
1182 * bp->reset_type should be set to a valid reset type value before
1183 * calling this routine.
1186 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1187 * upon a successful return of this routine.
1195 DBG_printk("In dfx_adap_init...\n");
1197 /* Disable PDQ interrupts first */
1199 dfx_port_write_long(bp
, PI_PDQ_K_REG_HOST_INT_ENB
, PI_HOST_INT_K_DISABLE_ALL_INTS
);
1201 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1203 if (dfx_hw_dma_uninit(bp
, bp
->reset_type
) != DFX_K_SUCCESS
)
1205 printk("%s: Could not uninitialize/reset adapter!\n", bp
->dev
->name
);
1206 return(DFX_K_FAILURE
);
1210 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1211 * so we'll acknowledge all Type 0 interrupts now before continuing.
1214 dfx_port_write_long(bp
, PI_PDQ_K_REG_TYPE_0_STATUS
, PI_HOST_INT_K_ACK_ALL_TYPE_0
);
1217 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1219 * Note: We only need to clear host copies of these registers. The PDQ reset
1220 * takes care of the on-board register values.
1223 bp
->cmd_req_reg
.lword
= 0;
1224 bp
->cmd_rsp_reg
.lword
= 0;
1225 bp
->rcv_xmt_reg
.lword
= 0;
1227 /* Clear consumer block before going to DMA_AVAILABLE state */
1229 memset(bp
->cons_block_virt
, 0, sizeof(PI_CONSUMER_BLOCK
));
1231 /* Initialize the DMA Burst Size */
1233 if (dfx_hw_port_ctrl_req(bp
,
1235 PI_SUB_CMD_K_BURST_SIZE_SET
,
1237 NULL
) != DFX_K_SUCCESS
)
1239 printk("%s: Could not set adapter burst size!\n", bp
->dev
->name
);
1240 return(DFX_K_FAILURE
);
1244 * Set base address of Consumer Block
1246 * Assumption: 32-bit physical address of consumer block is 64 byte
1247 * aligned. That is, bits 0-5 of the address must be zero.
1250 if (dfx_hw_port_ctrl_req(bp
,
1251 PI_PCTRL_M_CONS_BLOCK
,
1252 bp
->cons_block_phys
,
1254 NULL
) != DFX_K_SUCCESS
)
1256 printk("%s: Could not set consumer block address!\n", bp
->dev
->name
);
1257 return(DFX_K_FAILURE
);
1261 * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state
1263 * Note: We also set the literal and data swapping requirements in this
1264 * command. Since this driver presently runs on Intel platforms
1265 * which are Little Endian, we'll tell the adapter to byte swap
1266 * data only. This code will need to change when we support
1267 * Big Endian systems (eg. PowerPC).
1269 * Assumption: 32-bit physical address of descriptor block is 8Kbyte
1270 * aligned. That is, bits 0-12 of the address must be zero.
1273 if (dfx_hw_port_ctrl_req(bp
,
1275 (u32
) (bp
->descr_block_phys
| PI_PDATA_A_INIT_M_BSWAP_DATA
),
1277 NULL
) != DFX_K_SUCCESS
)
1279 printk("%s: Could not set descriptor block address!\n", bp
->dev
->name
);
1280 return(DFX_K_FAILURE
);
1283 /* Set transmit flush timeout value */
1285 bp
->cmd_req_virt
->cmd_type
= PI_CMD_K_CHARS_SET
;
1286 bp
->cmd_req_virt
->char_set
.item
[0].item_code
= PI_ITEM_K_FLUSH_TIME
;
1287 bp
->cmd_req_virt
->char_set
.item
[0].value
= 3; /* 3 seconds */
1288 bp
->cmd_req_virt
->char_set
.item
[0].item_index
= 0;
1289 bp
->cmd_req_virt
->char_set
.item
[1].item_code
= PI_ITEM_K_EOL
;
1290 if (dfx_hw_dma_cmd_req(bp
) != DFX_K_SUCCESS
)
1292 printk("%s: DMA command request failed!\n", bp
->dev
->name
);
1293 return(DFX_K_FAILURE
);
1296 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1298 bp
->cmd_req_virt
->cmd_type
= PI_CMD_K_SNMP_SET
;
1299 bp
->cmd_req_virt
->snmp_set
.item
[0].item_code
= PI_ITEM_K_FDX_ENB_DIS
;
1300 bp
->cmd_req_virt
->snmp_set
.item
[0].value
= bp
->full_duplex_enb
;
1301 bp
->cmd_req_virt
->snmp_set
.item
[0].item_index
= 0;
1302 bp
->cmd_req_virt
->snmp_set
.item
[1].item_code
= PI_ITEM_K_MAC_T_REQ
;
1303 bp
->cmd_req_virt
->snmp_set
.item
[1].value
= bp
->req_ttrt
;
1304 bp
->cmd_req_virt
->snmp_set
.item
[1].item_index
= 0;
1305 bp
->cmd_req_virt
->snmp_set
.item
[2].item_code
= PI_ITEM_K_EOL
;
1306 if (dfx_hw_dma_cmd_req(bp
) != DFX_K_SUCCESS
)
1308 printk("%s: DMA command request failed!\n", bp
->dev
->name
);
1309 return(DFX_K_FAILURE
);
1312 /* Initialize adapter CAM */
1314 if (dfx_ctl_update_cam(bp
) != DFX_K_SUCCESS
)
1316 printk("%s: Adapter CAM update failed!\n", bp
->dev
->name
);
1317 return(DFX_K_FAILURE
);
1320 /* Initialize adapter filters */
1322 if (dfx_ctl_update_filters(bp
) != DFX_K_SUCCESS
)
1324 printk("%s: Adapter filters update failed!\n", bp
->dev
->name
);
1325 return(DFX_K_FAILURE
);
1328 /* Initialize receive descriptor block and produce buffers */
1332 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1334 bp
->cmd_req_virt
->cmd_type
= PI_CMD_K_START
;
1335 if (dfx_hw_dma_cmd_req(bp
) != DFX_K_SUCCESS
)
1337 printk("%s: Start command failed\n", bp
->dev
->name
);
1338 return(DFX_K_FAILURE
);
1341 /* Initialization succeeded, reenable PDQ interrupts */
1343 dfx_port_write_long(bp
, PI_PDQ_K_REG_HOST_INT_ENB
, PI_HOST_INT_K_ENABLE_DEF_INTS
);
1344 return(DFX_K_SUCCESS
);
1360 * dev - pointer to device information
1362 * Functional Description:
1363 * This function brings the adapter to an operational state.
1366 * 0 - Adapter was successfully opened
1367 * -EAGAIN - Could not register IRQ or adapter initialization failed
1370 * This routine should only be called for a device that was
1371 * initialized successfully during the dfx_probe process.
1374 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1375 * if the open is successful.
1383 DFX_board_t
*bp
= (DFX_board_t
*)dev
->priv
;
1385 DBG_printk("In dfx_open...\n");
1387 /* Register IRQ - support shared interrupts by passing device ptr */
1389 if (request_irq(dev
->irq
, (void *)dfx_interrupt
, SA_SHIRQ
, dev
->name
, dev
))
1391 printk("%s: Requested IRQ %d is busy\n", dev
->name
, dev
->irq
);
1396 * Set current address to factory MAC address
1398 * Note: We've already done this step in dfx_driver_init.
1399 * However, it's possible that a user has set a node
1400 * address override, then closed and reopened the
1401 * adapter. Unless we reset the device address field
1402 * now, we'll continue to use the existing modified
1406 memcpy(dev
->dev_addr
, bp
->factory_mac_addr
, FDDI_K_ALEN
);
1408 /* Clear local unicast/multicast address tables and counts */
1410 memset(bp
->uc_table
, 0, sizeof(bp
->uc_table
));
1411 memset(bp
->mc_table
, 0, sizeof(bp
->mc_table
));
1415 /* Disable promiscuous filter settings */
1417 bp
->ind_group_prom
= PI_FSTATE_K_BLOCK
;
1418 bp
->group_prom
= PI_FSTATE_K_BLOCK
;
1420 /* Reset and initialize adapter */
1422 bp
->reset_type
= PI_PDATA_A_RESET_M_SKIP_ST
; /* skip self-test */
1423 if (dfx_adap_init(bp
) != DFX_K_SUCCESS
)
1425 printk("%s: Adapter open failed!\n", dev
->name
);
1429 /* Set device structure info */
1432 dev
->interrupt
= DFX_UNMASK_INTERRUPTS
;
1444 * Closes the device/module.
1450 * dev - pointer to device information
1452 * Functional Description:
1453 * This routine closes the adapter and brings it to a safe state.
1454 * The interrupt service routine is deregistered with the OS.
1455 * The adapter can be opened again with another call to dfx_open().
1461 * No further requests for this adapter are made after this routine is
1462 * called. dfx_open() can be called to reset and reinitialize the
1466 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1475 DFX_board_t
*bp
= (DFX_board_t
*)dev
->priv
;
1477 DBG_printk("In dfx_close...\n");
1479 /* Disable PDQ interrupts first */
1481 dfx_port_write_long(bp
, PI_PDQ_K_REG_HOST_INT_ENB
, PI_HOST_INT_K_DISABLE_ALL_INTS
);
1483 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1485 (void) dfx_hw_dma_uninit(bp
, PI_PDATA_A_RESET_M_SKIP_ST
);
1488 * Flush any pending transmit buffers
1490 * Note: It's important that we flush the transmit buffers
1491 * BEFORE we clear our copy of the Type 2 register.
1492 * Otherwise, we'll have no idea how many buffers
1499 * Clear Type 1 and Type 2 registers after adapter reset
1501 * Note: Even though we're closing the adapter, it's
1502 * possible that an interrupt will occur after
1503 * dfx_close is called. Without some assurance to
1504 * the contrary we want to make sure that we don't
1505 * process receive and transmit LLC frames and update
1506 * the Type 2 register with bad information.
1509 bp
->cmd_req_reg
.lword
= 0;
1510 bp
->cmd_rsp_reg
.lword
= 0;
1511 bp
->rcv_xmt_reg
.lword
= 0;
1513 /* Clear consumer block for the same reason given above */
1515 memset(bp
->cons_block_virt
, 0, sizeof(PI_CONSUMER_BLOCK
));
1517 /* Clear device structure flags */
1522 /* Deregister (free) IRQ */
1524 free_irq(dev
->irq
, dev
);
1530 * ======================
1531 * = dfx_int_pr_halt_id =
1532 * ======================
1535 * Displays halt id's in string form.
1541 * bp - pointer to board information
1543 * Functional Description:
1544 * Determine current halt id and display appropriate string.
1556 void dfx_int_pr_halt_id(
1561 PI_UINT32 port_status
; /* PDQ port status register value */
1562 PI_UINT32 halt_id
; /* PDQ port status halt ID */
1564 /* Read the latest port status */
1566 dfx_port_read_long(bp
, PI_PDQ_K_REG_PORT_STATUS
, &port_status
);
1568 /* Display halt state transition information */
1570 halt_id
= (port_status
& PI_PSTATUS_M_HALT_ID
) >> PI_PSTATUS_V_HALT_ID
;
1573 case PI_HALT_ID_K_SELFTEST_TIMEOUT
:
1574 printk("%s: Halt ID: Selftest Timeout\n", bp
->dev
->name
);
1577 case PI_HALT_ID_K_PARITY_ERROR
:
1578 printk("%s: Halt ID: Host Bus Parity Error\n", bp
->dev
->name
);
1581 case PI_HALT_ID_K_HOST_DIR_HALT
:
1582 printk("%s: Halt ID: Host-Directed Halt\n", bp
->dev
->name
);
1585 case PI_HALT_ID_K_SW_FAULT
:
1586 printk("%s: Halt ID: Adapter Software Fault\n", bp
->dev
->name
);
1589 case PI_HALT_ID_K_HW_FAULT
:
1590 printk("%s: Halt ID: Adapter Hardware Fault\n", bp
->dev
->name
);
1593 case PI_HALT_ID_K_PC_TRACE
:
1594 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp
->dev
->name
);
1597 case PI_HALT_ID_K_DMA_ERROR
:
1598 printk("%s: Halt ID: Adapter DMA Error\n", bp
->dev
->name
);
1601 case PI_HALT_ID_K_IMAGE_CRC_ERROR
:
1602 printk("%s: Halt ID: Firmware Image CRC Error\n", bp
->dev
->name
);
1605 case PI_HALT_ID_K_BUS_EXCEPTION
:
1606 printk("%s: Halt ID: 68000 Bus Exception\n", bp
->dev
->name
);
1610 printk("%s: Halt ID: Unknown (code = %X)\n", bp
->dev
->name
, halt_id
);
1618 * ==========================
1619 * = dfx_int_type_0_process =
1620 * ==========================
1623 * Processes Type 0 interrupts.
1629 * bp - pointer to board information
1631 * Functional Description:
1632 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1633 * is a serious fault on the adapter, then an error message is displayed
1634 * and the adapter is reset.
1636 * One tricky potential timing window is the rapid succession of "link avail"
1637 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1638 * interrupt must be done before reading the state from the Port Status
1639 * register. This is true because a state change could occur after reading
1640 * the data, but before acknowledging the interrupt. If this state change
1641 * does happen, it would be lost because the driver is using the old state,
1642 * and it will never know about the new state because it subsequently
1643 * acknowledges the state change interrupt.
1646 * read type 0 int reasons read type 0 int reasons
1647 * read adapter state ack type 0 interrupts
1648 * ack type 0 interrupts read adapter state
1649 * ... process interrupt ... ... process interrupt ...
1658 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1659 * or if the port status indicates that the adapter is halted. The driver
1660 * is responsible for reinitializing the adapter with the current CAM
1661 * contents and adapter filter settings.
1664 void dfx_int_type_0_process(
1669 PI_UINT32 type_0_status
; /* Host Interrupt Type 0 register */
1670 PI_UINT32 state
; /* current adap state (from port status) */
1673 * Read host interrupt Type 0 register to determine which Type 0
1674 * interrupts are pending. Immediately write it back out to clear
1678 dfx_port_read_long(bp
, PI_PDQ_K_REG_TYPE_0_STATUS
, &type_0_status
);
1679 dfx_port_write_long(bp
, PI_PDQ_K_REG_TYPE_0_STATUS
, type_0_status
);
1681 /* Check for Type 0 error interrupts */
1683 if (type_0_status
& (PI_TYPE_0_STAT_M_NXM
|
1684 PI_TYPE_0_STAT_M_PM_PAR_ERR
|
1685 PI_TYPE_0_STAT_M_BUS_PAR_ERR
))
1687 /* Check for Non-Existent Memory error */
1689 if (type_0_status
& PI_TYPE_0_STAT_M_NXM
)
1690 printk("%s: Non-Existent Memory Access Error\n", bp
->dev
->name
);
1692 /* Check for Packet Memory Parity error */
1694 if (type_0_status
& PI_TYPE_0_STAT_M_PM_PAR_ERR
)
1695 printk("%s: Packet Memory Parity Error\n", bp
->dev
->name
);
1697 /* Check for Host Bus Parity error */
1699 if (type_0_status
& PI_TYPE_0_STAT_M_BUS_PAR_ERR
)
1700 printk("%s: Host Bus Parity Error\n", bp
->dev
->name
);
1702 /* Reset adapter and bring it back on-line */
1704 bp
->link_available
= PI_K_FALSE
; /* link is no longer available */
1705 bp
->reset_type
= 0; /* rerun on-board diagnostics */
1706 printk("%s: Resetting adapter...\n", bp
->dev
->name
);
1707 if (dfx_adap_init(bp
) != DFX_K_SUCCESS
)
1709 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp
->dev
->name
);
1710 dfx_port_write_long(bp
, PI_PDQ_K_REG_HOST_INT_ENB
, PI_HOST_INT_K_DISABLE_ALL_INTS
);
1713 printk("%s: Adapter reset successful!\n", bp
->dev
->name
);
1717 /* Check for transmit flush interrupt */
1719 if (type_0_status
& PI_TYPE_0_STAT_M_XMT_FLUSH
)
1721 /* Flush any pending xmt's and acknowledge the flush interrupt */
1723 bp
->link_available
= PI_K_FALSE
; /* link is no longer available */
1724 dfx_xmt_flush(bp
); /* flush any outstanding packets */
1725 (void) dfx_hw_port_ctrl_req(bp
,
1726 PI_PCTRL_M_XMT_DATA_FLUSH_DONE
,
1732 /* Check for adapter state change */
1734 if (type_0_status
& PI_TYPE_0_STAT_M_STATE_CHANGE
)
1736 /* Get latest adapter state */
1738 state
= dfx_hw_adap_state_rd(bp
); /* get adapter state */
1739 if (state
== PI_STATE_K_HALTED
)
1742 * Adapter has transitioned to HALTED state, try to reset
1743 * adapter to bring it back on-line. If reset fails,
1744 * leave the adapter in the broken state.
1747 printk("%s: Controller has transitioned to HALTED state!\n", bp
->dev
->name
);
1748 dfx_int_pr_halt_id(bp
); /* display halt id as string */
1750 /* Reset adapter and bring it back on-line */
1752 bp
->link_available
= PI_K_FALSE
; /* link is no longer available */
1753 bp
->reset_type
= 0; /* rerun on-board diagnostics */
1754 printk("%s: Resetting adapter...\n", bp
->dev
->name
);
1755 if (dfx_adap_init(bp
) != DFX_K_SUCCESS
)
1757 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp
->dev
->name
);
1758 dfx_port_write_long(bp
, PI_PDQ_K_REG_HOST_INT_ENB
, PI_HOST_INT_K_DISABLE_ALL_INTS
);
1761 printk("%s: Adapter reset successful!\n", bp
->dev
->name
);
1763 else if (state
== PI_STATE_K_LINK_AVAIL
)
1765 bp
->link_available
= PI_K_TRUE
; /* set link available flag */
1773 * ==================
1774 * = dfx_int_common =
1775 * ==================
1778 * Interrupt service routine (ISR)
1784 * bp - pointer to board information
1786 * Functional Description:
1787 * This is the ISR which processes incoming adapter interrupts.
1793 * This routine assumes PDQ interrupts have not been disabled.
1794 * When interrupts are disabled at the PDQ, the Port Status register
1795 * is automatically cleared. This routine uses the Port Status
1796 * register value to determine whether a Type 0 interrupt occurred,
1797 * so it's important that adapter interrupts are not normally
1798 * enabled/disabled at the PDQ.
1800 * It's vital that this routine is NOT reentered for the
1801 * same board and that the OS is not in another section of
1802 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1806 * Pending interrupts are serviced. Depending on the type of
1807 * interrupt, acknowledging and clearing the interrupt at the
1808 * PDQ involves writing a register to clear the interrupt bit
1809 * or updating completion indices.
1812 void dfx_int_common(
1817 PI_UINT32 port_status
; /* Port Status register */
1819 /* Process xmt interrupts - frequent case, so always call this routine */
1821 dfx_xmt_done(bp
); /* free consumed xmt packets */
1823 /* Process rcv interrupts - frequent case, so always call this routine */
1825 dfx_rcv_queue_process(bp
); /* service received LLC frames */
1828 * Transmit and receive producer and completion indices are updated on the
1829 * adapter by writing to the Type 2 Producer register. Since the frequent
1830 * case is that we'll be processing either LLC transmit or receive buffers,
1831 * we'll optimize I/O writes by doing a single register write here.
1834 dfx_port_write_long(bp
, PI_PDQ_K_REG_TYPE_2_PROD
, bp
->rcv_xmt_reg
.lword
);
1836 /* Read PDQ Port Status register to find out which interrupts need processing */
1838 dfx_port_read_long(bp
, PI_PDQ_K_REG_PORT_STATUS
, &port_status
);
1840 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1842 if (port_status
& PI_PSTATUS_M_TYPE_0_PENDING
)
1843 dfx_int_type_0_process(bp
); /* process Type 0 interrupts */
1854 * Interrupt processing routine
1860 * irq - interrupt vector
1861 * dev_id - pointer to device information
1862 * regs - pointer to registers structure
1864 * Functional Description:
1865 * This routine calls the interrupt processing routine for this adapter. It
1866 * disables and reenables adapter interrupts, as appropriate. We can support
1867 * shared interrupts since the incoming dev_id pointer provides our device
1868 * structure context.
1874 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1875 * on Intel-based systems) is done by the operating system outside this
1878 * System interrupts are enabled through this call.
1881 * Interrupts are disabled, then reenabled at the adapter.
1887 struct pt_regs
*regs
1891 struct device
*dev
= (struct device
*) dev_id
;
1892 DFX_board_t
*bp
; /* private board structure pointer */
1893 u8 tmp
; /* used for disabling/enabling ints */
1895 /* Get board pointer only if device structure is valid */
1899 printk("dfx_interrupt(): irq %d for unknown device!\n", irq
);
1902 bp
= (DFX_board_t
*) dev
->priv
;
1904 /* See if we're already servicing an interrupt */
1907 printk("%s: Re-entering the interrupt handler!\n", dev
->name
);
1908 dev
->interrupt
= DFX_MASK_INTERRUPTS
; /* ensure non reentrancy */
1910 /* Service adapter interrupts */
1912 if (bp
->bus_type
== DFX_BUS_TYPE_PCI
)
1914 /* Disable PDQ-PFI interrupts at PFI */
1916 dfx_port_write_long(bp
, PFI_K_REG_MODE_CTRL
, PFI_MODE_M_DMA_ENB
);
1918 /* Call interrupt service routine for this adapter */
1922 /* Clear PDQ interrupt status bit and reenable interrupts */
1924 dfx_port_write_long(bp
, PFI_K_REG_STATUS
, PFI_STATUS_M_PDQ_INT
);
1925 dfx_port_write_long(bp
, PFI_K_REG_MODE_CTRL
,
1926 (PFI_MODE_M_PDQ_INT_ENB
+ PFI_MODE_M_DMA_ENB
));
1930 /* Disable interrupts at the ESIC */
1932 dfx_port_read_byte(bp
, PI_ESIC_K_IO_CONFIG_STAT_0
, &tmp
);
1933 tmp
&= ~PI_CONFIG_STAT_0_M_INT_ENB
;
1934 dfx_port_write_byte(bp
, PI_ESIC_K_IO_CONFIG_STAT_0
, tmp
);
1936 /* Call interrupt service routine for this adapter */
1940 /* Reenable interrupts at the ESIC */
1942 dfx_port_read_byte(bp
, PI_ESIC_K_IO_CONFIG_STAT_0
, &tmp
);
1943 tmp
|= PI_CONFIG_STAT_0_M_INT_ENB
;
1944 dfx_port_write_byte(bp
, PI_ESIC_K_IO_CONFIG_STAT_0
, tmp
);
1947 dev
->interrupt
= DFX_UNMASK_INTERRUPTS
;
1953 * =====================
1954 * = dfx_ctl_get_stats =
1955 * =====================
1958 * Get statistics for FDDI adapter
1961 * Pointer to FDDI statistics structure
1964 * dev - pointer to device information
1966 * Functional Description:
1967 * Gets current MIB objects from adapter, then
1968 * returns FDDI statistics structure as defined
1971 * Note: Since the FDDI statistics structure is
1972 * still new and the device structure doesn't
1973 * have an FDDI-specific get statistics handler,
1974 * we'll return the FDDI statistics structure as
1975 * a pointer to an Ethernet statistics structure.
1976 * That way, at least the first part of the statistics
1977 * structure can be decoded properly, and it allows
1978 * "smart" applications to perform a second cast to
1979 * decode the FDDI-specific statistics.
1981 * We'll have to pay attention to this routine as the
1982 * device structure becomes more mature and LAN media
1995 struct net_device_stats
*dfx_ctl_get_stats(
2000 DFX_board_t
*bp
= (DFX_board_t
*)dev
->priv
;
2002 /* Fill the bp->stats structure with driver-maintained counters */
2004 bp
->stats
.rx_packets
= bp
->rcv_total_frames
;
2005 bp
->stats
.tx_packets
= bp
->xmt_total_frames
;
2006 bp
->stats
.rx_errors
= (u32
)(bp
->rcv_crc_errors
+ bp
->rcv_frame_status_errors
+ bp
->rcv_length_errors
);
2007 bp
->stats
.tx_errors
= bp
->xmt_length_errors
;
2008 bp
->stats
.rx_dropped
= bp
->rcv_discards
;
2009 bp
->stats
.tx_dropped
= bp
->xmt_discards
;
2010 bp
->stats
.multicast
= bp
->rcv_multicast_frames
;
2011 bp
->stats
.transmit_collision
= 0; /* always zero (0) for FDDI */
2013 /* Get FDDI SMT MIB objects */
2015 bp
->cmd_req_virt
->cmd_type
= PI_CMD_K_SMT_MIB_GET
;
2016 if (dfx_hw_dma_cmd_req(bp
) != DFX_K_SUCCESS
)
2017 return((struct net_device_stats
*) &bp
->stats
);
2019 /* Fill the bp->stats structure with the SMT MIB object values */
2021 memcpy(bp
->stats
.smt_station_id
, &bp
->cmd_rsp_virt
->smt_mib_get
.smt_station_id
, sizeof(bp
->cmd_rsp_virt
->smt_mib_get
.smt_station_id
));
2022 bp
->stats
.smt_op_version_id
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_op_version_id
;
2023 bp
->stats
.smt_hi_version_id
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_hi_version_id
;
2024 bp
->stats
.smt_lo_version_id
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_lo_version_id
;
2025 memcpy(bp
->stats
.smt_user_data
, &bp
->cmd_rsp_virt
->smt_mib_get
.smt_user_data
, sizeof(bp
->cmd_rsp_virt
->smt_mib_get
.smt_user_data
));
2026 bp
->stats
.smt_mib_version_id
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_mib_version_id
;
2027 bp
->stats
.smt_mac_cts
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_mac_ct
;
2028 bp
->stats
.smt_non_master_cts
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_non_master_ct
;
2029 bp
->stats
.smt_master_cts
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_master_ct
;
2030 bp
->stats
.smt_available_paths
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_available_paths
;
2031 bp
->stats
.smt_config_capabilities
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_config_capabilities
;
2032 bp
->stats
.smt_config_policy
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_config_policy
;
2033 bp
->stats
.smt_connection_policy
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_connection_policy
;
2034 bp
->stats
.smt_t_notify
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_t_notify
;
2035 bp
->stats
.smt_stat_rpt_policy
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_stat_rpt_policy
;
2036 bp
->stats
.smt_trace_max_expiration
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_trace_max_expiration
;
2037 bp
->stats
.smt_bypass_present
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_bypass_present
;
2038 bp
->stats
.smt_ecm_state
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_ecm_state
;
2039 bp
->stats
.smt_cf_state
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_cf_state
;
2040 bp
->stats
.smt_remote_disconnect_flag
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_remote_disconnect_flag
;
2041 bp
->stats
.smt_station_status
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_station_status
;
2042 bp
->stats
.smt_peer_wrap_flag
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_peer_wrap_flag
;
2043 bp
->stats
.smt_time_stamp
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_msg_time_stamp
.ls
;
2044 bp
->stats
.smt_transition_time_stamp
= bp
->cmd_rsp_virt
->smt_mib_get
.smt_transition_time_stamp
.ls
;
2045 bp
->stats
.mac_frame_status_functions
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_frame_status_functions
;
2046 bp
->stats
.mac_t_max_capability
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_t_max_capability
;
2047 bp
->stats
.mac_tvx_capability
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_tvx_capability
;
2048 bp
->stats
.mac_available_paths
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_available_paths
;
2049 bp
->stats
.mac_current_path
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_current_path
;
2050 memcpy(bp
->stats
.mac_upstream_nbr
, &bp
->cmd_rsp_virt
->smt_mib_get
.mac_upstream_nbr
, FDDI_K_ALEN
);
2051 memcpy(bp
->stats
.mac_downstream_nbr
, &bp
->cmd_rsp_virt
->smt_mib_get
.mac_downstream_nbr
, FDDI_K_ALEN
);
2052 memcpy(bp
->stats
.mac_old_upstream_nbr
, &bp
->cmd_rsp_virt
->smt_mib_get
.mac_old_upstream_nbr
, FDDI_K_ALEN
);
2053 memcpy(bp
->stats
.mac_old_downstream_nbr
, &bp
->cmd_rsp_virt
->smt_mib_get
.mac_old_downstream_nbr
, FDDI_K_ALEN
);
2054 bp
->stats
.mac_dup_address_test
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_dup_address_test
;
2055 bp
->stats
.mac_requested_paths
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_requested_paths
;
2056 bp
->stats
.mac_downstream_port_type
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_downstream_port_type
;
2057 memcpy(bp
->stats
.mac_smt_address
, &bp
->cmd_rsp_virt
->smt_mib_get
.mac_smt_address
, FDDI_K_ALEN
);
2058 bp
->stats
.mac_t_req
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_t_req
;
2059 bp
->stats
.mac_t_neg
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_t_neg
;
2060 bp
->stats
.mac_t_max
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_t_max
;
2061 bp
->stats
.mac_tvx_value
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_tvx_value
;
2062 bp
->stats
.mac_frame_error_threshold
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_frame_error_threshold
;
2063 bp
->stats
.mac_frame_error_ratio
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_frame_error_ratio
;
2064 bp
->stats
.mac_rmt_state
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_rmt_state
;
2065 bp
->stats
.mac_da_flag
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_da_flag
;
2066 bp
->stats
.mac_una_da_flag
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_unda_flag
;
2067 bp
->stats
.mac_frame_error_flag
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_frame_error_flag
;
2068 bp
->stats
.mac_ma_unitdata_available
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_ma_unitdata_available
;
2069 bp
->stats
.mac_hardware_present
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_hardware_present
;
2070 bp
->stats
.mac_ma_unitdata_enable
= bp
->cmd_rsp_virt
->smt_mib_get
.mac_ma_unitdata_enable
;
2071 bp
->stats
.path_tvx_lower_bound
= bp
->cmd_rsp_virt
->smt_mib_get
.path_tvx_lower_bound
;
2072 bp
->stats
.path_t_max_lower_bound
= bp
->cmd_rsp_virt
->smt_mib_get
.path_t_max_lower_bound
;
2073 bp
->stats
.path_max_t_req
= bp
->cmd_rsp_virt
->smt_mib_get
.path_max_t_req
;
2074 memcpy(bp
->stats
.path_configuration
, &bp
->cmd_rsp_virt
->smt_mib_get
.path_configuration
, sizeof(bp
->cmd_rsp_virt
->smt_mib_get
.path_configuration
));
2075 bp
->stats
.port_my_type
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_my_type
[0];
2076 bp
->stats
.port_my_type
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_my_type
[1];
2077 bp
->stats
.port_neighbor_type
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_neighbor_type
[0];
2078 bp
->stats
.port_neighbor_type
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_neighbor_type
[1];
2079 bp
->stats
.port_connection_policies
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_connection_policies
[0];
2080 bp
->stats
.port_connection_policies
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_connection_policies
[1];
2081 bp
->stats
.port_mac_indicated
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_mac_indicated
[0];
2082 bp
->stats
.port_mac_indicated
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_mac_indicated
[1];
2083 bp
->stats
.port_current_path
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_current_path
[0];
2084 bp
->stats
.port_current_path
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_current_path
[1];
2085 memcpy(&bp
->stats
.port_requested_paths
[0*3], &bp
->cmd_rsp_virt
->smt_mib_get
.port_requested_paths
[0], 3);
2086 memcpy(&bp
->stats
.port_requested_paths
[1*3], &bp
->cmd_rsp_virt
->smt_mib_get
.port_requested_paths
[1], 3);
2087 bp
->stats
.port_mac_placement
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_mac_placement
[0];
2088 bp
->stats
.port_mac_placement
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_mac_placement
[1];
2089 bp
->stats
.port_available_paths
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_available_paths
[0];
2090 bp
->stats
.port_available_paths
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_available_paths
[1];
2091 bp
->stats
.port_pmd_class
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_pmd_class
[0];
2092 bp
->stats
.port_pmd_class
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_pmd_class
[1];
2093 bp
->stats
.port_connection_capabilities
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_connection_capabilities
[0];
2094 bp
->stats
.port_connection_capabilities
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_connection_capabilities
[1];
2095 bp
->stats
.port_bs_flag
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_bs_flag
[0];
2096 bp
->stats
.port_bs_flag
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_bs_flag
[1];
2097 bp
->stats
.port_ler_estimate
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_ler_estimate
[0];
2098 bp
->stats
.port_ler_estimate
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_ler_estimate
[1];
2099 bp
->stats
.port_ler_cutoff
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_ler_cutoff
[0];
2100 bp
->stats
.port_ler_cutoff
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_ler_cutoff
[1];
2101 bp
->stats
.port_ler_alarm
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_ler_alarm
[0];
2102 bp
->stats
.port_ler_alarm
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_ler_alarm
[1];
2103 bp
->stats
.port_connect_state
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_connect_state
[0];
2104 bp
->stats
.port_connect_state
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_connect_state
[1];
2105 bp
->stats
.port_pcm_state
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_pcm_state
[0];
2106 bp
->stats
.port_pcm_state
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_pcm_state
[1];
2107 bp
->stats
.port_pc_withhold
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_pc_withhold
[0];
2108 bp
->stats
.port_pc_withhold
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_pc_withhold
[1];
2109 bp
->stats
.port_ler_flag
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_ler_flag
[0];
2110 bp
->stats
.port_ler_flag
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_ler_flag
[1];
2111 bp
->stats
.port_hardware_present
[0] = bp
->cmd_rsp_virt
->smt_mib_get
.port_hardware_present
[0];
2112 bp
->stats
.port_hardware_present
[1] = bp
->cmd_rsp_virt
->smt_mib_get
.port_hardware_present
[1];
2114 /* Get FDDI counters */
2116 bp
->cmd_req_virt
->cmd_type
= PI_CMD_K_CNTRS_GET
;
2117 if (dfx_hw_dma_cmd_req(bp
) != DFX_K_SUCCESS
)
2118 return((struct net_device_stats
*) &bp
->stats
);
2120 /* Fill the bp->stats structure with the FDDI counter values */
2122 bp
->stats
.mac_frame_cts
= bp
->cmd_rsp_virt
->cntrs_get
.cntrs
.frame_cnt
.ls
;
2123 bp
->stats
.mac_copied_cts
= bp
->cmd_rsp_virt
->cntrs_get
.cntrs
.copied_cnt
.ls
;
2124 bp
->stats
.mac_transmit_cts
= bp
->cmd_rsp_virt
->cntrs_get
.cntrs
.transmit_cnt
.ls
;
2125 bp
->stats
.mac_error_cts
= bp
->cmd_rsp_virt
->cntrs_get
.cntrs
.error_cnt
.ls
;
2126 bp
->stats
.mac_lost_cts
= bp
->cmd_rsp_virt
->cntrs_get
.cntrs
.lost_cnt
.ls
;
2127 bp
->stats
.port_lct_fail_cts
[0] = bp
->cmd_rsp_virt
->cntrs_get
.cntrs
.lct_rejects
[0].ls
;
2128 bp
->stats
.port_lct_fail_cts
[1] = bp
->cmd_rsp_virt
->cntrs_get
.cntrs
.lct_rejects
[1].ls
;
2129 bp
->stats
.port_lem_reject_cts
[0] = bp
->cmd_rsp_virt
->cntrs_get
.cntrs
.lem_rejects
[0].ls
;
2130 bp
->stats
.port_lem_reject_cts
[1] = bp
->cmd_rsp_virt
->cntrs_get
.cntrs
.lem_rejects
[1].ls
;
2131 bp
->stats
.port_lem_cts
[0] = bp
->cmd_rsp_virt
->cntrs_get
.cntrs
.link_errors
[0].ls
;
2132 bp
->stats
.port_lem_cts
[1] = bp
->cmd_rsp_virt
->cntrs_get
.cntrs
.link_errors
[1].ls
;
2134 return((struct net_device_stats
*) &bp
->stats
);
2139 * ==============================
2140 * = dfx_ctl_set_multicast_list =
2141 * ==============================
2144 * Enable/Disable LLC frame promiscuous mode reception
2145 * on the adapter and/or update multicast address table.
2151 * dev - pointer to device information
2153 * Functional Description:
2154 * This routine follows a fairly simple algorithm for setting the
2155 * adapter filters and CAM:
2157 * if IFF_PROMISC flag is set
2158 * enable LLC individual/group promiscuous mode
2160 * disable LLC individual/group promiscuous mode
2161 * if number of incoming multicast addresses >
2162 * (CAM max size - number of unicast addresses in CAM)
2163 * enable LLC group promiscuous mode
2164 * set driver-maintained multicast address count to zero
2166 * disable LLC group promiscuous mode
2167 * set driver-maintained multicast address count to incoming count
2168 * update adapter CAM
2169 * update adapter filters
2175 * Multicast addresses are presented in canonical (LSB) format.
2178 * On-board adapter CAM and filters are updated.
2181 void dfx_ctl_set_multicast_list(
2186 DFX_board_t
*bp
= (DFX_board_t
*)dev
->priv
;
2187 int i
; /* used as index in for loop */
2188 struct dev_mc_list
*dmi
; /* ptr to multicast addr entry */
2190 /* Enable LLC frame promiscuous mode, if necessary */
2192 if (dev
->flags
& IFF_PROMISC
)
2193 bp
->ind_group_prom
= PI_FSTATE_K_PASS
; /* Enable LLC ind/group prom mode */
2195 /* Else, update multicast address table */
2199 bp
->ind_group_prom
= PI_FSTATE_K_BLOCK
; /* Disable LLC ind/group prom mode */
2201 * Check whether incoming multicast address count exceeds table size
2203 * Note: The adapters utilize an on-board 64 entry CAM for
2204 * supporting perfect filtering of multicast packets
2205 * and bridge functions when adding unicast addresses.
2206 * There is no hash function available. To support
2207 * additional multicast addresses, the all multicast
2208 * filter (LLC group promiscuous mode) must be enabled.
2210 * The firmware reserves two CAM entries for SMT-related
2211 * multicast addresses, which leaves 62 entries available.
2212 * The following code ensures that we're not being asked
2213 * to add more than 62 addresses to the CAM. If we are,
2214 * the driver will enable the all multicast filter.
2215 * Should the number of multicast addresses drop below
2216 * the high water mark, the filter will be disabled and
2217 * perfect filtering will be used.
2220 if (dev
->mc_count
> (PI_CMD_ADDR_FILTER_K_SIZE
- bp
->uc_count
))
2222 bp
->group_prom
= PI_FSTATE_K_PASS
; /* Enable LLC group prom mode */
2223 bp
->mc_count
= 0; /* Don't add mc addrs to CAM */
2227 bp
->group_prom
= PI_FSTATE_K_BLOCK
; /* Disable LLC group prom mode */
2228 bp
->mc_count
= dev
->mc_count
; /* Add mc addrs to CAM */
2231 /* Copy addresses to multicast address table, then update adapter CAM */
2233 dmi
= dev
->mc_list
; /* point to first multicast addr */
2234 for (i
=0; i
< bp
->mc_count
; i
++)
2236 memcpy(&bp
->mc_table
[i
*FDDI_K_ALEN
], dmi
->dmi_addr
, FDDI_K_ALEN
);
2237 dmi
= dmi
->next
; /* point to next multicast addr */
2239 if (dfx_ctl_update_cam(bp
) != DFX_K_SUCCESS
)
2241 DBG_printk("%s: Could not update multicast address table!\n", dev
->name
);
2245 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev
->name
, bp
->mc_count
);
2249 /* Update adapter filters */
2251 if (dfx_ctl_update_filters(bp
) != DFX_K_SUCCESS
)
2253 DBG_printk("%s: Could not update adapter filters!\n", dev
->name
);
2257 DBG_printk("%s: Adapter filters updated!\n", dev
->name
);
2264 * ===========================
2265 * = dfx_ctl_set_mac_address =
2266 * ===========================
2269 * Add node address override (unicast address) to adapter
2270 * CAM and update dev_addr field in device table.
2276 * dev - pointer to device information
2277 * addr - pointer to sockaddr structure containing unicast address to add
2279 * Functional Description:
2280 * The adapter supports node address overrides by adding one or more
2281 * unicast addresses to the adapter CAM. This is similar to adding
2282 * multicast addresses. In this routine we'll update the driver and
2283 * device structures with the new address, then update the adapter CAM
2284 * to ensure that the adapter will copy and strip frames destined and
2285 * sourced by that address.
2288 * Always returns zero.
2291 * The address pointed to by addr->sa_data is a valid unicast
2292 * address and is presented in canonical (LSB) format.
2295 * On-board adapter CAM is updated. On-board adapter filters
2299 int dfx_ctl_set_mac_address(
2305 DFX_board_t
*bp
= (DFX_board_t
*)dev
->priv
;
2306 struct sockaddr
*p_sockaddr
= (struct sockaddr
*)addr
;
2308 /* Copy unicast address to driver-maintained structs and update count */
2310 memcpy(dev
->dev_addr
, p_sockaddr
->sa_data
, FDDI_K_ALEN
); /* update device struct */
2311 memcpy(&bp
->uc_table
[0], p_sockaddr
->sa_data
, FDDI_K_ALEN
); /* update driver struct */
2315 * Verify we're not exceeding the CAM size by adding unicast address
2317 * Note: It's possible that before entering this routine we've
2318 * already filled the CAM with 62 multicast addresses.
2319 * Since we need to place the node address override into
2320 * the CAM, we have to check to see that we're not
2321 * exceeding the CAM size. If we are, we have to enable
2322 * the LLC group (multicast) promiscuous mode filter as
2323 * in dfx_ctl_set_multicast_list.
2326 if ((bp
->uc_count
+ bp
->mc_count
) > PI_CMD_ADDR_FILTER_K_SIZE
)
2328 bp
->group_prom
= PI_FSTATE_K_PASS
; /* Enable LLC group prom mode */
2329 bp
->mc_count
= 0; /* Don't add mc addrs to CAM */
2331 /* Update adapter filters */
2333 if (dfx_ctl_update_filters(bp
) != DFX_K_SUCCESS
)
2335 DBG_printk("%s: Could not update adapter filters!\n", dev
->name
);
2339 DBG_printk("%s: Adapter filters updated!\n", dev
->name
);
2343 /* Update adapter CAM with new unicast address */
2345 if (dfx_ctl_update_cam(bp
) != DFX_K_SUCCESS
)
2347 DBG_printk("%s: Could not set new MAC address!\n", dev
->name
);
2351 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev
->name
);
2353 return(0); /* always return zero */
2358 * ======================
2359 * = dfx_ctl_update_cam =
2360 * ======================
2363 * Procedure to update adapter CAM (Content Addressable Memory)
2364 * with desired unicast and multicast address entries.
2370 * bp - pointer to board information
2372 * Functional Description:
2373 * Updates adapter CAM with current contents of board structure
2374 * unicast and multicast address tables. Since there are only 62
2375 * free entries in CAM, this routine ensures that the command
2376 * request buffer is not overrun.
2379 * DFX_K_SUCCESS - Request succeeded
2380 * DFX_K_FAILURE - Request failed
2383 * All addresses being added (unicast and multicast) are in canonical
2387 * On-board adapter CAM is updated.
2390 int dfx_ctl_update_cam(
2395 int i
; /* used as index */
2396 PI_LAN_ADDR
*p_addr
; /* pointer to CAM entry */
2399 * Fill in command request information
2401 * Note: Even though both the unicast and multicast address
2402 * table entries are stored as contiguous 6 byte entries,
2403 * the firmware address filter set command expects each
2404 * entry to be two longwords (8 bytes total). We must be
2405 * careful to only copy the six bytes of each unicast and
2406 * multicast table entry into each command entry. This
2407 * is also why we must first clear the entire command
2411 memset(bp
->cmd_req_virt
, 0, PI_CMD_REQ_K_SIZE_MAX
); /* first clear buffer */
2412 bp
->cmd_req_virt
->cmd_type
= PI_CMD_K_ADDR_FILTER_SET
;
2413 p_addr
= &bp
->cmd_req_virt
->addr_filter_set
.entry
[0];
2415 /* Now add unicast addresses to command request buffer, if any */
2417 for (i
=0; i
< (int)bp
->uc_count
; i
++)
2419 if (i
< PI_CMD_ADDR_FILTER_K_SIZE
)
2421 memcpy(p_addr
, &bp
->uc_table
[i
*FDDI_K_ALEN
], FDDI_K_ALEN
);
2422 p_addr
++; /* point to next command entry */
2426 /* Now add multicast addresses to command request buffer, if any */
2428 for (i
=0; i
< (int)bp
->mc_count
; i
++)
2430 if ((i
+ bp
->uc_count
) < PI_CMD_ADDR_FILTER_K_SIZE
)
2432 memcpy(p_addr
, &bp
->mc_table
[i
*FDDI_K_ALEN
], FDDI_K_ALEN
);
2433 p_addr
++; /* point to next command entry */
2437 /* Issue command to update adapter CAM, then return */
2439 if (dfx_hw_dma_cmd_req(bp
) != DFX_K_SUCCESS
)
2440 return(DFX_K_FAILURE
);
2441 return(DFX_K_SUCCESS
);
2446 * ==========================
2447 * = dfx_ctl_update_filters =
2448 * ==========================
2451 * Procedure to update adapter filters with desired
2458 * bp - pointer to board information
2460 * Functional Description:
2461 * Enables or disables filter using current filter settings.
2464 * DFX_K_SUCCESS - Request succeeded.
2465 * DFX_K_FAILURE - Request failed.
2468 * We must always pass up packets destined to the broadcast
2469 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2470 * broadcast filter enabled.
2473 * On-board adapter filters are updated.
2476 int dfx_ctl_update_filters(
2481 int i
= 0; /* used as index */
2483 /* Fill in command request information */
2485 bp
->cmd_req_virt
->cmd_type
= PI_CMD_K_FILTERS_SET
;
2487 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2489 bp
->cmd_req_virt
->filter_set
.item
[i
].item_code
= PI_ITEM_K_BROADCAST
;
2490 bp
->cmd_req_virt
->filter_set
.item
[i
++].value
= PI_FSTATE_K_PASS
;
2492 /* Initialize LLC Individual/Group Promiscuous filter */
2494 bp
->cmd_req_virt
->filter_set
.item
[i
].item_code
= PI_ITEM_K_IND_GROUP_PROM
;
2495 bp
->cmd_req_virt
->filter_set
.item
[i
++].value
= bp
->ind_group_prom
;
2497 /* Initialize LLC Group Promiscuous filter */
2499 bp
->cmd_req_virt
->filter_set
.item
[i
].item_code
= PI_ITEM_K_GROUP_PROM
;
2500 bp
->cmd_req_virt
->filter_set
.item
[i
++].value
= bp
->group_prom
;
2502 /* Terminate the item code list */
2504 bp
->cmd_req_virt
->filter_set
.item
[i
].item_code
= PI_ITEM_K_EOL
;
2506 /* Issue command to update adapter filters, then return */
2508 if (dfx_hw_dma_cmd_req(bp
) != DFX_K_SUCCESS
)
2509 return(DFX_K_FAILURE
);
2510 return(DFX_K_SUCCESS
);
2515 * ======================
2516 * = dfx_hw_dma_cmd_req =
2517 * ======================
2520 * Sends PDQ DMA command to adapter firmware
2526 * bp - pointer to board information
2528 * Functional Description:
2529 * The command request and response buffers are posted to the adapter in the manner
2530 * described in the PDQ Port Specification:
2532 * 1. Command Response Buffer is posted to adapter.
2533 * 2. Command Request Buffer is posted to adapter.
2534 * 3. Command Request consumer index is polled until it indicates that request
2535 * buffer has been DMA'd to adapter.
2536 * 4. Command Response consumer index is polled until it indicates that response
2537 * buffer has been DMA'd from adapter.
2539 * This ordering ensures that a response buffer is already available for the firmware
2540 * to use once it's done processing the request buffer.
2543 * DFX_K_SUCCESS - DMA command succeeded
2544 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2545 * DFX_K_HW_TIMEOUT - DMA command timed out
2548 * Command request buffer has already been filled with desired DMA command.
2554 int dfx_hw_dma_cmd_req(
2559 int status
; /* adapter status */
2560 int timeout_cnt
; /* used in for loops */
2562 /* Make sure the adapter is in a state that we can issue the DMA command in */
2564 status
= dfx_hw_adap_state_rd(bp
);
2565 if ((status
== PI_STATE_K_RESET
) ||
2566 (status
== PI_STATE_K_HALTED
) ||
2567 (status
== PI_STATE_K_DMA_UNAVAIL
) ||
2568 (status
== PI_STATE_K_UPGRADE
))
2569 return(DFX_K_OUTSTATE
);
2571 /* Put response buffer on the command response queue */
2573 bp
->descr_block_virt
->cmd_rsp
[bp
->cmd_rsp_reg
.index
.prod
].long_0
= (u32
) (PI_RCV_DESCR_M_SOP
|
2574 ((PI_CMD_RSP_K_SIZE_MAX
/ PI_ALIGN_K_CMD_RSP_BUFF
) << PI_RCV_DESCR_V_SEG_LEN
));
2575 bp
->descr_block_virt
->cmd_rsp
[bp
->cmd_rsp_reg
.index
.prod
].long_1
= bp
->cmd_rsp_phys
;
2577 /* Bump (and wrap) the producer index and write out to register */
2579 bp
->cmd_rsp_reg
.index
.prod
+= 1;
2580 bp
->cmd_rsp_reg
.index
.prod
&= PI_CMD_RSP_K_NUM_ENTRIES
-1;
2581 dfx_port_write_long(bp
, PI_PDQ_K_REG_CMD_RSP_PROD
, bp
->cmd_rsp_reg
.lword
);
2583 /* Put request buffer on the command request queue */
2585 bp
->descr_block_virt
->cmd_req
[bp
->cmd_req_reg
.index
.prod
].long_0
= (u32
) (PI_XMT_DESCR_M_SOP
|
2586 PI_XMT_DESCR_M_EOP
| (PI_CMD_REQ_K_SIZE_MAX
<< PI_XMT_DESCR_V_SEG_LEN
));
2587 bp
->descr_block_virt
->cmd_req
[bp
->cmd_req_reg
.index
.prod
].long_1
= bp
->cmd_req_phys
;
2589 /* Bump (and wrap) the producer index and write out to register */
2591 bp
->cmd_req_reg
.index
.prod
+= 1;
2592 bp
->cmd_req_reg
.index
.prod
&= PI_CMD_REQ_K_NUM_ENTRIES
-1;
2593 dfx_port_write_long(bp
, PI_PDQ_K_REG_CMD_REQ_PROD
, bp
->cmd_req_reg
.lword
);
2596 * Here we wait for the command request consumer index to be equal
2597 * to the producer, indicating that the adapter has DMAed the request.
2600 for (timeout_cnt
= 20000; timeout_cnt
> 0; timeout_cnt
--)
2602 if (bp
->cmd_req_reg
.index
.prod
== (u8
)(bp
->cons_block_virt
->cmd_req
))
2604 udelay(100); /* wait for 100 microseconds */
2606 if (timeout_cnt
== 0)
2607 return(DFX_K_HW_TIMEOUT
);
2609 /* Bump (and wrap) the completion index and write out to register */
2611 bp
->cmd_req_reg
.index
.comp
+= 1;
2612 bp
->cmd_req_reg
.index
.comp
&= PI_CMD_REQ_K_NUM_ENTRIES
-1;
2613 dfx_port_write_long(bp
, PI_PDQ_K_REG_CMD_REQ_PROD
, bp
->cmd_req_reg
.lword
);
2616 * Here we wait for the command response consumer index to be equal
2617 * to the producer, indicating that the adapter has DMAed the response.
2620 for (timeout_cnt
= 20000; timeout_cnt
> 0; timeout_cnt
--)
2622 if (bp
->cmd_rsp_reg
.index
.prod
== (u8
)(bp
->cons_block_virt
->cmd_rsp
))
2624 udelay(100); /* wait for 100 microseconds */
2626 if (timeout_cnt
== 0)
2627 return(DFX_K_HW_TIMEOUT
);
2629 /* Bump (and wrap) the completion index and write out to register */
2631 bp
->cmd_rsp_reg
.index
.comp
+= 1;
2632 bp
->cmd_rsp_reg
.index
.comp
&= PI_CMD_RSP_K_NUM_ENTRIES
-1;
2633 dfx_port_write_long(bp
, PI_PDQ_K_REG_CMD_RSP_PROD
, bp
->cmd_rsp_reg
.lword
);
2634 return(DFX_K_SUCCESS
);
2639 * ========================
2640 * = dfx_hw_port_ctrl_req =
2641 * ========================
2644 * Sends PDQ port control command to adapter firmware
2647 * Host data register value in host_data if ptr is not NULL
2650 * bp - pointer to board information
2651 * command - port control command
2652 * data_a - port data A register value
2653 * data_b - port data B register value
2654 * host_data - ptr to host data register value
2656 * Functional Description:
2657 * Send generic port control command to adapter by writing
2658 * to various PDQ port registers, then polling for completion.
2661 * DFX_K_SUCCESS - port control command succeeded
2662 * DFX_K_HW_TIMEOUT - port control command timed out
2671 int dfx_hw_port_ctrl_req(
2676 PI_UINT32
*host_data
2680 PI_UINT32 port_cmd
; /* Port Control command register value */
2681 int timeout_cnt
; /* used in for loops */
2683 /* Set Command Error bit in command longword */
2685 port_cmd
= (PI_UINT32
) (command
| PI_PCTRL_M_CMD_ERROR
);
2687 /* Issue port command to the adapter */
2689 dfx_port_write_long(bp
, PI_PDQ_K_REG_PORT_DATA_A
, data_a
);
2690 dfx_port_write_long(bp
, PI_PDQ_K_REG_PORT_DATA_B
, data_b
);
2691 dfx_port_write_long(bp
, PI_PDQ_K_REG_PORT_CTRL
, port_cmd
);
2693 /* Now wait for command to complete */
2695 if (command
== PI_PCTRL_M_BLAST_FLASH
)
2696 timeout_cnt
= 600000; /* set command timeout count to 60 seconds */
2698 timeout_cnt
= 20000; /* set command timeout count to 2 seconds */
2700 for (; timeout_cnt
> 0; timeout_cnt
--)
2702 dfx_port_read_long(bp
, PI_PDQ_K_REG_PORT_CTRL
, &port_cmd
);
2703 if (!(port_cmd
& PI_PCTRL_M_CMD_ERROR
))
2705 udelay(100); /* wait for 100 microseconds */
2707 if (timeout_cnt
== 0)
2708 return(DFX_K_HW_TIMEOUT
);
2711 * If the address of host_data is non-zero, assume caller has supplied a
2712 * non NULL pointer, and return the contents of the HOST_DATA register in
2716 if (host_data
!= NULL
)
2717 dfx_port_read_long(bp
, PI_PDQ_K_REG_HOST_DATA
, host_data
);
2718 return(DFX_K_SUCCESS
);
2723 * =====================
2724 * = dfx_hw_adap_reset =
2725 * =====================
2734 * bp - pointer to board information
2735 * type - type of reset to perform
2737 * Functional Description:
2738 * Issue soft reset to adapter by writing to PDQ Port Reset
2739 * register. Use incoming reset type to tell adapter what
2740 * kind of reset operation to perform.
2746 * This routine merely issues a soft reset to the adapter.
2747 * It is expected that after this routine returns, the caller
2748 * will appropriately poll the Port Status register for the
2749 * adapter to enter the proper state.
2752 * Internal adapter registers are cleared.
2755 void dfx_hw_adap_reset(
2761 /* Set Reset type and assert reset */
2763 dfx_port_write_long(bp
, PI_PDQ_K_REG_PORT_DATA_A
, type
); /* tell adapter type of reset */
2764 dfx_port_write_long(bp
, PI_PDQ_K_REG_PORT_RESET
, PI_RESET_M_ASSERT_RESET
);
2766 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2770 /* Deassert reset */
2772 dfx_port_write_long(bp
, PI_PDQ_K_REG_PORT_RESET
, 0);
2778 * ========================
2779 * = dfx_hw_adap_state_rd =
2780 * ========================
2783 * Returns current adapter state
2786 * Adapter state per PDQ Port Specification
2789 * bp - pointer to board information
2791 * Functional Description:
2792 * Reads PDQ Port Status register and returns adapter state.
2804 int dfx_hw_adap_state_rd(
2809 PI_UINT32 port_status
; /* Port Status register value */
2811 dfx_port_read_long(bp
, PI_PDQ_K_REG_PORT_STATUS
, &port_status
);
2812 return((port_status
& PI_PSTATUS_M_STATE
) >> PI_PSTATUS_V_STATE
);
2817 * =====================
2818 * = dfx_hw_dma_uninit =
2819 * =====================
2822 * Brings adapter to DMA_UNAVAILABLE state
2828 * bp - pointer to board information
2829 * type - type of reset to perform
2831 * Functional Description:
2832 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2833 * 1. Set reset type bit in Port Data A Register then reset adapter.
2834 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2837 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2838 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2844 * Internal adapter registers are cleared.
2847 int dfx_hw_dma_uninit(
2853 int timeout_cnt
; /* used in for loops */
2855 /* Set reset type bit and reset adapter */
2857 dfx_hw_adap_reset(bp
, type
);
2859 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2861 for (timeout_cnt
= 100000; timeout_cnt
> 0; timeout_cnt
--)
2863 if (dfx_hw_adap_state_rd(bp
) == PI_STATE_K_DMA_UNAVAIL
)
2865 udelay(100); /* wait for 100 microseconds */
2867 if (timeout_cnt
== 0)
2868 return(DFX_K_HW_TIMEOUT
);
2869 return(DFX_K_SUCCESS
);
2879 * Produces buffers to adapter LLC Host receive descriptor block
2885 * bp - pointer to board information
2887 * Functional Description:
2888 * This routine can be called during dfx_adap_init() or during an adapter
2889 * reset. It initializes the descriptor block and produces all allocated
2890 * LLC Host queue receive buffers.
2896 * The PDQ has been reset and the adapter and driver maintained Type 2
2897 * register indices are cleared.
2900 * Receive buffers are posted to the adapter LLC queue and the adapter
2909 int i
, j
; /* used in for loop */
2912 * Since each receive buffer is a single fragment of same length, initialize
2913 * first longword in each receive descriptor for entire LLC Host descriptor
2914 * block. Also initialize second longword in each receive descriptor with
2915 * physical address of receive buffer. We'll always allocate receive
2916 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2917 * block and produce new receive buffers by simply updating the receive
2921 * To support all shipping versions of PDQ, the receive buffer size
2922 * must be mod 128 in length and the physical address must be 128 byte
2923 * aligned. In other words, bits 0-6 of the length and address must
2924 * be zero for the following descriptor field entries to be correct on
2925 * all PDQ-based boards. We guaranteed both requirements during
2926 * driver initialization when we allocated memory for the receive buffers.
2929 for (i
=0; i
< (int)(bp
->rcv_bufs_to_post
); i
++)
2930 for (j
=0; (i
+ j
) < (int)PI_RCV_DATA_K_NUM_ENTRIES
; j
+= bp
->rcv_bufs_to_post
)
2932 bp
->descr_block_virt
->rcv_data
[i
+j
].long_0
= (u32
) (PI_RCV_DESCR_M_SOP
|
2933 ((PI_RCV_DATA_K_SIZE_MAX
/ PI_ALIGN_K_RCV_DATA_BUFF
) << PI_RCV_DESCR_V_SEG_LEN
));
2934 bp
->descr_block_virt
->rcv_data
[i
+j
].long_1
= (u32
) (bp
->rcv_block_phys
+ (i
* PI_RCV_DATA_K_SIZE_MAX
));
2935 bp
->p_rcv_buff_va
[i
+j
] = (char *) (bp
->rcv_block_virt
+ (i
* PI_RCV_DATA_K_SIZE_MAX
));
2938 /* Update receive producer and Type 2 register */
2940 bp
->rcv_xmt_reg
.index
.rcv_prod
= bp
->rcv_bufs_to_post
;
2941 dfx_port_write_long(bp
, PI_PDQ_K_REG_TYPE_2_PROD
, bp
->rcv_xmt_reg
.lword
);
2947 * =========================
2948 * = dfx_rcv_queue_process =
2949 * =========================
2952 * Process received LLC frames.
2958 * bp - pointer to board information
2960 * Functional Description:
2961 * Received LLC frames are processed until there are no more consumed frames.
2962 * Once all frames are processed, the receive buffers are returned to the
2963 * adapter. Note that this algorithm fixes the length of time that can be spent
2964 * in this routine, because there are a fixed number of receive buffers to
2965 * process and buffers are not produced until this routine exits and returns
2978 void dfx_rcv_queue_process(
2983 PI_TYPE_2_CONSUMER
*p_type_2_cons
; /* ptr to rcv/xmt consumer block register */
2984 char *p_buff
; /* ptr to start of packet receive buffer (FMC descriptor) */
2985 u32 descr
, pkt_len
; /* FMC descriptor field and packet length */
2986 struct sk_buff
*skb
; /* pointer to a sk_buff to hold incoming packet data */
2988 /* Service all consumed LLC receive frames */
2990 p_type_2_cons
= (PI_TYPE_2_CONSUMER
*)(&bp
->cons_block_virt
->xmt_rcv_data
);
2991 while (bp
->rcv_xmt_reg
.index
.rcv_comp
!= p_type_2_cons
->index
.rcv_cons
)
2993 /* Process any errors */
2995 p_buff
= (char *) bp
->p_rcv_buff_va
[bp
->rcv_xmt_reg
.index
.rcv_comp
];
2996 memcpy(&descr
, p_buff
+ RCV_BUFF_K_DESCR
, sizeof(u32
));
2998 if (descr
& PI_FMC_DESCR_M_RCC_FLUSH
)
3000 if (descr
& PI_FMC_DESCR_M_RCC_CRC
)
3001 bp
->rcv_crc_errors
++;
3003 bp
->rcv_frame_status_errors
++;
3007 /* The frame was received without errors - verify packet length */
3009 pkt_len
= (u32
)((descr
& PI_FMC_DESCR_M_LEN
) >> PI_FMC_DESCR_V_LEN
);
3010 pkt_len
-= 4; /* subtract 4 byte CRC */
3011 if (!IN_RANGE(pkt_len
, FDDI_K_LLC_ZLEN
, FDDI_K_LLC_LEN
))
3012 bp
->rcv_length_errors
++;
3015 skb
= dev_alloc_skb(pkt_len
+3); /* alloc new buffer to pass up, add room for PRH */
3018 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp
->dev
->name
);
3023 /* Receive buffer allocated, pass receive packet up */
3025 memcpy(skb
->data
, p_buff
+ RCV_BUFF_K_PADDING
, pkt_len
+3);
3026 skb
->data
+= 3; /* adjust data field so that it points to FC byte */
3027 skb
->len
= pkt_len
; /* pass up packet length, NOT including CRC */
3028 skb
->dev
= bp
->dev
; /* pass up device pointer */
3029 skb
->protocol
= fddi_type_trans(skb
, bp
->dev
);
3032 /* Update the rcv counters */
3034 bp
->rcv_total_frames
++;
3035 if (*(p_buff
+ RCV_BUFF_K_DA
) & 0x01)
3036 bp
->rcv_multicast_frames
++;
3042 * Advance the producer (for recycling) and advance the completion
3043 * (for servicing received frames). Note that it is okay to
3044 * advance the producer without checking that it passes the
3045 * completion index because they are both advanced at the same
3049 bp
->rcv_xmt_reg
.index
.rcv_prod
+= 1;
3050 bp
->rcv_xmt_reg
.index
.rcv_comp
+= 1;
3057 * =====================
3058 * = dfx_xmt_queue_pkt =
3059 * =====================
3062 * Queues packets for transmission
3068 * skb - pointer to sk_buff to queue for transmission
3069 * dev - pointer to device information
3071 * Functional Description:
3072 * Here we assume that an incoming skb transmit request
3073 * is contained in a single physically contiguous buffer
3074 * in which the virtual address of the start of packet
3075 * (skb->data) can be converted to a physical address
3076 * by using virt_to_bus().
3078 * Since the adapter architecture requires a three byte
3079 * packet request header to prepend the start of packet,
3080 * we'll write the three byte field immediately prior to
3081 * the FC byte. This assumption is valid because we've
3082 * ensured that dev->hard_header_len includes three pad
3083 * bytes. By posting a single fragment to the adapter,
3084 * we'll reduce the number of descriptor fetches and
3085 * bus traffic needed to send the request.
3087 * Also, we can't free the skb until after it's been DMA'd
3088 * out by the adapter, so we'll queue it in the driver and
3089 * return it in dfx_xmt_done.
3092 * 0 - driver queued packet, link is unavailable, or skbuff was bad
3093 * 1 - caller should requeue the sk_buff for later transmission
3096 * First and foremost, we assume the incoming skb pointer
3097 * is NOT NULL and is pointing to a valid sk_buff structure.
3099 * The outgoing packet is complete, starting with the
3100 * frame control byte including the last byte of data,
3101 * but NOT including the 4 byte CRC. We'll let the
3102 * adapter hardware generate and append the CRC.
3104 * The entire packet is stored in one physically
3105 * contiguous buffer which is not cached and whose
3106 * 32-bit physical address can be determined.
3108 * It's vital that this routine is NOT reentered for the
3109 * same board and that the OS is not in another section of
3110 * code (eg. dfx_int_common) for the same board on a
3117 int dfx_xmt_queue_pkt(
3118 struct sk_buff
*skb
,
3123 DFX_board_t
*bp
= (DFX_board_t
*) dev
->priv
;
3124 u8 prod
; /* local transmit producer index */
3125 PI_XMT_DESCR
*p_xmt_descr
; /* ptr to transmit descriptor block entry */
3126 XMT_DRIVER_DESCR
*p_xmt_drv_descr
; /* ptr to transmit driver descriptor */
3129 * Verify that incoming transmit request is OK
3131 * Note: The packet size check is consistent with other
3132 * Linux device drivers, although the correct packet
3133 * size should be verified before calling the
3137 if (!IN_RANGE(skb
->len
, FDDI_K_LLC_ZLEN
, FDDI_K_LLC_LEN
))
3139 printk("%s: Invalid packet length - %u bytes\n",
3140 dev
->name
, skb
->len
);
3141 bp
->xmt_length_errors
++; /* bump error counter */
3142 dev_tint(dev
); /* dequeue packets from xmt queue and send them */
3143 return(0); /* return "success" */
3146 * See if adapter link is available, if not, free buffer
3148 * Note: If the link isn't available, free buffer and return 0
3149 * rather than tell the upper layer to requeue the packet.
3150 * The methodology here is that by the time the link
3151 * becomes available, the packet to be sent will be
3152 * fairly stale. By simply dropping the packet, the
3153 * higher layer protocols will eventually time out
3154 * waiting for response packets which it won't receive.
3157 if (bp
->link_available
== PI_K_FALSE
)
3159 if (dfx_hw_adap_state_rd(bp
) == PI_STATE_K_LINK_AVAIL
) /* is link really available? */
3160 bp
->link_available
= PI_K_TRUE
; /* if so, set flag and continue */
3163 bp
->xmt_discards
++; /* bump error counter */
3164 dev_kfree_skb(skb
, FREE_WRITE
); /* free sk_buff now */
3165 return(0); /* return "success" */
3169 /* Get the current producer and the next free xmt data descriptor */
3171 prod
= bp
->rcv_xmt_reg
.index
.xmt_prod
;
3172 p_xmt_descr
= &(bp
->descr_block_virt
->xmt_data
[prod
]);
3175 * Get pointer to auxiliary queue entry to contain information for this packet.
3177 * Note: The current xmt producer index will become the current xmt completion
3178 * index when we complete this packet later on. So, we'll get the
3179 * pointer to the next auxiliary queue entry now before we bump the
3183 p_xmt_drv_descr
= &(bp
->xmt_drv_descr_blk
[prod
++]); /* also bump producer index */
3185 /* Write the three PRH bytes immediately before the FC byte */
3187 *((char *)skb
->data
- 3) = DFX_PRH0_BYTE
; /* these byte values are defined */
3188 *((char *)skb
->data
- 2) = DFX_PRH1_BYTE
; /* in the Motorola FDDI MAC chip */
3189 *((char *)skb
->data
- 1) = DFX_PRH2_BYTE
; /* specification */
3192 * Write the descriptor with buffer info and bump producer
3194 * Note: Since we need to start DMA from the packet request
3195 * header, we'll add 3 bytes to the DMA buffer length,
3196 * and we'll determine the physical address of the
3197 * buffer from the PRH, not skb->data.
3200 * 1. Packet starts with the frame control (FC) byte
3202 * 2. The 4-byte CRC is not appended to the buffer or
3203 * included in the length.
3204 * 3. Packet length (skb->len) is from FC to end of
3206 * 4. The packet length does not exceed the maximum
3207 * FDDI LLC frame length of 4491 bytes.
3208 * 5. The entire packet is contained in a physically
3209 * contiguous, non-cached, locked memory space
3210 * comprised of a single buffer pointed to by
3212 * 6. The physical address of the start of packet
3213 * can be determined from the virtual address
3214 * by using virt_to_bus() and is only 32-bits
3218 p_xmt_descr
->long_0
= (u32
) (PI_XMT_DESCR_M_SOP
| PI_XMT_DESCR_M_EOP
| ((skb
->len
+ 3) << PI_XMT_DESCR_V_SEG_LEN
));
3219 p_xmt_descr
->long_1
= (u32
) virt_to_bus(skb
->data
- 3);
3222 * Verify that descriptor is actually available
3224 * Note: If descriptor isn't available, return 1 which tells
3225 * the upper layer to requeue the packet for later
3228 * We need to ensure that the producer never reaches the
3229 * completion, except to indicate that the queue is empty.
3232 if (prod
== bp
->rcv_xmt_reg
.index
.xmt_comp
)
3233 return(1); /* requeue packet for later */
3236 * Save info for this packet for xmt done indication routine
3238 * Normally, we'd save the producer index in the p_xmt_drv_descr
3239 * structure so that we'd have it handy when we complete this
3240 * packet later (in dfx_xmt_done). However, since the current
3241 * transmit architecture guarantees a single fragment for the
3242 * entire packet, we can simply bump the completion index by
3243 * one (1) for each completed packet.
3245 * Note: If this assumption changes and we're presented with
3246 * an inconsistent number of transmit fragments for packet
3247 * data, we'll need to modify this code to save the current
3248 * transmit producer index.
3251 p_xmt_drv_descr
->p_skb
= skb
;
3253 /* Update Type 2 register */
3255 bp
->rcv_xmt_reg
.index
.xmt_prod
= prod
;
3256 dfx_port_write_long(bp
, PI_PDQ_K_REG_TYPE_2_PROD
, bp
->rcv_xmt_reg
.lword
);
3257 return(0); /* packet queued to adapter */
3267 * Processes all frames that have been transmitted.
3273 * bp - pointer to board information
3275 * Functional Description:
3276 * For all consumed transmit descriptors that have not
3277 * yet been completed, we'll free the skb we were holding
3278 * onto using dev_kfree_skb and bump the appropriate
3285 * The Type 2 register is not updated in this routine. It is
3286 * assumed that it will be updated in the ISR when dfx_xmt_done
3298 XMT_DRIVER_DESCR
*p_xmt_drv_descr
; /* ptr to transmit driver descriptor */
3299 PI_TYPE_2_CONSUMER
*p_type_2_cons
; /* ptr to rcv/xmt consumer block register */
3301 /* Service all consumed transmit frames */
3303 p_type_2_cons
= (PI_TYPE_2_CONSUMER
*)(&bp
->cons_block_virt
->xmt_rcv_data
);
3304 while (bp
->rcv_xmt_reg
.index
.xmt_comp
!= p_type_2_cons
->index
.xmt_cons
)
3306 /* Get pointer to the transmit driver descriptor block information */
3308 p_xmt_drv_descr
= &(bp
->xmt_drv_descr_blk
[bp
->rcv_xmt_reg
.index
.xmt_comp
]);
3310 /* Return skb to operating system */
3312 dev_kfree_skb(p_xmt_drv_descr
->p_skb
, FREE_WRITE
);
3314 /* Increment transmit counters */
3316 bp
->xmt_total_frames
++;
3319 * Move to start of next packet by updating completion index
3321 * Here we assume that a transmit packet request is always
3322 * serviced by posting one fragment. We can therefore
3323 * simplify the completion code by incrementing the
3324 * completion index by one. This code will need to be
3325 * modified if this assumption changes. See comments
3326 * in dfx_xmt_queue_pkt for more details.
3329 bp
->rcv_xmt_reg
.index
.xmt_comp
+= 1;
3341 * Processes all frames whether they've been transmitted
3348 * bp - pointer to board information
3350 * Functional Description:
3351 * For all produced transmit descriptors that have not
3352 * yet been completed, we'll free the skb we were holding
3353 * onto using dev_kfree_skb and bump the appropriate
3354 * counters. Of course, it's possible that some of
3355 * these transmit requests actually did go out, but we
3356 * won't make that distinction here. Finally, we'll
3357 * update the consumer index to match the producer.
3363 * This routine does NOT update the Type 2 register. It
3364 * is assumed that this routine is being called during a
3365 * transmit flush interrupt, or a shutdown or close routine.
3376 u32 prod_cons
; /* rcv/xmt consumer block longword */
3377 XMT_DRIVER_DESCR
*p_xmt_drv_descr
; /* ptr to transmit driver descriptor */
3379 /* Flush all outstanding transmit frames */
3381 while (bp
->rcv_xmt_reg
.index
.xmt_comp
!= bp
->rcv_xmt_reg
.index
.xmt_prod
)
3383 /* Get pointer to the transmit driver descriptor block information */
3385 p_xmt_drv_descr
= &(bp
->xmt_drv_descr_blk
[bp
->rcv_xmt_reg
.index
.xmt_comp
]);
3387 /* Return skb to operating system */
3389 dev_kfree_skb(p_xmt_drv_descr
->p_skb
, FREE_WRITE
);
3391 /* Increment transmit error counter */
3396 * Move to start of next packet by updating completion index
3398 * Here we assume that a transmit packet request is always
3399 * serviced by posting one fragment. We can therefore
3400 * simplify the completion code by incrementing the
3401 * completion index by one. This code will need to be
3402 * modified if this assumption changes. See comments
3403 * in dfx_xmt_queue_pkt for more details.
3406 bp
->rcv_xmt_reg
.index
.xmt_comp
+= 1;
3409 /* Update the transmit consumer index in the consumer block */
3411 prod_cons
= (u32
)(bp
->cons_block_virt
->xmt_rcv_data
& ~PI_CONS_M_XMT_INDEX
);
3412 prod_cons
|= (u32
)(bp
->rcv_xmt_reg
.index
.xmt_prod
<< PI_CONS_V_XMT_INDEX
);
3413 bp
->cons_block_virt
->xmt_rcv_data
= prod_cons
;
3420 * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -DCPU=586 -c defxx.c"