drivers/pci/quirks.c

   1 /*
   2  * $Id: quirks.c,v 1.5 1998/05/02 19:24:14 mj Exp $
   3  *
   4  *  This file contains work-arounds for many known PCI hardware
   5  *  bugs.  Devices present only on certain architectures (host
   6  *  bridges et cetera) should be handled in arch-specific code.
   7  *
   8  *  Copyright (c) 1999 Martin Mares <mj@suse.cz>
   9  *
  10  *  The bridge optimization stuff has been removed. If you really
  11  *  have a silly BIOS which is unable to set your host bridge right,
  12  *  use the PowerTweak utility (see http://powertweak.sourceforge.net).
  13  */
  14
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19
  20 #undef DEBUG
  21
  22 /* Deal with broken BIOS'es that neglect to enable passive release,
  23    which can cause problems in combination with the 82441FX/PPro MTRRs */
  24 static void __init quirk_passive_release(struct pci_dev *dev)
  25 {
  26         struct pci_dev *d = NULL;
  27         unsigned char dlc;
  28
  29         /* We have to make sure a particular bit is set in the PIIX3
  30            ISA bridge, so we have to go out and find it. */
  31         while ((d = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
  32                 pci_read_config_byte(d, 0x82, &dlc);
  33                 if (!(dlc & 1<<1)) {
  34                         printk("PCI: PIIX3: Enabling Passive Release on %s\n", d->slot_name);
  35                         dlc |= 1<<1;
  36                         pci_write_config_byte(d, 0x82, dlc);
  37                 }
  38         }
  39 }
  40
  41 /*  The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
  42     but VIA don't answer queries. If you happen to have good contacts at VIA
  43     ask them for me please -- Alan
  44
  45     This appears to be BIOS not version dependent. So presumably there is a
  46     chipset level fix */
  47
  48
  49 int isa_dma_bridge_buggy = 0;           /* Exported */
  50
  51 static void __init quirk_isa_dma_hangs(struct pci_dev *dev)
  52 {
  53         if (!isa_dma_bridge_buggy) {
  54                 isa_dma_bridge_buggy=1;
  55                 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
  56         }
  57 }
  58
  59 int pci_pci_problems = 0;
  60
  61 /*
  62  *      Chipsets where PCI->PCI transfers vanish or hang
  63  */
  64
  65 static void __init quirk_nopcipci(struct pci_dev *dev)
  66 {
  67         if((pci_pci_problems&PCIPCI_FAIL)==0)
  68         {
  69                 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
  70                 pci_pci_problems|=PCIPCI_FAIL;
  71         }
  72 }
  73
  74 /*
  75  *      Triton requires workarounds to be used by the drivers
  76  */
  77
  78 static void __init quirk_triton(struct pci_dev *dev)
  79 {
  80         if((pci_pci_problems&PCIPCI_TRITON)==0)
  81         {
  82                 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  83                 pci_pci_problems|=PCIPCI_TRITON;
  84         }
  85 }
  86
  87 /*
  88  *      Natoma has some interesting boundary conditions with Zoran stuff
  89  *      at least
  90  */
  91
  92 static void __init quirk_natoma(struct pci_dev *dev)
  93 {
  94         if((pci_pci_problems&PCIPCI_NATOMA)==0)
  95         {
  96                 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  97                 pci_pci_problems|=PCIPCI_NATOMA;
  98         }
  99 }
 100
 101 /*
 102  *  S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
 103  *  If it's needed, re-allocate the region.
 104  */
 105
 106 static void __init quirk_s3_64M(struct pci_dev *dev)
 107 {
 108         struct resource *r = &dev->resource[0];
 109
 110         if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
 111                 r->start = 0;
 112                 r->end = 0x3ffffff;
 113         }
 114 }
 115
 116 static void __init quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
 117 {
 118         region &= ~(size-1);
 119         if (region) {
 120                 struct resource *res = dev->resource + nr;
 121
 122                 res->name = dev->name;
 123                 res->start = region;
 124                 res->end = region + size - 1;
 125                 res->flags = IORESOURCE_IO;
 126                 pci_claim_resource(dev, nr);
 127         }
 128 }
 129
 130 /*
 131  * Let's make the southbridge information explicit instead
 132  * of having to worry about people probing the ACPI areas,
 133  * for example.. (Yes, it happens, and if you read the wrong
 134  * ACPI register it will put the machine to sleep with no
 135  * way of waking it up again. Bummer).
 136  *
 137  * ALI M7101: Two IO regions pointed to by words at
 138  *      0xE0 (64 bytes of ACPI registers)
 139  *      0xE2 (32 bytes of SMB registers)
 140  */
 141 static void __init quirk_ali7101_acpi(struct pci_dev *dev)
 142 {
 143         u16 region;
 144
 145         pci_read_config_word(dev, 0xE0, &region);
 146         quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
 147         pci_read_config_word(dev, 0xE2, &region);
 148         quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
 149 }
 150
 151 /*
 152  * PIIX4 ACPI: Two IO regions pointed to by longwords at
 153  *      0x40 (64 bytes of ACPI registers)
 154  *      0x90 (32 bytes of SMB registers)
 155  */
 156 static void __init quirk_piix4_acpi(struct pci_dev *dev)
 157 {
 158         u32 region;
 159
 160         pci_read_config_dword(dev, 0x40, &region);
 161         quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
 162         pci_read_config_dword(dev, 0x90, &region);
 163         quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
 164 }
 165
 166 /*
 167  * VIA ACPI: One IO region pointed to by longword at
 168  *      0x48 or 0x20 (256 bytes of ACPI registers)
 169  */
 170 static void __init quirk_vt82c586_acpi(struct pci_dev *dev)
 171 {
 172         u8 rev;
 173         u32 region;
 174
 175         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
 176         if (rev & 0x10) {
 177                 pci_read_config_dword(dev, 0x48, &region);
 178                 region &= PCI_BASE_ADDRESS_IO_MASK;
 179                 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
 180         }
 181 }
 182
 183 /*
 184  * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
 185  *      0x48 (256 bytes of ACPI registers)
 186  *      0x70 (128 bytes of hardware monitoring register)
 187  *      0x90 (16 bytes of SMB registers)
 188  */
 189 static void __init quirk_vt82c686_acpi(struct pci_dev *dev)
 190 {
 191         u16 hm;
 192         u32 smb;
 193
 194         quirk_vt82c586_acpi(dev);
 195
 196         pci_read_config_word(dev, 0x70, &hm);
 197         hm &= PCI_BASE_ADDRESS_IO_MASK;
 198         quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
 199
 200         pci_read_config_dword(dev, 0x90, &smb);
 201         smb &= PCI_BASE_ADDRESS_IO_MASK;
 202         quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
 203 }
 204
 205 /*
 206  * PIIX3 USB: We have to disable USB interrupts that are
 207  * hardwired to PIRQD# and may be shared with an
 208  * external device.
 209  *
 210  * Legacy Support Register (LEGSUP):
 211  *     bit13:  USB PIRQ Enable (USBPIRQDEN),
 212  *     bit4:   Trap/SMI ON IRQ Enable (USBSMIEN).
 213  *
 214  * We mask out all r/wc bits, too.
 215  */
 216 static void __init quirk_piix3usb(struct pci_dev *dev)
 217 {
 218         u16 legsup;
 219
 220         pci_read_config_word(dev, 0xc0, &legsup);
 221         legsup &= 0x50ef;
 222         pci_write_config_word(dev, 0xc0, legsup);
 223 }
 224
 225 /*
 226  * VIA VT82C598 has its device ID settable and many BIOSes
 227  * set it to the ID of VT82C597 for backward compatibility.
 228  * We need to switch it off to be able to recognize the real
 229  * type of the chip.
 230  */
 231 static void __init quirk_vt82c598_id(struct pci_dev *dev)
 232 {
 233         pci_write_config_byte(dev, 0xfc, 0);
 234         pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
 235 }
 236
 237 /*
 238  *  The main table of quirks.
 239  */
 240
 241 static struct pci_fixup pci_fixups[] __initdata = {
 242         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release },
 243         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release },
 244         /*
 245          * Its not totally clear which chipsets are the problematic ones
 246          * We know 82C586 and 82C596 variants are affected.
 247          */
 248         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_0,     quirk_isa_dma_hangs },
 249         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C596,       quirk_isa_dma_hangs },
 250         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs },
 251         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_868,           quirk_s3_64M },
 252         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_968,           quirk_s3_64M },
 253         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437,      quirk_triton },
 254         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437VX,    quirk_triton },
 255         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439,      quirk_triton },
 256         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439TX,    quirk_triton },
 257         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_natoma },
 258         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_0,  quirk_natoma },
 259         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_1,  quirk_natoma },
 260         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_0,  quirk_natoma },
 261         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_1,  quirk_natoma },
 262         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_2,  quirk_natoma },
 263         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_5597,          quirk_nopcipci },
 264         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_496,           quirk_nopcipci },
 265         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C597_0,     quirk_vt82c598_id },
 266         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_3,     quirk_vt82c586_acpi },
 267         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686_4,     quirk_vt82c686_acpi },
 268         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371AB_3,  quirk_piix4_acpi },
 269         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M7101,         quirk_ali7101_acpi },
 270         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_2,  quirk_piix3usb },
 271         { 0 }
 272 };
 273
 274
 275 static void pci_do_fixups(struct pci_dev *dev, int pass, struct pci_fixup *f)
 276 {
 277         while (f->pass) {
 278                 if (f->pass == pass &&
 279                     (f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
 280                     (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
 281 #ifdef DEBUG
 282                         printk("PCI: Calling quirk %p for %s\n", f->hook, dev->slot_name);
 283 #endif
 284                         f->hook(dev);
 285                 }
 286                 f++;
 287         }
 288 }
 289
 290 void pci_fixup_device(int pass, struct pci_dev *dev)
 291 {
 292         pci_do_fixups(dev, pass, pcibios_fixups);
 293         pci_do_fixups(dev, pass, pci_fixups);
 294 }