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Linux-2.4.0-test2
[davej-history.git] / drivers / pcmcia / i82365.c
blob578cbfcd0afcd3670a365a27f4a249fd49e2fb96
1 /*======================================================================
2
3 Device driver for Intel 82365 and compatible PC Card controllers.
4
5 i82365.c 1.265 1999/11/10 18:36:21
6
7 The contents of this file are subject to the Mozilla Public
8 License Version 1.1 (the "License"); you may not use this file
9 except in compliance with the License. You may obtain a copy of
10 the License at http://www.mozilla.org/MPL/
11
12 Software distributed under the License is distributed on an "AS
13 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
14 implied. See the License for the specific language governing
15 rights and limitations under the License.
16
17 The initial developer of the original code is David A. Hinds
18 <dhinds@pcmcia.sourceforge.org>. Portions created by David A. Hinds
19 are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
20
21 Alternatively, the contents of this file may be used under the
22 terms of the GNU Public License version 2 (the "GPL"), in which
23 case the provisions of the GPL are applicable instead of the
24 above. If you wish to allow the use of your version of this file
25 only under the terms of the GPL and not to allow others to use
26 your version of this file under the MPL, indicate your decision
27 by deleting the provisions above and replace them with the notice
28 and other provisions required by the GPL. If you do not delete
29 the provisions above, a recipient may use your version of this
30 file under either the MPL or the GPL.
31
32 ======================================================================*/
33
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/config.h>
37 #include <linux/types.h>
38 #include <linux/fcntl.h>
39 #include <linux/string.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/timer.h>
43 #include <linux/sched.h>
44 #include <linux/malloc.h>
45 #include <linux/pci.h>
46 #include <linux/ioport.h>
47 #include <linux/delay.h>
48 #include <linux/proc_fs.h>
49 #include <asm/irq.h>
50 #include <asm/io.h>
51 #include <asm/bitops.h>
52 #include <asm/segment.h>
53 #include <asm/system.h>
54
55 #include <pcmcia/version.h>
56 #include <pcmcia/cs_types.h>
57 #include <pcmcia/ss.h>
58 #include <pcmcia/cs.h>
59
60 /* ISA-bus controllers */
61 #include "i82365.h"
62 #include "cirrus.h"
63 #include "vg468.h"
64 #include "ricoh.h"
65 #include "o2micro.h"
66
67 /* PCI-bus controllers */
68 #include "old-yenta.h"
69 #include "smc34c90.h"
70 #include "topic.h"
71
72 #ifdef PCMCIA_DEBUG
73 static int pc_debug = PCMCIA_DEBUG;
74 MODULE_PARM(pc_debug, "i");
75 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
76 static const char *version =
77 "i82365.c 1.265 1999/11/10 18:36:21 (David Hinds)";
78 #else
79 #define DEBUG(n, args...) do { } while (0)
80 #endif
81
82 static void irq_count(int, void *, struct pt_regs *);
83 static inline int _check_irq(int irq, int flags)
84 {
85 if (request_irq(irq, irq_count, flags, "x", irq_count) != 0)
86 return -1;
87 free_irq(irq, irq_count);
88 return 0;
89 }
90
91 /*====================================================================*/
92
93 /* Parameters that can be set with 'insmod' */
94
95 #ifdef CONFIG_ISA
96 /* Default base address for i82365sl and other ISA chips */
97 static int i365_base = 0x3e0;
98 /* Should we probe at 0x3e2 for an extra ISA controller? */
99 static int extra_sockets = 0;
100 /* Specify a socket number to ignore */
101 static int ignore = -1;
102 /* Bit map or list of interrupts to choose from */
103 static u_int irq_mask = 0xffff;
104 static int irq_list[16] = { -1 };
105 /* The card status change interrupt -- 0 means autoselect */
106 static int cs_irq = 0;
107 #endif
108
109 /* Probe for safe interrupts? */
110 static int do_scan = 1;
111 /* Poll status interval -- 0 means default to interrupt */
112 static int poll_interval = 0;
113 /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
114 static int cycle_time = 120;
115
116 /* Cirrus options */
117 static int has_dma = -1;
118 static int has_led = -1;
119 static int has_ring = -1;
120 static int dynamic_mode = 0;
121 static int freq_bypass = -1;
122 static int setup_time = -1;
123 static int cmd_time = -1;
124 static int recov_time = -1;
125
126 #ifdef CONFIG_ISA
127 /* Vadem options */
128 static int async_clock = -1;
129 static int cable_mode = -1;
130 static int wakeup = 0;
131 #endif
132
133 #ifdef CONFIG_ISA
134 MODULE_PARM(i365_base, "i");
135 MODULE_PARM(ignore, "i");
136 MODULE_PARM(extra_sockets, "i");
137 MODULE_PARM(irq_mask, "i");
138 MODULE_PARM(irq_list, "1-16i");
139 MODULE_PARM(cs_irq, "i");
140 MODULE_PARM(async_clock, "i");
141 MODULE_PARM(cable_mode, "i");
142 MODULE_PARM(wakeup, "i");
143 #endif
144
145 MODULE_PARM(do_scan, "i");
146 MODULE_PARM(poll_interval, "i");
147 MODULE_PARM(cycle_time, "i");
148 MODULE_PARM(has_dma, "i");
149 MODULE_PARM(has_led, "i");
150 MODULE_PARM(has_ring, "i");
151 MODULE_PARM(dynamic_mode, "i");
152 MODULE_PARM(freq_bypass, "i");
153 MODULE_PARM(setup_time, "i");
154 MODULE_PARM(cmd_time, "i");
155 MODULE_PARM(recov_time, "i");
156
157 /*====================================================================*/
158
159 typedef struct cirrus_state_t {
160 u_char misc1, misc2;
161 u_char timer[6];
162 } cirrus_state_t;
163
164 typedef struct vg46x_state_t {
165 u_char ctl, ema;
166 } vg46x_state_t;
167
168 typedef struct socket_info_t {
169 u_short type, flags;
170 socket_cap_t cap;
171 ioaddr_t ioaddr;
172 u_short psock;
173 u_char cs_irq, intr;
174 void (*handler)(void *info, u_int events);
175 void *info;
176 #ifdef CONFIG_PROC_FS
177 struct proc_dir_entry *proc;
178 #endif
179 union {
180 cirrus_state_t cirrus;
181 vg46x_state_t vg46x;
182 } state;
183 } socket_info_t;
184
185 /* Where we keep track of our sockets... */
186 static int sockets = 0;
187 static socket_info_t socket[8] = {
188 { 0, }, /* ... */
189 };
190
191 /* Default ISA interrupt mask */
192 #define I365_MASK 0xdeb8 /* irq 15,14,12,11,10,9,7,5,4,3 */
193
194 #ifdef CONFIG_ISA
195 static int grab_irq;
196 static spinlock_t isa_lock = SPIN_LOCK_UNLOCKED;
197 #define ISA_LOCK(n, f) spin_lock_irqsave(&isa_lock, f)
198 #define ISA_UNLOCK(n, f) spin_unlock_irqrestore(&isa_lock, f)
199 #else
200 #define ISA_LOCK(n, f) do { } while (0)
201 #define ISA_UNLOCK(n, f) do { } while (0)
202 #endif
203
204 static struct timer_list poll_timer;
205
206 /*====================================================================*/
207
208 /* Default settings for PCI command configuration register */
209 #define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
210 PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
211
212 /* These definitions must match the pcic table! */
213 typedef enum pcic_id {
214 #ifdef CONFIG_ISA
215 IS_I82365A, IS_I82365B, IS_I82365DF,
216 IS_IBM, IS_RF5Cx96, IS_VLSI, IS_VG468, IS_VG469,
217 IS_PD6710, IS_PD672X, IS_VT83C469,
218 #endif
219 } pcic_id;
220
221 /* Flags for classifying groups of controllers */
222 #define IS_VADEM 0x0001
223 #define IS_CIRRUS 0x0002
224 #define IS_TI 0x0004
225 #define IS_O2MICRO 0x0008
226 #define IS_VIA 0x0010
227 #define IS_TOPIC 0x0020
228 #define IS_RICOH 0x0040
229 #define IS_UNKNOWN 0x0400
230 #define IS_VG_PWR 0x0800
231 #define IS_DF_PWR 0x1000
232 #define IS_PCI 0x2000
233 #define IS_ALIVE 0x8000
234
235 typedef struct pcic_t {
236 char *name;
237 u_short flags;
238 } pcic_t;
239
240 static pcic_t pcic[] = {
241 #ifdef CONFIG_ISA
242 { "Intel i82365sl A step", 0 },
243 { "Intel i82365sl B step", 0 },
244 { "Intel i82365sl DF", IS_DF_PWR },
245 { "IBM Clone", 0 },
246 { "Ricoh RF5C296/396", 0 },
247 { "VLSI 82C146", 0 },
248 { "Vadem VG-468", IS_VADEM },
249 { "Vadem VG-469", IS_VADEM|IS_VG_PWR },
250 { "Cirrus PD6710", IS_CIRRUS },
251 { "Cirrus PD672x", IS_CIRRUS },
252 { "VIA VT83C469", IS_CIRRUS|IS_VIA },
253 #endif
254 };
255
256 #define PCIC_COUNT (sizeof(pcic)/sizeof(pcic_t))
257
258 /*====================================================================*/
259
260 static u_char i365_get(u_short sock, u_short reg)
261 {
262 {
263 ioaddr_t port = socket[sock].ioaddr;
264 u_char val;
265 reg = I365_REG(socket[sock].psock, reg);
266 outb(reg, port); val = inb(port+1);
267 return val;
268 }
269 }
270
271 static void i365_set(u_short sock, u_short reg, u_char data)
272 {
273 {
274 ioaddr_t port = socket[sock].ioaddr;
275 u_char val = I365_REG(socket[sock].psock, reg);
276 outb(val, port); outb(data, port+1);
277 }
278 }
279
280 static void i365_bset(u_short sock, u_short reg, u_char mask)
281 {
282 u_char d = i365_get(sock, reg);
283 d |= mask;
284 i365_set(sock, reg, d);
285 }
286
287 static void i365_bclr(u_short sock, u_short reg, u_char mask)
288 {
289 u_char d = i365_get(sock, reg);
290 d &= ~mask;
291 i365_set(sock, reg, d);
292 }
293
294 static void i365_bflip(u_short sock, u_short reg, u_char mask, int b)
295 {
296 u_char d = i365_get(sock, reg);
297 if (b)
298 d |= mask;
299 else
300 d &= ~mask;
301 i365_set(sock, reg, d);
302 }
303
304 static u_short i365_get_pair(u_short sock, u_short reg)
305 {
306 u_short a, b;
307 a = i365_get(sock, reg);
308 b = i365_get(sock, reg+1);
309 return (a + (b<<8));
310 }
311
312 static void i365_set_pair(u_short sock, u_short reg, u_short data)
313 {
314 i365_set(sock, reg, data & 0xff);
315 i365_set(sock, reg+1, data >> 8);
316 }
317
318 /*======================================================================
319
320 Code to save and restore global state information for Cirrus
321 PD67xx controllers, and to set and report global configuration
322 options.
323
324 The VIA controllers also use these routines, as they are mostly
325 Cirrus lookalikes, without the timing registers.
326
327 ======================================================================*/
328
329 #define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
330
331 static void cirrus_get_state(u_short s)
332 {
333 int i;
334 cirrus_state_t *p = &socket[s].state.cirrus;
335 p->misc1 = i365_get(s, PD67_MISC_CTL_1);
336 p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
337 p->misc2 = i365_get(s, PD67_MISC_CTL_2);
338 for (i = 0; i < 6; i++)
339 p->timer[i] = i365_get(s, PD67_TIME_SETUP(0)+i);
340 }
341
342 static void cirrus_set_state(u_short s)
343 {
344 int i;
345 u_char misc;
346 cirrus_state_t *p = &socket[s].state.cirrus;
347
348 misc = i365_get(s, PD67_MISC_CTL_2);
349 i365_set(s, PD67_MISC_CTL_2, p->misc2);
350 if (misc & PD67_MC2_SUSPEND) mdelay(50);
351 misc = i365_get(s, PD67_MISC_CTL_1);
352 misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
353 i365_set(s, PD67_MISC_CTL_1, misc | p->misc1);
354 for (i = 0; i < 6; i++)
355 i365_set(s, PD67_TIME_SETUP(0)+i, p->timer[i]);
356 }
357
358 static u_int __init cirrus_set_opts(u_short s, char *buf)
359 {
360 socket_info_t *t = &socket[s];
361 cirrus_state_t *p = &socket[s].state.cirrus;
362 u_int mask = 0xffff;
363
364 if (has_ring == -1) has_ring = 1;
365 flip(p->misc2, PD67_MC2_IRQ15_RI, has_ring);
366 flip(p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
367 if (p->misc2 & PD67_MC2_IRQ15_RI)
368 strcat(buf, " [ring]");
369 if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
370 strcat(buf, " [dyn mode]");
371 if (p->misc1 & PD67_MC1_INPACK_ENA)
372 strcat(buf, " [inpack]");
373 if (!(t->flags & IS_PCI)) {
374 if (p->misc2 & PD67_MC2_IRQ15_RI)
375 mask &= ~0x8000;
376 if (has_led > 0) {
377 strcat(buf, " [led]");
378 mask &= ~0x1000;
379 }
380 if (has_dma > 0) {
381 strcat(buf, " [dma]");
382 mask &= ~0x0600;
383 flip(p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
384 if (p->misc2 & PD67_MC2_FREQ_BYPASS)
385 strcat(buf, " [freq bypass]");
386 }
387 }
388 if (!(t->flags & IS_VIA)) {
389 if (setup_time >= 0)
390 p->timer[0] = p->timer[3] = setup_time;
391 if (cmd_time > 0) {
392 p->timer[1] = cmd_time;
393 p->timer[4] = cmd_time*2+4;
394 }
395 if (p->timer[1] == 0) {
396 p->timer[1] = 6; p->timer[4] = 16;
397 if (p->timer[0] == 0)
398 p->timer[0] = p->timer[3] = 1;
399 }
400 if (recov_time >= 0)
401 p->timer[2] = p->timer[5] = recov_time;
402 buf += strlen(buf);
403 sprintf(buf, " [%d/%d/%d] [%d/%d/%d]", p->timer[0], p->timer[1],
404 p->timer[2], p->timer[3], p->timer[4], p->timer[5]);
405 }
406 return mask;
407 }
408
409 /*======================================================================
410
411 Code to save and restore global state information for Vadem VG468
412 and VG469 controllers, and to set and report global configuration
413 options.
414
415 ======================================================================*/
416
417 #ifdef CONFIG_ISA
418
419 static void vg46x_get_state(u_short s)
420 {
421 vg46x_state_t *p = &socket[s].state.vg46x;
422 p->ctl = i365_get(s, VG468_CTL);
423 if (socket[s].type == IS_VG469)
424 p->ema = i365_get(s, VG469_EXT_MODE);
425 }
426
427 static void vg46x_set_state(u_short s)
428 {
429 vg46x_state_t *p = &socket[s].state.vg46x;
430 i365_set(s, VG468_CTL, p->ctl);
431 if (socket[s].type == IS_VG469)
432 i365_set(s, VG469_EXT_MODE, p->ema);
433 }
434
435 static u_int __init vg46x_set_opts(u_short s, char *buf)
436 {
437 vg46x_state_t *p = &socket[s].state.vg46x;
438
439 flip(p->ctl, VG468_CTL_ASYNC, async_clock);
440 flip(p->ema, VG469_MODE_CABLE, cable_mode);
441 if (p->ctl & VG468_CTL_ASYNC)
442 strcat(buf, " [async]");
443 if (p->ctl & VG468_CTL_INPACK)
444 strcat(buf, " [inpack]");
445 if (socket[s].type == IS_VG469) {
446 u_char vsel = i365_get(s, VG469_VSELECT);
447 if (vsel & VG469_VSEL_EXT_STAT) {
448 strcat(buf, " [ext mode]");
449 if (vsel & VG469_VSEL_EXT_BUS)
450 strcat(buf, " [isa buf]");
451 }
452 if (p->ema & VG469_MODE_CABLE)
453 strcat(buf, " [cable]");
454 if (p->ema & VG469_MODE_COMPAT)
455 strcat(buf, " [c step]");
456 }
457 return 0xffff;
458 }
459
460 #endif
461
462
463 /*======================================================================
464
465 Generic routines to get and set controller options
466
467 ======================================================================*/
468
469 static void get_bridge_state(u_short s)
470 {
471 socket_info_t *t = &socket[s];
472 if (t->flags & IS_CIRRUS)
473 cirrus_get_state(s);
474 #ifdef CONFIG_ISA
475 else if (t->flags & IS_VADEM)
476 vg46x_get_state(s);
477 #endif
478 }
479
480 static void set_bridge_state(u_short s)
481 {
482 socket_info_t *t = &socket[s];
483 if (t->flags & IS_CIRRUS)
484 cirrus_set_state(s);
485 else {
486 i365_set(s, I365_GBLCTL, 0x00);
487 i365_set(s, I365_GENCTL, 0x00);
488 }
489 i365_bflip(s, I365_INTCTL, I365_INTR_ENA, t->intr);
490 #ifdef CONFIG_ISA
491 if (t->flags & IS_VADEM)
492 vg46x_set_state(s);
493 #endif
494 }
495
496 static u_int __init set_bridge_opts(u_short s, u_short ns)
497 {
498 u_short i;
499 u_int m = 0xffff;
500 char buf[128];
501
502 for (i = s; i < s+ns; i++) {
503 if (socket[i].flags & IS_ALIVE) {
504 printk(KERN_INFO " host opts [%d]: already alive!\n", i);
505 continue;
506 }
507 buf[0] = '\0';
508 get_bridge_state(i);
509 if (socket[i].flags & IS_CIRRUS)
510 m = cirrus_set_opts(i, buf);
511 #ifdef CONFIG_ISA
512 else if (socket[i].flags & IS_VADEM)
513 m = vg46x_set_opts(i, buf);
514 #endif
515 set_bridge_state(i);
516 printk(KERN_INFO " host opts [%d]:%s\n", i,
517 (*buf) ? buf : " none");
518 }
519 return m;
520 }
521
522 /*======================================================================
523
524 Interrupt testing code, for ISA and PCI interrupts
525
526 ======================================================================*/
527
528 static volatile u_int irq_hits;
529 static u_short irq_sock;
530
531 static void irq_count(int irq, void *dev, struct pt_regs *regs)
532 {
533 i365_get(irq_sock, I365_CSC);
534 irq_hits++;
535 DEBUG(2, "-> hit on irq %d\n", irq);
536 }
537
538 static u_int __init test_irq(u_short sock, int irq)
539 {
540 DEBUG(2, " testing ISA irq %d\n", irq);
541 if (request_irq(irq, irq_count, 0, "scan", irq_count) != 0)
542 return 1;
543 irq_hits = 0; irq_sock = sock;
544 __set_current_state(TASK_UNINTERRUPTIBLE);
545 schedule_timeout(HZ/100);
546 if (irq_hits) {
547 free_irq(irq, irq_count);
548 DEBUG(2, " spurious hit!\n");
549 return 1;
550 }
551
552 /* Generate one interrupt */
553 i365_set(sock, I365_CSCINT, I365_CSC_DETECT | (irq << 4));
554 i365_bset(sock, I365_GENCTL, I365_CTL_SW_IRQ);
555 udelay(1000);
556
557 free_irq(irq, irq_count);
558
559 /* mask all interrupts */
560 i365_set(sock, I365_CSCINT, 0);
561 DEBUG(2, " hits = %d\n", irq_hits);
562
563 return (irq_hits != 1);
564 }
565
566 #ifdef CONFIG_ISA
567
568 static u_int __init isa_scan(u_short sock, u_int mask0)
569 {
570 u_int mask1 = 0;
571 int i;
572
573 #ifdef __alpha__
574 #define PIC 0x4d0
575 /* Don't probe level-triggered interrupts -- reserved for PCI */
576 mask0 &= ~(inb(PIC) | (inb(PIC+1) << 8));
577 #endif
578
579 if (do_scan) {
580 set_bridge_state(sock);
581 i365_set(sock, I365_CSCINT, 0);
582 for (i = 0; i < 16; i++)
583 if ((mask0 & (1 << i)) && (test_irq(sock, i) == 0))
584 mask1 |= (1 << i);
585 for (i = 0; i < 16; i++)
586 if ((mask1 & (1 << i)) && (test_irq(sock, i) != 0))
587 mask1 ^= (1 << i);
588 }
589
590 printk(KERN_INFO " ISA irqs (");
591 if (mask1) {
592 printk("scanned");
593 } else {
594 /* Fallback: just find interrupts that aren't in use */
595 for (i = 0; i < 16; i++)
596 if ((mask0 & (1 << i)) && (_check_irq(i, 0) == 0))
597 mask1 |= (1 << i);
598 printk("default");
599 /* If scan failed, default to polled status */
600 if (!cs_irq && (poll_interval == 0)) poll_interval = HZ;
601 }
602 printk(") = ");
603
604 for (i = 0; i < 16; i++)
605 if (mask1 & (1<<i))
606 printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i);
607 if (mask1 == 0) printk("none!");
608
609 return mask1;
610 }
611
612 #endif /* CONFIG_ISA */
613
614 /*====================================================================*/
615
616 /* Time conversion functions */
617
618 static int to_cycles(int ns)
619 {
620 return ns/cycle_time;
621 }
622
623 static int to_ns(int cycles)
624 {
625 return cycle_time*cycles;
626 }
627
628 /*====================================================================*/
629
630 #ifdef CONFIG_ISA
631
632 static int __init identify(u_short port, u_short sock)
633 {
634 u_char val;
635 int type = -1;
636
637 /* Use the next free entry in the socket table */
638 socket[sockets].ioaddr = port;
639 socket[sockets].psock = sock;
640
641 /* Wake up a sleepy Cirrus controller */
642 if (wakeup) {
643 i365_bclr(sockets, PD67_MISC_CTL_2, PD67_MC2_SUSPEND);
644 /* Pause at least 50 ms */
645 mdelay(50);
646 }
647
648 if ((val = i365_get(sockets, I365_IDENT)) & 0x70)
649 return -1;
650 switch (val) {
651 case 0x82:
652 type = IS_I82365A; break;
653 case 0x83:
654 type = IS_I82365B; break;
655 case 0x84:
656 type = IS_I82365DF; break;
657 case 0x88: case 0x89: case 0x8a:
658 type = IS_IBM; break;
659 }
660
661 /* Check for Vadem VG-468 chips */
662 outb(0x0e, port);
663 outb(0x37, port);
664 i365_bset(sockets, VG468_MISC, VG468_MISC_VADEMREV);
665 val = i365_get(sockets, I365_IDENT);
666 if (val & I365_IDENT_VADEM) {
667 i365_bclr(sockets, VG468_MISC, VG468_MISC_VADEMREV);
668 type = ((val & 7) >= 4) ? IS_VG469 : IS_VG468;
669 }
670
671 /* Check for Ricoh chips */
672 val = i365_get(sockets, RF5C_CHIP_ID);
673 if ((val == RF5C_CHIP_RF5C296) || (val == RF5C_CHIP_RF5C396))
674 type = IS_RF5Cx96;
675
676 /* Check for Cirrus CL-PD67xx chips */
677 i365_set(sockets, PD67_CHIP_INFO, 0);
678 val = i365_get(sockets, PD67_CHIP_INFO);
679 if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
680 val = i365_get(sockets, PD67_CHIP_INFO);
681 if ((val & PD67_INFO_CHIP_ID) == 0) {
682 type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
683 i365_set(sockets, PD67_EXT_INDEX, 0xe5);
684 if (i365_get(sockets, PD67_EXT_INDEX) != 0xe5)
685 type = IS_VT83C469;
686 }
687 }
688 return type;
689 } /* identify */
690
691 #endif
692
693 /*======================================================================
694
695 See if a card is present, powered up, in IO mode, and already
696 bound to a (non PC Card) Linux driver. We leave these alone.
697
698 We make an exception for cards that seem to be serial devices.
699
700 ======================================================================*/
701
702 static int __init is_alive(u_short sock)
703 {
704 u_char stat;
705 u_short start, stop;
706
707 stat = i365_get(sock, I365_STATUS);
708 start = i365_get_pair(sock, I365_IO(0)+I365_W_START);
709 stop = i365_get_pair(sock, I365_IO(0)+I365_W_STOP);
710 if ((stat & I365_CS_DETECT) && (stat & I365_CS_POWERON) &&
711 (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD) &&
712 (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(0)) &&
713 (check_region(start, stop-start+1) != 0) &&
714 ((start & 0xfeef) != 0x02e8))
715 return 1;
716 else
717 return 0;
718 }
719
720 /*====================================================================*/
721
722 static void __init add_socket(u_short port, int psock, int type)
723 {
724 socket[sockets].ioaddr = port;
725 socket[sockets].psock = psock;
726 socket[sockets].type = type;
727 socket[sockets].flags = pcic[type].flags;
728 if (is_alive(sockets))
729 socket[sockets].flags |= IS_ALIVE;
730 sockets++;
731 }
732
733 static void __init add_pcic(int ns, int type)
734 {
735 u_int mask = 0, i, base;
736 int use_pci = 0, isa_irq = 0;
737 socket_info_t *t = &socket[sockets-ns];
738
739 base = sockets-ns;
740 if (t->ioaddr > 0) request_region(t->ioaddr, 2, "i82365");
741
742 if (base == 0) printk("\n");
743 printk(KERN_INFO " %s", pcic[type].name);
744 printk(" ISA-to-PCMCIA at port %#x ofs 0x%02x",
745 t->ioaddr, t->psock*0x40);
746 printk(", %d socket%s\n", ns, ((ns > 1) ? "s" : ""));
747
748 #ifdef CONFIG_ISA
749 /* Set host options, build basic interrupt mask */
750 if (irq_list[0] == -1)
751 mask = irq_mask;
752 else
753 for (i = mask = 0; i < 16; i++)
754 mask |= (1<<irq_list[i]);
755 #endif
756 mask &= I365_MASK & set_bridge_opts(base, ns);
757 #ifdef CONFIG_ISA
758 /* Scan for ISA interrupts */
759 mask = isa_scan(base, mask);
760 #else
761 printk(KERN_INFO " PCI card interrupts,");
762 #endif
763
764 #ifdef CONFIG_ISA
765 /* Poll if only two interrupts available */
766 if (!use_pci && !poll_interval) {
767 u_int tmp = (mask & 0xff20);
768 tmp = tmp & (tmp-1);
769 if ((tmp & (tmp-1)) == 0)
770 poll_interval = HZ;
771 }
772 /* Only try an ISA cs_irq if this is the first controller */
773 if (!use_pci && !grab_irq && (cs_irq || !poll_interval)) {
774 /* Avoid irq 12 unless it is explicitly requested */
775 u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12));
776 for (cs_irq = 15; cs_irq > 0; cs_irq--)
777 if ((cs_mask & (1 << cs_irq)) &&
778 (_check_irq(cs_irq, 0) == 0))
779 break;
780 if (cs_irq) {
781 grab_irq = 1;
782 isa_irq = cs_irq;
783 printk(" status change on irq %d\n", cs_irq);
784 }
785 }
786 #endif
787
788 if (!use_pci && !isa_irq) {
789 if (poll_interval == 0)
790 poll_interval = HZ;
791 printk(" polling interval = %d ms\n",
792 poll_interval * 1000 / HZ);
793
794 }
795
796 /* Update socket interrupt information, capabilities */
797 for (i = 0; i < ns; i++) {
798 t[i].cap.features |= SS_CAP_PCCARD;
799 t[i].cap.map_size = 0x1000;
800 t[i].cap.irq_mask = mask;
801 t[i].cs_irq = isa_irq;
802 }
803
804 } /* add_pcic */
805
806
807 /*====================================================================*/
808
809 #ifdef CONFIG_ISA
810
811 static void __init isa_probe(void)
812 {
813 int i, j, sock, k, ns, id;
814 ioaddr_t port;
815
816 if (check_region(i365_base, 2) != 0) {
817 if (sockets == 0)
818 printk("port conflict at %#x\n", i365_base);
819 return;
820 }
821
822 id = identify(i365_base, 0);
823 if ((id == IS_I82365DF) && (identify(i365_base, 1) != id)) {
824 for (i = 0; i < 4; i++) {
825 if (i == ignore) continue;
826 port = i365_base + ((i & 1) << 2) + ((i & 2) << 1);
827 sock = (i & 1) << 1;
828 if (identify(port, sock) == IS_I82365DF) {
829 add_socket(port, sock, IS_VLSI);
830 add_pcic(1, IS_VLSI);
831 }
832 }
833 } else {
834 for (i = 0; i < (extra_sockets ? 8 : 4); i += 2) {
835 port = i365_base + 2*(i>>2);
836 sock = (i & 3);
837 id = identify(port, sock);
838 if (id < 0) continue;
839
840 for (j = ns = 0; j < 2; j++) {
841 /* Does the socket exist? */
842 if ((ignore == i+j) || (identify(port, sock+j) < 0))
843 continue;
844 /* Check for bad socket decode */
845 for (k = 0; k <= sockets; k++)
846 i365_set(k, I365_MEM(0)+I365_W_OFF, k);
847 for (k = 0; k <= sockets; k++)
848 if (i365_get(k, I365_MEM(0)+I365_W_OFF) != k)
849 break;
850 if (k <= sockets) break;
851 add_socket(port, sock+j, id); ns++;
852 }
853 if (ns != 0) add_pcic(ns, id);
854 }
855 }
856 }
857
858 #endif
859
860 /*====================================================================*/
861
862 static void pcic_interrupt(int irq, void *dev,
863 struct pt_regs *regs)
864 {
865 int i, j, csc;
866 u_int events, active;
867 #ifdef CONFIG_ISA
868 u_long flags = 0;
869 #endif
870
871 DEBUG(4, "i82365: pcic_interrupt(%d)\n", irq);
872
873 for (j = 0; j < 20; j++) {
874 active = 0;
875 for (i = 0; i < sockets; i++) {
876 if ((socket[i].cs_irq != irq) &&
877 (socket[i].cap.pci_irq != irq))
878 continue;
879 ISA_LOCK(i, flags);
880 csc = i365_get(i, I365_CSC);
881 if ((csc == 0) || (!socket[i].handler) ||
882 (i365_get(i, I365_IDENT) & 0x70)) {
883 ISA_UNLOCK(i, flags);
884 continue;
885 }
886 events = (csc & I365_CSC_DETECT) ? SS_DETECT : 0;
887 if (i365_get(i, I365_INTCTL) & I365_PC_IOCARD)
888 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
889 else {
890 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
891 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
892 events |= (csc & I365_CSC_READY) ? SS_READY : 0;
893 }
894 ISA_UNLOCK(i, flags);
895 DEBUG(2, "i82365: socket %d event 0x%02x\n", i, events);
896 if (events)
897 socket[i].handler(socket[i].info, events);
898 active |= events;
899 }
900 if (!active) break;
901 }
902 if (j == 20)
903 printk(KERN_NOTICE "i82365: infinite loop in interrupt handler\n");
904
905 DEBUG(4, "i82365: interrupt done\n");
906 } /* pcic_interrupt */
907
908 static void pcic_interrupt_wrapper(u_long data)
909 {
910 pcic_interrupt(0, NULL, NULL);
911 poll_timer.expires = jiffies + poll_interval;
912 add_timer(&poll_timer);
913 }
914
915 /*====================================================================*/
916
917 static int pcic_register_callback(unsigned int sock, void (*handler)(void *, unsigned int), void * info)
918 {
919 socket[sock].handler = handler;
920 socket[sock].info = info;
921 if (handler == NULL) {
922 MOD_DEC_USE_COUNT;
923 } else {
924 MOD_INC_USE_COUNT;
925 }
926 return 0;
927 } /* pcic_register_callback */
928
929 /*====================================================================*/
930
931 static int pcic_inquire_socket(unsigned int sock, socket_cap_t *cap)
932 {
933 *cap = socket[sock].cap;
934 return 0;
935 } /* pcic_inquire_socket */
936
937 /*====================================================================*/
938
939 static int i365_get_status(u_short sock, u_int *value)
940 {
941 u_int status;
942
943 status = i365_get(sock, I365_STATUS);
944 *value = ((status & I365_CS_DETECT) == I365_CS_DETECT)
945 ? SS_DETECT : 0;
946 if (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD)
947 *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
948 else {
949 *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
950 *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
951 }
952 *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
953 *value |= (status & I365_CS_READY) ? SS_READY : 0;
954 *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
955
956 #ifdef CONFIG_ISA
957 if (socket[sock].type == IS_VG469) {
958 status = i365_get(sock, VG469_VSENSE);
959 if (socket[sock].psock & 1) {
960 *value |= (status & VG469_VSENSE_B_VS1) ? 0 : SS_3VCARD;
961 *value |= (status & VG469_VSENSE_B_VS2) ? 0 : SS_XVCARD;
962 } else {
963 *value |= (status & VG469_VSENSE_A_VS1) ? 0 : SS_3VCARD;
964 *value |= (status & VG469_VSENSE_A_VS2) ? 0 : SS_XVCARD;
965 }
966 }
967 #endif
968
969 DEBUG(1, "i82365: GetStatus(%d) = %#4.4x\n", sock, *value);
970 return 0;
971 } /* i365_get_status */
972
973 /*====================================================================*/
974
975 static int i365_get_socket(u_short sock, socket_state_t *state)
976 {
977 socket_info_t *t = &socket[sock];
978 u_char reg, vcc, vpp;
979
980 reg = i365_get(sock, I365_POWER);
981 state->flags = (reg & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
982 state->flags |= (reg & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
983 vcc = reg & I365_VCC_MASK; vpp = reg & I365_VPP1_MASK;
984 state->Vcc = state->Vpp = 0;
985 if (t->flags & IS_CIRRUS) {
986 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) {
987 if (reg & I365_VCC_5V) state->Vcc = 33;
988 if (vpp == I365_VPP1_5V) state->Vpp = 33;
989 } else {
990 if (reg & I365_VCC_5V) state->Vcc = 50;
991 if (vpp == I365_VPP1_5V) state->Vpp = 50;
992 }
993 if (vpp == I365_VPP1_12V) state->Vpp = 120;
994 } else if (t->flags & IS_VG_PWR) {
995 if (i365_get(sock, VG469_VSELECT) & VG469_VSEL_VCC) {
996 if (reg & I365_VCC_5V) state->Vcc = 33;
997 if (vpp == I365_VPP1_5V) state->Vpp = 33;
998 } else {
999 if (reg & I365_VCC_5V) state->Vcc = 50;
1000 if (vpp == I365_VPP1_5V) state->Vpp = 50;
1001 }
1002 if (vpp == I365_VPP1_12V) state->Vpp = 120;
1003 } else if (t->flags & IS_DF_PWR) {
1004 if (vcc == I365_VCC_3V) state->Vcc = 33;
1005 if (vcc == I365_VCC_5V) state->Vcc = 50;
1006 if (vpp == I365_VPP1_5V) state->Vpp = 50;
1007 if (vpp == I365_VPP1_12V) state->Vpp = 120;
1008 } else {
1009 if (reg & I365_VCC_5V) {
1010 state->Vcc = 50;
1011 if (vpp == I365_VPP1_5V) state->Vpp = 50;
1012 if (vpp == I365_VPP1_12V) state->Vpp = 120;
1013 }
1014 }
1015
1016 /* IO card, RESET flags, IO interrupt */
1017 reg = i365_get(sock, I365_INTCTL);
1018 state->flags |= (reg & I365_PC_RESET) ? 0 : SS_RESET;
1019 if (reg & I365_PC_IOCARD) state->flags |= SS_IOCARD;
1020 state->io_irq = reg & I365_IRQ_MASK;
1021
1022 /* speaker control */
1023 if (t->flags & IS_CIRRUS) {
1024 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_SPKR_ENA)
1025 state->flags |= SS_SPKR_ENA;
1026 }
1027
1028 /* Card status change mask */
1029 reg = i365_get(sock, I365_CSCINT);
1030 state->csc_mask = (reg & I365_CSC_DETECT) ? SS_DETECT : 0;
1031 if (state->flags & SS_IOCARD)
1032 state->csc_mask |= (reg & I365_CSC_STSCHG) ? SS_STSCHG : 0;
1033 else {
1034 state->csc_mask |= (reg & I365_CSC_BVD1) ? SS_BATDEAD : 0;
1035 state->csc_mask |= (reg & I365_CSC_BVD2) ? SS_BATWARN : 0;
1036 state->csc_mask |= (reg & I365_CSC_READY) ? SS_READY : 0;
1037 }
1038
1039 DEBUG(1, "i82365: GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
1040 "io_irq %d, csc_mask %#2.2x\n", sock, state->flags,
1041 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
1042 return 0;
1043 } /* i365_get_socket */
1044
1045 /*====================================================================*/
1046
1047 static int i365_set_socket(u_short sock, socket_state_t *state)
1048 {
1049 socket_info_t *t = &socket[sock];
1050 u_char reg;
1051
1052 DEBUG(1, "i82365: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
1053 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
1054 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
1055
1056 /* First set global controller options */
1057 set_bridge_state(sock);
1058
1059 /* IO card, RESET flag, IO interrupt */
1060 reg = t->intr;
1061 if (state->io_irq != t->cap.pci_irq) reg |= state->io_irq;
1062 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
1063 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
1064 i365_set(sock, I365_INTCTL, reg);
1065
1066 reg = I365_PWR_NORESET;
1067 if (state->flags & SS_PWR_AUTO) reg |= I365_PWR_AUTO;
1068 if (state->flags & SS_OUTPUT_ENA) reg |= I365_PWR_OUT;
1069
1070 if (t->flags & IS_CIRRUS) {
1071 if (state->Vpp != 0) {
1072 if (state->Vpp == 120)
1073 reg |= I365_VPP1_12V;
1074 else if (state->Vpp == state->Vcc)
1075 reg |= I365_VPP1_5V;
1076 else return -EINVAL;
1077 }
1078 if (state->Vcc != 0) {
1079 reg |= I365_VCC_5V;
1080 if (state->Vcc == 33)
1081 i365_bset(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
1082 else if (state->Vcc == 50)
1083 i365_bclr(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
1084 else return -EINVAL;
1085 }
1086 } else if (t->flags & IS_VG_PWR) {
1087 if (state->Vpp != 0) {
1088 if (state->Vpp == 120)
1089 reg |= I365_VPP1_12V;
1090 else if (state->Vpp == state->Vcc)
1091 reg |= I365_VPP1_5V;
1092 else return -EINVAL;
1093 }
1094 if (state->Vcc != 0) {
1095 reg |= I365_VCC_5V;
1096 if (state->Vcc == 33)
1097 i365_bset(sock, VG469_VSELECT, VG469_VSEL_VCC);
1098 else if (state->Vcc == 50)
1099 i365_bclr(sock, VG469_VSELECT, VG469_VSEL_VCC);
1100 else return -EINVAL;
1101 }
1102 } else if (t->flags & IS_DF_PWR) {
1103 switch (state->Vcc) {
1104 case 0: break;
1105 case 33: reg |= I365_VCC_3V; break;
1106 case 50: reg |= I365_VCC_5V; break;
1107 default: return -EINVAL;
1108 }
1109 switch (state->Vpp) {
1110 case 0: break;
1111 case 50: reg |= I365_VPP1_5V; break;
1112 case 120: reg |= I365_VPP1_12V; break;
1113 default: return -EINVAL;
1114 }
1115 } else {
1116 switch (state->Vcc) {
1117 case 0: break;
1118 case 50: reg |= I365_VCC_5V; break;
1119 default: return -EINVAL;
1120 }
1121 switch (state->Vpp) {
1122 case 0: break;
1123 case 50: reg |= I365_VPP1_5V | I365_VPP2_5V; break;
1124 case 120: reg |= I365_VPP1_12V | I365_VPP2_12V; break;
1125 default: return -EINVAL;
1126 }
1127 }
1128
1129 if (reg != i365_get(sock, I365_POWER))
1130 i365_set(sock, I365_POWER, reg);
1131
1132 /* Chipset-specific functions */
1133 if (t->flags & IS_CIRRUS) {
1134 /* Speaker control */
1135 i365_bflip(sock, PD67_MISC_CTL_1, PD67_MC1_SPKR_ENA,
1136 state->flags & SS_SPKR_ENA);
1137 }
1138
1139 /* Card status change interrupt mask */
1140 reg = t->cs_irq << 4;
1141 if (state->csc_mask & SS_DETECT) reg |= I365_CSC_DETECT;
1142 if (state->flags & SS_IOCARD) {
1143 if (state->csc_mask & SS_STSCHG) reg |= I365_CSC_STSCHG;
1144 } else {
1145 if (state->csc_mask & SS_BATDEAD) reg |= I365_CSC_BVD1;
1146 if (state->csc_mask & SS_BATWARN) reg |= I365_CSC_BVD2;
1147 if (state->csc_mask & SS_READY) reg |= I365_CSC_READY;
1148 }
1149 i365_set(sock, I365_CSCINT, reg);
1150 i365_get(sock, I365_CSC);
1151
1152 return 0;
1153 } /* i365_set_socket */
1154
1155 /*====================================================================*/
1156
1157 static int i365_get_io_map(u_short sock, struct pccard_io_map *io)
1158 {
1159 u_char map, ioctl, addr;
1160
1161 map = io->map;
1162 if (map > 1) return -EINVAL;
1163 io->start = i365_get_pair(sock, I365_IO(map)+I365_W_START);
1164 io->stop = i365_get_pair(sock, I365_IO(map)+I365_W_STOP);
1165 ioctl = i365_get(sock, I365_IOCTL);
1166 addr = i365_get(sock, I365_ADDRWIN);
1167 io->speed = to_ns(ioctl & I365_IOCTL_WAIT(map)) ? 1 : 0;
1168 io->flags = (addr & I365_ENA_IO(map)) ? MAP_ACTIVE : 0;
1169 io->flags |= (ioctl & I365_IOCTL_0WS(map)) ? MAP_0WS : 0;
1170 io->flags |= (ioctl & I365_IOCTL_16BIT(map)) ? MAP_16BIT : 0;
1171 io->flags |= (ioctl & I365_IOCTL_IOCS16(map)) ? MAP_AUTOSZ : 0;
1172 DEBUG(1, "i82365: GetIOMap(%d, %d) = %#2.2x, %d ns, "
1173 "%#4.4x-%#4.4x\n", sock, map, io->flags, io->speed,
1174 io->start, io->stop);
1175 return 0;
1176 } /* i365_get_io_map */
1177
1178 /*====================================================================*/
1179
1180 static int i365_set_io_map(u_short sock, struct pccard_io_map *io)
1181 {
1182 u_char map, ioctl;
1183
1184 DEBUG(1, "i82365: SetIOMap(%d, %d, %#2.2x, %d ns, "
1185 "%#4.4x-%#4.4x)\n", sock, io->map, io->flags,
1186 io->speed, io->start, io->stop);
1187 map = io->map;
1188 if ((map > 1) || (io->start > 0xffff) || (io->stop > 0xffff) ||
1189 (io->stop < io->start)) return -EINVAL;
1190 /* Turn off the window before changing anything */
1191 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(map))
1192 i365_bclr(sock, I365_ADDRWIN, I365_ENA_IO(map));
1193 i365_set_pair(sock, I365_IO(map)+I365_W_START, io->start);
1194 i365_set_pair(sock, I365_IO(map)+I365_W_STOP, io->stop);
1195 ioctl = i365_get(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map);
1196 if (io->speed) ioctl |= I365_IOCTL_WAIT(map);
1197 if (io->flags & MAP_0WS) ioctl |= I365_IOCTL_0WS(map);
1198 if (io->flags & MAP_16BIT) ioctl |= I365_IOCTL_16BIT(map);
1199 if (io->flags & MAP_AUTOSZ) ioctl |= I365_IOCTL_IOCS16(map);
1200 i365_set(sock, I365_IOCTL, ioctl);
1201 /* Turn on the window if necessary */
1202 if (io->flags & MAP_ACTIVE)
1203 i365_bset(sock, I365_ADDRWIN, I365_ENA_IO(map));
1204 return 0;
1205 } /* i365_set_io_map */
1206
1207 /*====================================================================*/
1208
1209 static int i365_get_mem_map(u_short sock, struct pccard_mem_map *mem)
1210 {
1211 u_short base, i;
1212 u_char map, addr;
1213
1214 map = mem->map;
1215 if (map > 4) return -EINVAL;
1216 addr = i365_get(sock, I365_ADDRWIN);
1217 mem->flags = (addr & I365_ENA_MEM(map)) ? MAP_ACTIVE : 0;
1218 base = I365_MEM(map);
1219
1220 i = i365_get_pair(sock, base+I365_W_START);
1221 mem->flags |= (i & I365_MEM_16BIT) ? MAP_16BIT : 0;
1222 mem->flags |= (i & I365_MEM_0WS) ? MAP_0WS : 0;
1223 mem->sys_start += ((u_long)(i & 0x0fff) << 12);
1224
1225 i = i365_get_pair(sock, base+I365_W_STOP);
1226 mem->speed = (i & I365_MEM_WS0) ? 1 : 0;
1227 mem->speed += (i & I365_MEM_WS1) ? 2 : 0;
1228 mem->speed = to_ns(mem->speed);
1229 mem->sys_stop = ((u_long)(i & 0x0fff) << 12) + 0x0fff;
1230
1231 i = i365_get_pair(sock, base+I365_W_OFF);
1232 mem->flags |= (i & I365_MEM_WRPROT) ? MAP_WRPROT : 0;
1233 mem->flags |= (i & I365_MEM_REG) ? MAP_ATTRIB : 0;
1234 mem->card_start = ((u_int)(i & 0x3fff) << 12) + mem->sys_start;
1235 mem->card_start &= 0x3ffffff;
1236
1237 DEBUG(1, "i82365: GetMemMap(%d, %d) = %#2.2x, %d ns, %#5.5lx-%#5."
1238 "5lx, %#5.5x\n", sock, mem->map, mem->flags, mem->speed,
1239 mem->sys_start, mem->sys_stop, mem->card_start);
1240 return 0;
1241 } /* i365_get_mem_map */
1242
1243 /*====================================================================*/
1244
1245 static int i365_set_mem_map(u_short sock, struct pccard_mem_map *mem)
1246 {
1247 u_short base, i;
1248 u_char map;
1249
1250 DEBUG(1, "i82365: SetMemMap(%d, %d, %#2.2x, %d ns, %#5.5lx-%#5.5"
1251 "lx, %#5.5x)\n", sock, mem->map, mem->flags, mem->speed,
1252 mem->sys_start, mem->sys_stop, mem->card_start);
1253
1254 map = mem->map;
1255 if ((map > 4) || (mem->card_start > 0x3ffffff) ||
1256 (mem->sys_start > mem->sys_stop) || (mem->speed > 1000))
1257 return -EINVAL;
1258 if (!(socket[sock].flags & IS_PCI) &&
1259 ((mem->sys_start > 0xffffff) || (mem->sys_stop > 0xffffff)))
1260 return -EINVAL;
1261
1262 /* Turn off the window before changing anything */
1263 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
1264 i365_bclr(sock, I365_ADDRWIN, I365_ENA_MEM(map));
1265
1266 base = I365_MEM(map);
1267 i = (mem->sys_start >> 12) & 0x0fff;
1268 if (mem->flags & MAP_16BIT) i |= I365_MEM_16BIT;
1269 if (mem->flags & MAP_0WS) i |= I365_MEM_0WS;
1270 i365_set_pair(sock, base+I365_W_START, i);
1271
1272 i = (mem->sys_stop >> 12) & 0x0fff;
1273 switch (to_cycles(mem->speed)) {
1274 case 0: break;
1275 case 1: i |= I365_MEM_WS0; break;
1276 case 2: i |= I365_MEM_WS1; break;
1277 default: i |= I365_MEM_WS1 | I365_MEM_WS0; break;
1278 }
1279 i365_set_pair(sock, base+I365_W_STOP, i);
1280
1281 i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
1282 if (mem->flags & MAP_WRPROT) i |= I365_MEM_WRPROT;
1283 if (mem->flags & MAP_ATTRIB) i |= I365_MEM_REG;
1284 i365_set_pair(sock, base+I365_W_OFF, i);
1285
1286 /* Turn on the window if necessary */
1287 if (mem->flags & MAP_ACTIVE)
1288 i365_bset(sock, I365_ADDRWIN, I365_ENA_MEM(map));
1289 return 0;
1290 } /* i365_set_mem_map */
1291
1292 /*======================================================================
1293
1294 Routines for accessing socket information and register dumps via
1295 /proc/bus/pccard/...
1296
1297 ======================================================================*/
1298
1299 #ifdef CONFIG_PROC_FS
1300
1301 static int proc_read_info(char *buf, char **start, off_t pos,
1302 int count, int *eof, void *data)
1303 {
1304 socket_info_t *s = data;
1305 char *p = buf;
1306 p += sprintf(p, "type: %s\npsock: %d\n",
1307 pcic[s->type].name, s->psock);
1308 return (p - buf);
1309 }
1310
1311 static int proc_read_exca(char *buf, char **start, off_t pos,
1312 int count, int *eof, void *data)
1313 {
1314 u_short sock = (socket_info_t *)data - socket;
1315 char *p = buf;
1316 int i, top;
1317
1318 #ifdef CONFIG_ISA
1319 u_long flags = 0;
1320 #endif
1321 ISA_LOCK(sock, flags);
1322 top = 0x40;
1323 for (i = 0; i < top; i += 4) {
1324 if (i == 0x50) {
1325 p += sprintf(p, "\n");
1326 i = 0x100;
1327 }
1328 p += sprintf(p, "%02x %02x %02x %02x%s",
1329 i365_get(sock,i), i365_get(sock,i+1),
1330 i365_get(sock,i+2), i365_get(sock,i+3),
1331 ((i % 16) == 12) ? "\n" : " ");
1332 }
1333 ISA_UNLOCK(sock, flags);
1334 return (p - buf);
1335 }
1336
1337 static void pcic_proc_setup(unsigned int sock, struct proc_dir_entry *base)
1338 {
1339 socket_info_t *s = &socket[sock];
1340
1341 if (s->flags & IS_ALIVE)
1342 return;
1343
1344 create_proc_read_entry("info", 0, base, proc_read_info, s);
1345 create_proc_read_entry("exca", 0, base, proc_read_exca, s);
1346 s->proc = base;
1347 }
1348
1349 static void pcic_proc_remove(u_short sock)
1350 {
1351 struct proc_dir_entry *base = socket[sock].proc;
1352 if (base == NULL) return;
1353 remove_proc_entry("info", base);
1354 remove_proc_entry("exca", base);
1355 }
1356
1357 #else
1358
1359 #define pcic_proc_setup NULL
1360
1361 #endif /* CONFIG_PROC_FS */
1362
1363 /*====================================================================*/
1364
1365 /*
1366 * The locking is rather broken. Why do we only lock for ISA, not for
1367 * all other cases? If there are reasons to lock, we should lock. Not
1368 * this silly conditional.
1369 *
1370 * Plan: make it bug-for-bug compatible with the old stuff, and clean
1371 * it up when the infrastructure is done.
1372 */
1373 #ifdef CONFIG_ISA
1374 #define LOCKED(x) do { \
1375 int retval; \
1376 unsigned long flags; \
1377 spin_lock_irqsave(&isa_lock, flags); \
1378 retval = x; \
1379 spin_unlock_irqrestore(&isa_lock, flags); \
1380 return retval; \
1381 } while (0)
1382 #else
1383 #define LOCKED(x) return x
1384 #endif
1385
1386
1387 static int pcic_get_status(unsigned int sock, u_int *value)
1388 {
1389 if (socket[sock].flags & IS_ALIVE) {
1390 *value = 0;
1391 return -EINVAL;
1392 }
1393
1394 LOCKED(i365_get_status(sock, value));
1395 }
1396
1397 static int pcic_get_socket(unsigned int sock, socket_state_t *state)
1398 {
1399 if (socket[sock].flags & IS_ALIVE)
1400 return -EINVAL;
1401
1402 LOCKED(i365_get_socket(sock, state));
1403 }
1404
1405 static int pcic_set_socket(unsigned int sock, socket_state_t *state)
1406 {
1407 if (socket[sock].flags & IS_ALIVE)
1408 return -EINVAL;
1409
1410 LOCKED(i365_set_socket(sock, state));
1411 }
1412
1413 static int pcic_get_io_map(unsigned int sock, struct pccard_io_map *io)
1414 {
1415 if (socket[sock].flags & IS_ALIVE)
1416 return -EINVAL;
1417
1418 LOCKED(i365_get_io_map(sock, io));
1419 }
1420
1421 static int pcic_set_io_map(unsigned int sock, struct pccard_io_map *io)
1422 {
1423 if (socket[sock].flags & IS_ALIVE)
1424 return -EINVAL;
1425
1426 LOCKED(i365_set_io_map(sock, io));
1427 }
1428
1429 static int pcic_get_mem_map(unsigned int sock, struct pccard_mem_map *mem)
1430 {
1431 if (socket[sock].flags & IS_ALIVE)
1432 return -EINVAL;
1433
1434 LOCKED(i365_get_mem_map(sock, mem));
1435 }
1436
1437 static int pcic_set_mem_map(unsigned int sock, struct pccard_mem_map *mem)
1438 {
1439 if (socket[sock].flags & IS_ALIVE)
1440 return -EINVAL;
1441
1442 LOCKED(i365_set_mem_map(sock, mem));
1443 }
1444
1445 static int pcic_init(unsigned int s)
1446 {
1447 int i;
1448 pccard_io_map io = { 0, 0, 0, 0, 1 };
1449 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1450
1451 mem.sys_stop = 0x1000;
1452 pcic_set_socket(s, &dead_socket);
1453 for (i = 0; i < 2; i++) {
1454 io.map = i;
1455 pcic_set_io_map(s, &io);
1456 }
1457 for (i = 0; i < 5; i++) {
1458 mem.map = i;
1459 pcic_set_mem_map(s, &mem);
1460 }
1461 return 0;
1462 }
1463
1464 static int pcic_suspend(unsigned int sock)
1465 {
1466 return pcic_set_socket(sock, &dead_socket);
1467 }
1468
1469 static struct pccard_operations pcic_operations = {
1470 pcic_init,
1471 pcic_suspend,
1472 pcic_register_callback,
1473 pcic_inquire_socket,
1474 pcic_get_status,
1475 pcic_get_socket,
1476 pcic_set_socket,
1477 pcic_get_io_map,
1478 pcic_set_io_map,
1479 pcic_get_mem_map,
1480 pcic_set_mem_map,
1481 pcic_proc_setup
1482 };
1483
1484 /*====================================================================*/
1485
1486 static int __init init_i82365(void)
1487 {
1488 servinfo_t serv;
1489 pcmcia_get_card_services_info(&serv);
1490 if (serv.Revision != CS_RELEASE_CODE) {
1491 printk(KERN_NOTICE "i82365: Card Services release "
1492 "does not match!\n");
1493 return -1;
1494 }
1495 DEBUG(0, "%s\n", version);
1496 printk(KERN_INFO "Intel PCIC probe: ");
1497 sockets = 0;
1498
1499 #ifdef CONFIG_ISA
1500 isa_probe();
1501 #endif
1502
1503 if (sockets == 0) {
1504 printk("not found.\n");
1505 return -ENODEV;
1506 }
1507
1508 /* Set up interrupt handler(s) */
1509 #ifdef CONFIG_ISA
1510 if (grab_irq != 0)
1511 request_irq(cs_irq, pcic_interrupt, 0, "i82365", pcic_interrupt);
1512 #endif
1513
1514 if (register_ss_entry(sockets, &pcic_operations) != 0)
1515 printk(KERN_NOTICE "i82365: register_ss_entry() failed\n");
1516
1517 /* Finally, schedule a polling interrupt */
1518 if (poll_interval != 0) {
1519 poll_timer.function = pcic_interrupt_wrapper;
1520 poll_timer.data = 0;
1521 init_timer(&poll_timer);
1522 poll_timer.expires = jiffies + poll_interval;
1523 add_timer(&poll_timer);
1524 }
1525
1526 return 0;
1527
1528 } /* init_i82365 */
1529
1530 static void __exit exit_i82365(void)
1531 {
1532 int i;
1533 #ifdef CONFIG_PROC_FS
1534 for (i = 0; i < sockets; i++) pcic_proc_remove(i);
1535 #endif
1536 unregister_ss_entry(&pcic_operations);
1537 if (poll_interval != 0)
1538 del_timer(&poll_timer);
1539 #ifdef CONFIG_ISA
1540 if (grab_irq != 0)
1541 free_irq(cs_irq, pcic_interrupt);
1542 #endif
1543 for (i = 0; i < sockets; i++) {
1544 /* Turn off all interrupt sources! */
1545 i365_set(i, I365_CSCINT, 0);
1546 release_region(socket[i].ioaddr, 2);
1547 }
1548 } /* exit_i82365 */
1549
1550 module_init(init_i82365);
1551 module_exit(exit_i82365);
1552
1553 /*====================================================================*/
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