include/asm-ppc/dma.h

   1 /* $Id: dma.h,v 1.3 1997/03/16 06:20:39 cort Exp $
   2  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   3  * Written by Hennus Bergman, 1992.
   4  * High DMA channel support & info by Hannu Savolainen
   5  * and John Boyd, Nov. 1992.
   6  * Changes for ppc sound by Christoph Nadig
   7  */
   8
   9 #ifdef __KERNEL__
  10
  11 #include <linux/config.h>
  12 #include <asm/io.h>
  13 #include <linux/spinlock.h>
  14 #include <asm/system.h>
  15
  16 /*
  17  * Note: Adapted for PowerPC by Gary Thomas
  18  * Modified by Cort Dougan <cort@cs.nmt.edu>
  19  *
  20  * None of this really applies for Power Macintoshes.  There is
  21  * basically just enough here to get kernel/dma.c to compile.
  22  *
  23  * There may be some comments or restrictions made here which are
  24  * not valid for the PReP platform.  Take what you read
  25  * with a grain of salt.
  26  */
  27
  28
  29 #ifndef _ASM_DMA_H
  30 #define _ASM_DMA_H
  31
  32 #ifndef MAX_DMA_CHANNELS
  33 #define MAX_DMA_CHANNELS        8
  34 #endif
  35
  36 /* The maximum address that we can perform a DMA transfer to on this platform */
  37 /* Doesn't really apply... */
  38 #define MAX_DMA_ADDRESS      0xFFFFFFFF
  39
  40 /* in arch/ppc/kernel/setup.c -- Cort */
  41 extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
  42 extern unsigned long ISA_DMA_THRESHOLD;
  43
  44
  45 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  46 #define dma_outb        outb_p
  47 #else
  48 #define dma_outb        outb
  49 #endif
  50
  51 #define dma_inb         inb
  52
  53 /*
  54  * NOTES about DMA transfers:
  55  *
  56  *  controller 1: channels 0-3, byte operations, ports 00-1F
  57  *  controller 2: channels 4-7, word operations, ports C0-DF
  58  *
  59  *  - ALL registers are 8 bits only, regardless of transfer size
  60  *  - channel 4 is not used - cascades 1 into 2.
  61  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  62  *  - channels 5-7 are word - addresses/counts are for physical words
  63  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  64  *  - transfer count loaded to registers is 1 less than actual count
  65  *  - controller 2 offsets are all even (2x offsets for controller 1)
  66  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  67  *  - page registers for 0-3 use bit 0, represent 64K pages
  68  *
  69  * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
  70  * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
  71  * Note that addresses loaded into registers must be _physical_ addresses,
  72  * not logical addresses (which may differ if paging is active).
  73  *
  74  *  Address mapping for channels 0-3:
  75  *
  76  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  77  *    |  ...  |   |  ... |   |  ... |
  78  *    |  ...  |   |  ... |   |  ... |
  79  *    |  ...  |   |  ... |   |  ... |
  80  *   P7  ...  P0  A7 ... A0  A7 ... A0
  81  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  82  *
  83  *  Address mapping for channels 5-7:
  84  *
  85  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  86  *    |  ...  |   \   \   ... \  \  \  ... \  \
  87  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  88  *    |  ...  |     \   \   ... \  \  \  ... \
  89  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  90  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  91  *
  92  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  93  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  94  * the hardware level, so odd-byte transfers aren't possible).
  95  *
  96  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  97  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  98  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  99  *
 100  */
 101
 102 /* used in nasty hack for sound - see prep_setup_arch() -- Cort */
 103 extern long ppc_cs4232_dma, ppc_cs4232_dma2;
 104 #if defined(CONFIG_CS4232)
 105 #if defined(CONFIG_PREP) || defined(CONFIG_ALL_PPC)
 106 #define SND_DMA1 ppc_cs4232_dma
 107 #define SND_DMA2 ppc_cs4232_dma2
 108 #else /* !CONFIG_PREP && !CONFIG_ALL_PPC */
 109 #define SND_DMA1 -1
 110 #define SND_DMA2 -1
 111 #endif /* !CONFIG_PREP */
 112 #elif defined(CONFIG_MSS)
 113 #define SND_DMA1 CONFIG_MSS_DMA
 114 #define SND_DMA2 CONFIG_MSS_DMA2
 115 #else
 116 #define SND_DMA1 -1
 117 #define SND_DMA2 -1
 118 #endif
 119
 120 /* 8237 DMA controllers */
 121 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
 122 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
 123
 124 /* DMA controller registers */
 125 #define DMA1_CMD_REG            0x08    /* command register (w) */
 126 #define DMA1_STAT_REG           0x08    /* status register (r) */
 127 #define DMA1_REQ_REG            0x09    /* request register (w) */
 128 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
 129 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
 130 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
 131 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
 132 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
 133 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
 134 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
 135
 136 #define DMA2_CMD_REG            0xD0    /* command register (w) */
 137 #define DMA2_STAT_REG           0xD0    /* status register (r) */
 138 #define DMA2_REQ_REG            0xD2    /* request register (w) */
 139 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 140 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
 141 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 142 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 143 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 144 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 145 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 146
 147 #define DMA_ADDR_0              0x00    /* DMA address registers */
 148 #define DMA_ADDR_1              0x02
 149 #define DMA_ADDR_2              0x04
 150 #define DMA_ADDR_3              0x06
 151 #define DMA_ADDR_4              0xC0
 152 #define DMA_ADDR_5              0xC4
 153 #define DMA_ADDR_6              0xC8
 154 #define DMA_ADDR_7              0xCC
 155
 156 #define DMA_CNT_0               0x01    /* DMA count registers */
 157 #define DMA_CNT_1               0x03
 158 #define DMA_CNT_2               0x05
 159 #define DMA_CNT_3               0x07
 160 #define DMA_CNT_4               0xC2
 161 #define DMA_CNT_5               0xC6
 162 #define DMA_CNT_6               0xCA
 163 #define DMA_CNT_7               0xCE
 164
 165 #define DMA_LO_PAGE_0              0x87    /* DMA page registers */
 166 #define DMA_LO_PAGE_1              0x83
 167 #define DMA_LO_PAGE_2              0x81
 168 #define DMA_LO_PAGE_3              0x82
 169 #define DMA_LO_PAGE_5              0x8B
 170 #define DMA_LO_PAGE_6              0x89
 171 #define DMA_LO_PAGE_7              0x8A
 172
 173 #define DMA_HI_PAGE_0              0x487    /* DMA page registers */
 174 #define DMA_HI_PAGE_1              0x483
 175 #define DMA_HI_PAGE_2              0x481
 176 #define DMA_HI_PAGE_3              0x482
 177 #define DMA_HI_PAGE_5              0x48B
 178 #define DMA_HI_PAGE_6              0x489
 179 #define DMA_HI_PAGE_7              0x48A
 180
 181 #define DMA1_EXT_REG               0x40B
 182 #define DMA2_EXT_REG               0x4D6
 183
 184 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 185 #define DMA_AUTOINIT     0x10
 186
 187 extern spinlock_t  dma_spin_lock;
 188
 189 static __inline__ unsigned long claim_dma_lock(void)
 190 {
 191         unsigned long flags;
 192         spin_lock_irqsave(&dma_spin_lock, flags);
 193         return flags;
 194 }
 195
 196 static __inline__ void release_dma_lock(unsigned long flags)
 197 {
 198         spin_unlock_irqrestore(&dma_spin_lock, flags);
 199 }
 200
 201 /* enable/disable a specific DMA channel */
 202 static __inline__ void enable_dma(unsigned int dmanr)
 203 {
 204         /*
 205          * The Radstone PPC2 and PPC2a boards have inverted DREQ
 206          * lines (active low) so each command needs to be logically
 207          * ORed with 0x40
 208          */
 209         unsigned char ucDmaCmd=0x00;
 210
 211 #if defined(CONFIG_PREP) || defined(CONFIG_ALL_PPC)
 212         if(_prep_type==_PREP_Radstone)
 213         {
 214                 switch(ucSystemType)
 215                 {
 216                         case RS_SYS_TYPE_PPC2:
 217                         case RS_SYS_TYPE_PPC2a:
 218                         case RS_SYS_TYPE_PPC2ep:
 219                         {
 220                                 /*
 221                                  * DREQ lines are active low
 222                                  */
 223                                 ucDmaCmd=0x40;
 224                                 break;
 225                         }
 226
 227                         default:
 228                         {
 229                                 /*
 230                                  * DREQ lines are active high
 231                                  */
 232                                 break;
 233                         }
 234                 }
 235         }
 236 #endif /* CONFIG_PREP || CONFIG_ALL_PPC */
 237
 238         if (dmanr != 4)
 239         {
 240                 dma_outb(0, DMA2_MASK_REG);  /* This may not be enabled */
 241                 dma_outb(ucDmaCmd, DMA2_CMD_REG);  /* Enable group */
 242         }
 243         if (dmanr<=3)
 244         {
 245                 dma_outb(dmanr,  DMA1_MASK_REG);
 246                 dma_outb(ucDmaCmd, DMA1_CMD_REG);  /* Enable group */
 247         } else
 248         {
 249                 dma_outb(dmanr & 3,  DMA2_MASK_REG);
 250         }
 251 }
 252
 253 static __inline__ void disable_dma(unsigned int dmanr)
 254 {
 255         if (dmanr<=3)
 256                 dma_outb(dmanr | 4,  DMA1_MASK_REG);
 257         else
 258                 dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 259 }
 260
 261 /* Clear the 'DMA Pointer Flip Flop'.
 262  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 263  * Use this once to initialize the FF to a known state.
 264  * After that, keep track of it. :-)
 265  * --- In order to do that, the DMA routines below should ---
 266  * --- only be used while interrupts are disabled! ---
 267  */
 268 static __inline__ void clear_dma_ff(unsigned int dmanr)
 269 {
 270         if (dmanr<=3)
 271                 dma_outb(0,  DMA1_CLEAR_FF_REG);
 272         else
 273                 dma_outb(0,  DMA2_CLEAR_FF_REG);
 274 }
 275
 276 /* set mode (above) for a specific DMA channel */
 277 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 278 {
 279         if (dmanr<=3)
 280                 dma_outb(mode | dmanr,  DMA1_MODE_REG);
 281         else
 282                 dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 283 }
 284
 285 /* Set only the page register bits of the transfer address.
 286  * This is used for successive transfers when we know the contents of
 287  * the lower 16 bits of the DMA current address register, but a 64k boundary
 288  * may have been crossed.
 289  */
 290 static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
 291 {
 292         switch(dmanr) {
 293                 case 0:
 294                         dma_outb(pagenr, DMA_LO_PAGE_0);
 295                         dma_outb(pagenr>>8, DMA_HI_PAGE_0);
 296                         break;
 297                 case 1:
 298                         dma_outb(pagenr, DMA_LO_PAGE_1);
 299                         dma_outb(pagenr>>8, DMA_HI_PAGE_1);
 300                         break;
 301                 case 2:
 302                         dma_outb(pagenr, DMA_LO_PAGE_2);
 303                         dma_outb(pagenr>>8, DMA_HI_PAGE_2);
 304                         break;
 305                 case 3:
 306                         dma_outb(pagenr, DMA_LO_PAGE_3);
 307                         dma_outb(pagenr>>8, DMA_HI_PAGE_3);
 308                         break;
 309                 case 5:
 310                         if (SND_DMA1 == 5 || SND_DMA2 == 5)
 311                                 dma_outb(pagenr, DMA_LO_PAGE_5);
 312                         else
 313                                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
 314                         dma_outb(pagenr>>8, DMA_HI_PAGE_5);
 315                         break;
 316                 case 6:
 317                         if (SND_DMA1 == 6 || SND_DMA2 == 6)
 318                                 dma_outb(pagenr, DMA_LO_PAGE_6);
 319                         else
 320                                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
 321                         dma_outb(pagenr>>8, DMA_HI_PAGE_6);
 322                         break;
 323                 case 7:
 324                         if (SND_DMA1 == 7 || SND_DMA2 == 7)
 325                                 dma_outb(pagenr, DMA_LO_PAGE_7);
 326                         else
 327                                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
 328                         dma_outb(pagenr>>8, DMA_HI_PAGE_7);
 329                   break;
 330         }
 331 }
 332
 333
 334 /* Set transfer address & page bits for specific DMA channel.
 335  * Assumes dma flipflop is clear.
 336  */
 337 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
 338 {
 339         if (dmanr <= 3)  {
 340             dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 341             dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 342         }  else  {
 343           if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
 344             dma_outb( phys  & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 345             dma_outb( (phys>>8)  & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 346             dma_outb( (dmanr&3), DMA2_EXT_REG);
 347           } else {
 348             dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 349             dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 350           }
 351         }
 352         set_dma_page(dmanr, phys>>16);
 353 }
 354
 355
 356 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 357  * a specific DMA channel.
 358  * You must ensure the parameters are valid.
 359  * NOTE: from a manual: "the number of transfers is one more
 360  * than the initial word count"! This is taken into account.
 361  * Assumes dma flip-flop is clear.
 362  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 363  */
 364 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 365 {
 366         count--;
 367         if (dmanr <= 3)  {
 368             dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 369             dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 370         } else {
 371           if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
 372             dma_outb( count & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 373             dma_outb( (count>>8) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 374           } else {
 375             dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 376             dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 377           }
 378         }
 379 }
 380
 381
 382 /* Get DMA residue count. After a DMA transfer, this
 383  * should return zero. Reading this while a DMA transfer is
 384  * still in progress will return unpredictable results.
 385  * If called before the channel has been used, it may return 1.
 386  * Otherwise, it returns the number of _bytes_ left to transfer.
 387  *
 388  * Assumes DMA flip-flop is clear.
 389  */
 390 static __inline__ int get_dma_residue(unsigned int dmanr)
 391 {
 392         unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 393                                          : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 394
 395         /* using short to get 16-bit wrap around */
 396         unsigned short count;
 397
 398         count = 1 + dma_inb(io_port);
 399         count += dma_inb(io_port) << 8;
 400
 401         return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
 402           ? count : (count<<1);
 403 }
 404
 405 /* These are in kernel/dma.c: */
 406 extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 407 extern void free_dma(unsigned int dmanr);       /* release it again */
 408
 409 #ifdef CONFIG_PCI
 410 extern int isa_dma_bridge_buggy;
 411 #else
 412 #define isa_dma_bridge_buggy   (0)
 413 #endif
 414 #endif /* _ASM_DMA_H */
 415 #endif /* __KERNEL__ */