drivers/scsi/cyberstorm.c

   1 /* cyberstorm.c: Driver for CyberStorm SCSI Controller.
   2  *
   3  * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
   4  *
   5  * The CyberStorm SCSI driver is based on David S. Miller's ESP driver
   6  * for the Sparc computers.
   7  *
   8  * This work was made possible by Phase5 who willingly (and most generously)
   9  * supported me with hardware and all the information I needed.
  10  */
  11
  12 /* TODO:
  13  *
  14  * 1) Figure out how to make a cleaner merge with the sparc driver with regard
  15  *    to the caches and the Sparc MMU mapping.
  16  * 2) Make as few routines required outside the generic driver. A lot of the
  17  *    routines in this file used to be inline!
  18  */
  19
  20 #include <linux/module.h>
  21
  22 #include <linux/init.h>
  23 #include <linux/kernel.h>
  24 #include <linux/delay.h>
  25 #include <linux/types.h>
  26 #include <linux/string.h>
  27 #include <linux/malloc.h>
  28 #include <linux/blk.h>
  29 #include <linux/proc_fs.h>
  30 #include <linux/stat.h>
  31
  32 #include "scsi.h"
  33 #include "hosts.h"
  34 #include "NCR53C9x.h"
  35 #include "cyberstorm.h"
  36
  37 #include <linux/zorro.h>
  38 #include <asm/irq.h>
  39 #include <asm/amigaints.h>
  40 #include <asm/amigahw.h>
  41
  42 #include <asm/pgtable.h>
  43
  44 static int  dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
  45 static int  dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
  46 static void dma_dump_state(struct NCR_ESP *esp);
  47 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
  48 static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
  49 static void dma_ints_off(struct NCR_ESP *esp);
  50 static void dma_ints_on(struct NCR_ESP *esp);
  51 static int  dma_irq_p(struct NCR_ESP *esp);
  52 static void dma_led_off(struct NCR_ESP *esp);
  53 static void dma_led_on(struct NCR_ESP *esp);
  54 static int  dma_ports_p(struct NCR_ESP *esp);
  55 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
  56
  57 static unsigned char ctrl_data = 0;     /* Keep backup of the stuff written
  58                                  * to ctrl_reg. Always write a copy
  59                                  * to this register when writing to
  60                                  * the hardware register!
  61                                  */
  62
  63 volatile unsigned char cmd_buffer[16];
  64                                 /* This is where all commands are put
  65                                  * before they are transfered to the ESP chip
  66                                  * via PIO.
  67                                  */
  68
  69 /***************************************************************** Detection */
  70 int __init cyber_esp_detect(Scsi_Host_Template *tpnt)
  71 {
  72         struct NCR_ESP *esp;
  73         struct zorro_dev *z = NULL;
  74         unsigned long address;
  75
  76         while ((z = zorro_find_device(ZORRO_WILDCARD, z))) {
  77             unsigned long board = z->resource.start;
  78             if ((z->id == ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM ||
  79                  z->id == ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060) &&
  80                 request_mem_region(board+CYBER_ESP_ADDR,
  81                                    sizeof(struct ESP_regs), "NCR53C9x")) {
  82                 /* Figure out if this is a CyberStorm or really a
  83                  * Fastlane/Blizzard Mk II by looking at the board size.
  84                  * CyberStorm maps 64kB
  85                  * (ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM does anyway)
  86                  */
  87                 if(z->resource.end-board != 0xffff) {
  88                         release_mem_region(board+CYBER_ESP_ADDR,
  89                                            sizeof(struct ESP_regs));
  90                         return 0;
  91                 }
  92                 strcpy(z->name, "Cyberstorm SCSI Host Adapter");
  93
  94                 esp = esp_allocate(tpnt, (void *)board+CYBER_ESP_ADDR);
  95
  96                 /* Do command transfer with programmed I/O */
  97                 esp->do_pio_cmds = 1;
  98
  99                 /* Required functions */
 100                 esp->dma_bytes_sent = &dma_bytes_sent;
 101                 esp->dma_can_transfer = &dma_can_transfer;
 102                 esp->dma_dump_state = &dma_dump_state;
 103                 esp->dma_init_read = &dma_init_read;
 104                 esp->dma_init_write = &dma_init_write;
 105                 esp->dma_ints_off = &dma_ints_off;
 106                 esp->dma_ints_on = &dma_ints_on;
 107                 esp->dma_irq_p = &dma_irq_p;
 108                 esp->dma_ports_p = &dma_ports_p;
 109                 esp->dma_setup = &dma_setup;
 110
 111                 /* Optional functions */
 112                 esp->dma_barrier = 0;
 113                 esp->dma_drain = 0;
 114                 esp->dma_invalidate = 0;
 115                 esp->dma_irq_entry = 0;
 116                 esp->dma_irq_exit = 0;
 117                 esp->dma_led_on = &dma_led_on;
 118                 esp->dma_led_off = &dma_led_off;
 119                 esp->dma_poll = 0;
 120                 esp->dma_reset = 0;
 121
 122                 /* SCSI chip speed */
 123                 esp->cfreq = 40000000;
 124
 125                 /* The DMA registers on the CyberStorm are mapped
 126                  * relative to the device (i.e. in the same Zorro
 127                  * I/O block).
 128                  */
 129                 address = (unsigned long)ZTWO_VADDR(board);
 130                 esp->dregs = (void *)(address + CYBER_DMA_ADDR);
 131
 132                 /* ESP register base */
 133                 esp->eregs = (struct ESP_regs *)(address + CYBER_ESP_ADDR);
 134
 135                 /* Set the command buffer */
 136                 esp->esp_command = (volatile unsigned char*) cmd_buffer;
 137                 esp->esp_command_dvma = virt_to_bus(cmd_buffer);
 138
 139                 esp->irq = IRQ_AMIGA_PORTS;
 140                 request_irq(IRQ_AMIGA_PORTS, esp_intr, SA_SHIRQ,
 141                             "CyberStorm SCSI", esp_intr);
 142                 /* Figure out our scsi ID on the bus */
 143                 /* The DMA cond flag contains a hardcoded jumper bit
 144                  * which can be used to select host number 6 or 7.
 145                  * However, even though it may change, we use a hardcoded
 146                  * value of 7.
 147                  */
 148                 esp->scsi_id = 7;
 149
 150                 /* We don't have a differential SCSI-bus. */
 151                 esp->diff = 0;
 152
 153                 esp_initialize(esp);
 154
 155                 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
 156                 esps_running = esps_in_use;
 157                 return esps_in_use;
 158             }
 159         }
 160         return 0;
 161 }
 162
 163 /************************************************************* DMA Functions */
 164 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
 165 {
 166         /* Since the CyberStorm DMA is fully dedicated to the ESP chip,
 167          * the number of bytes sent (to the ESP chip) equals the number
 168          * of bytes in the FIFO - there is no buffering in the DMA controller.
 169          * XXXX Do I read this right? It is from host to ESP, right?
 170          */
 171         return fifo_count;
 172 }
 173
 174 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
 175 {
 176         /* I don't think there's any limit on the CyberDMA. So we use what
 177          * the ESP chip can handle (24 bit).
 178          */
 179         unsigned long sz = sp->SCp.this_residual;
 180         if(sz > 0x1000000)
 181                 sz = 0x1000000;
 182         return sz;
 183 }
 184
 185 static void dma_dump_state(struct NCR_ESP *esp)
 186 {
 187         ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
 188                 esp->esp_id, ((struct cyber_dma_registers *)
 189                               (esp->dregs))->cond_reg));
 190         ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
 191                 custom.intreqr, custom.intenar));
 192 }
 193
 194 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
 195 {
 196         struct cyber_dma_registers *dregs =
 197                 (struct cyber_dma_registers *) esp->dregs;
 198
 199         cache_clear(addr, length);
 200
 201         addr &= ~(1);
 202         dregs->dma_addr0 = (addr >> 24) & 0xff;
 203         dregs->dma_addr1 = (addr >> 16) & 0xff;
 204         dregs->dma_addr2 = (addr >>  8) & 0xff;
 205         dregs->dma_addr3 = (addr      ) & 0xff;
 206         ctrl_data &= ~(CYBER_DMA_WRITE);
 207
 208         /* Check if physical address is outside Z2 space and of
 209          * block length/block aligned in memory. If this is the
 210          * case, enable 32 bit transfer. In all other cases, fall back
 211          * to 16 bit transfer.
 212          * Obviously 32 bit transfer should be enabled if the DMA address
 213          * and length are 32 bit aligned. However, this leads to some
 214          * strange behavior. Even 64 bit aligned addr/length fails.
 215          * Until I've found a reason for this, 32 bit transfer is only
 216          * used for full-block transfers (1kB).
 217          *                                                      -jskov
 218          */
 219 #if 0
 220         if((addr & 0x3fc) || length & 0x3ff || ((addr > 0x200000) &&
 221                                                 (addr < 0xff0000)))
 222                 ctrl_data &= ~(CYBER_DMA_Z3);   /* Z2, do 16 bit DMA */
 223         else
 224                 ctrl_data |= CYBER_DMA_Z3; /* CHIP/Z3, do 32 bit DMA */
 225 #else
 226         ctrl_data &= ~(CYBER_DMA_Z3);   /* Z2, do 16 bit DMA */
 227 #endif
 228         dregs->ctrl_reg = ctrl_data;
 229 }
 230
 231 static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
 232 {
 233         struct cyber_dma_registers *dregs =
 234                 (struct cyber_dma_registers *) esp->dregs;
 235
 236         cache_push(addr, length);
 237
 238         addr |= 1;
 239         dregs->dma_addr0 = (addr >> 24) & 0xff;
 240         dregs->dma_addr1 = (addr >> 16) & 0xff;
 241         dregs->dma_addr2 = (addr >>  8) & 0xff;
 242         dregs->dma_addr3 = (addr      ) & 0xff;
 243         ctrl_data |= CYBER_DMA_WRITE;
 244
 245         /* See comment above */
 246 #if 0
 247         if((addr & 0x3fc) || length & 0x3ff || ((addr > 0x200000) &&
 248                                                 (addr < 0xff0000)))
 249                 ctrl_data &= ~(CYBER_DMA_Z3);   /* Z2, do 16 bit DMA */
 250         else
 251                 ctrl_data |= CYBER_DMA_Z3; /* CHIP/Z3, do 32 bit DMA */
 252 #else
 253         ctrl_data &= ~(CYBER_DMA_Z3);   /* Z2, do 16 bit DMA */
 254 #endif
 255         dregs->ctrl_reg = ctrl_data;
 256 }
 257
 258 static void dma_ints_off(struct NCR_ESP *esp)
 259 {
 260         disable_irq(esp->irq);
 261 }
 262
 263 static void dma_ints_on(struct NCR_ESP *esp)
 264 {
 265         enable_irq(esp->irq);
 266 }
 267
 268 static int dma_irq_p(struct NCR_ESP *esp)
 269 {
 270         /* It's important to check the DMA IRQ bit in the correct way! */
 271         return ((esp_read(esp->eregs->esp_status) & ESP_STAT_INTR) &&
 272                 ((((struct cyber_dma_registers *)(esp->dregs))->cond_reg) &
 273                  CYBER_DMA_HNDL_INTR));
 274 }
 275
 276 static void dma_led_off(struct NCR_ESP *esp)
 277 {
 278         ctrl_data &= ~CYBER_DMA_LED;
 279         ((struct cyber_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
 280 }
 281
 282 static void dma_led_on(struct NCR_ESP *esp)
 283 {
 284         ctrl_data |= CYBER_DMA_LED;
 285         ((struct cyber_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
 286 }
 287
 288 static int dma_ports_p(struct NCR_ESP *esp)
 289 {
 290         return ((custom.intenar) & IF_PORTS);
 291 }
 292
 293 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
 294 {
 295         /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
 296          * so when (write) is true, it actually means READ!
 297          */
 298         if(write){
 299                 dma_init_read(esp, addr, count);
 300         } else {
 301                 dma_init_write(esp, addr, count);
 302         }
 303 }
 304
 305 #ifdef MODULE
 306
 307 #define HOSTS_C
 308
 309 #include "cyberstorm.h"
 310
 311 Scsi_Host_Template driver_template = SCSI_CYBERSTORM;
 312
 313 #include "scsi_module.c"
 314
 315 #endif
 316
 317 int cyber_esp_release(struct Scsi_Host *instance)
 318 {
 319 #ifdef MODULE
 320         unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
 321
 322         esp_deallocate((struct NCR_ESP *)instance->hostdata);
 323         esp_release();
 324         release_mem_region(address, sizeof(struct ESP_regs));
 325         free_irq(IRQ_AMIGA_PORTS, esp_intr);
 326 #endif
 327         return 1;
 328 }