include/asm-sparc/irq.h

   1 /* $Id: irq.h,v 1.30 2000/06/30 10:18:39 davem Exp $
   2  * irq.h: IRQ registers on the Sparc.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #ifndef _SPARC_IRQ_H
   8 #define _SPARC_IRQ_H
   9
  10 #include <linux/config.h>
  11 #include <linux/linkage.h>
  12 #include <linux/threads.h>     /* For NR_CPUS */
  13
  14 #include <asm/system.h>     /* For SUN4M_NCPUS */
  15 #include <asm/btfixup.h>
  16
  17 #define __irq_ino(irq) irq
  18 #define __irq_pil(irq) irq
  19 BTFIXUPDEF_CALL(char *, __irq_itoa, unsigned int)
  20 #define __irq_itoa(irq) BTFIXUP_CALL(__irq_itoa)(irq)
  21
  22 #define NR_IRQS    15
  23
  24 /* IRQ handler dispatch entry and exit. */
  25 #ifdef CONFIG_SMP
  26 extern unsigned int __local_irq_count[NR_CPUS];
  27 #define irq_enter(cpu, irq)                     \
  28 do {    hardirq_enter(cpu);                     \
  29         spin_unlock_wait(&global_irq_lock);     \
  30         } while(0)
  31 #define irq_exit(cpu, irq)      hardirq_exit(cpu)
  32 #else
  33 extern unsigned int __local_irq_count;
  34 #define irq_enter(cpu, irq)     (__local_irq_count++)
  35 #define irq_exit(cpu, irq)      (__local_irq_count--)
  36 #endif
  37
  38 /* Dave Redman (djhr@tadpole.co.uk)
  39  * changed these to function pointers.. it saves cycles and will allow
  40  * the irq dependencies to be split into different files at a later date
  41  * sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size.
  42  * Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  43  * Changed these to btfixup entities... It saves cycles :)
  44  */
  45 BTFIXUPDEF_CALL(void, disable_irq, unsigned int)
  46 BTFIXUPDEF_CALL(void, enable_irq, unsigned int)
  47 BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
  48 BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
  49 BTFIXUPDEF_CALL(void, clear_clock_irq, void)
  50 BTFIXUPDEF_CALL(void, clear_profile_irq, int)
  51 BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
  52
  53 #define disable_irq_nosync disable_irq
  54 #define disable_irq(irq) BTFIXUP_CALL(disable_irq)(irq)
  55 #define enable_irq(irq) BTFIXUP_CALL(enable_irq)(irq)
  56 #define disable_pil_irq(irq) BTFIXUP_CALL(disable_pil_irq)(irq)
  57 #define enable_pil_irq(irq) BTFIXUP_CALL(enable_pil_irq)(irq)
  58 #define clear_clock_irq() BTFIXUP_CALL(clear_clock_irq)()
  59 #define clear_profile_irq(cpu) BTFIXUP_CALL(clear_profile_irq)(cpu)
  60 #define load_profile_irq(cpu,limit) BTFIXUP_CALL(load_profile_irq)(cpu,limit)
  61
  62 extern void (*init_timers)(void (*lvl10_irq)(int, void *, struct pt_regs *));
  63 extern void claim_ticker14(void (*irq_handler)(int, void *, struct pt_regs *),
  64                            int irq,
  65                            unsigned int timeout);
  66
  67 #ifdef CONFIG_SMP
  68 BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
  69 BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
  70 BTFIXUPDEF_CALL(void, set_irq_udt, int)
  71
  72 #define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
  73 #define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
  74 #define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
  75 #endif
  76
  77 extern int request_fast_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), unsigned long flags, __const__ char *devname);
  78
  79 /* On the sun4m, just like the timers, we have both per-cpu and master
  80  * interrupt registers.
  81  */
  82
  83 /* These registers are used for sending/receiving irqs from/to
  84  * different cpu's.
  85  */
  86 struct sun4m_intreg_percpu {
  87         unsigned int tbt;        /* Interrupts still pending for this cpu. */
  88
  89         /* These next two registers are WRITE-ONLY and are only
  90          * "on bit" sensitive, "off bits" written have NO affect.
  91          */
  92         unsigned int clear;  /* Clear this cpus irqs here. */
  93         unsigned int set;    /* Set this cpus irqs here. */
  94         unsigned char space[PAGE_SIZE - 12];
  95 };
  96
  97 /*
  98  * djhr
  99  * Actually the clear and set fields in this struct are misleading..
 100  * according to the SLAVIO manual (and the same applies for the SEC)
 101  * the clear field clears bits in the mask which will ENABLE that IRQ
 102  * the set field sets bits in the mask to DISABLE the IRQ.
 103  *
 104  * Also the undirected_xx address in the SLAVIO is defined as
 105  * RESERVED and write only..
 106  *
 107  * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
 108  *             sun4m machines, for MP the layout makes more sense.
 109  */
 110 struct sun4m_intregs {
 111         struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
 112         unsigned int tbt;                /* IRQ's that are still pending. */
 113         unsigned int irqs;               /* Master IRQ bits. */
 114
 115         /* Again, like the above, two these registers are WRITE-ONLY. */
 116         unsigned int clear;              /* Clear master IRQ's by setting bits here. */
 117         unsigned int set;                /* Set master IRQ's by setting bits here. */
 118
 119         /* This register is both READ and WRITE. */
 120         unsigned int undirected_target;  /* Which cpu gets undirected irqs. */
 121 };
 122
 123 extern struct sun4m_intregs *sun4m_interrupts;
 124
 125 /*
 126  * Bit field defines for the interrupt registers on various
 127  * Sparc machines.
 128  */
 129
 130 /* The sun4c interrupt register. */
 131 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
 132 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
 133 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
 134 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
 135 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
 136 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
 137 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
 138
 139 /* Dave Redman (djhr@tadpole.co.uk)
 140  * The sun4m interrupt registers.
 141  */
 142 #define SUN4M_INT_ENABLE        0x80000000
 143 #define SUN4M_INT_E14           0x00000080
 144 #define SUN4M_INT_E10           0x00080000
 145
 146 #define SUN4M_HARD_INT(x)       (0x000000001 << (x))
 147 #define SUN4M_SOFT_INT(x)       (0x000010000 << (x))
 148
 149 #define SUN4M_INT_MASKALL       0x80000000        /* mask all interrupts */
 150 #define SUN4M_INT_MODULE_ERR    0x40000000        /* module error */
 151 #define SUN4M_INT_M2S_WRITE     0x20000000        /* write buffer error */
 152 #define SUN4M_INT_ECC           0x10000000        /* ecc memory error */
 153 #define SUN4M_INT_FLOPPY        0x00400000        /* floppy disk */
 154 #define SUN4M_INT_MODULE        0x00200000        /* module interrupt */
 155 #define SUN4M_INT_VIDEO         0x00100000        /* onboard video */
 156 #define SUN4M_INT_REALTIME      0x00080000        /* system timer */
 157 #define SUN4M_INT_SCSI          0x00040000        /* onboard scsi */
 158 #define SUN4M_INT_AUDIO         0x00020000        /* audio/isdn */
 159 #define SUN4M_INT_ETHERNET      0x00010000        /* onboard ethernet */
 160 #define SUN4M_INT_SERIAL        0x00008000        /* serial ports */
 161 #define SUN4M_INT_KBDMS         0x00004000        /* keyboard/mouse */
 162 #define SUN4M_INT_SBUSBITS      0x00003F80        /* sbus int bits */
 163
 164 #define SUN4M_INT_SBUS(x)       (1 << (x+7))
 165 #define SUN4M_INT_VME(x)        (1 << (x))
 166
 167 #endif