drivers/sound/trident.h

   1 #ifndef __TRID4DWAVE_H
   2 #define __TRID4DWAVE_H
   3
   4 /*
   5  *  audio@tridentmicro.com
   6  *  Fri Feb 19 15:55:28 MST 1999
   7  *  Definitions for Trident 4DWave DX/NX chips
   8  *
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  *
  24  */
  25
  26 /* PCI vendor and device ID */
  27 #ifndef PCI_VENDOR_ID_TRIDENT
  28 #define PCI_VENDOR_ID_TRIDENT           0x1023
  29 #endif
  30
  31 #ifndef PCI_VENDOR_ID_SI
  32 #define PCI_VENDOR_ID_SI                        0x0139
  33 #endif
  34
  35 #ifndef PCI_VENDOR_ID_ALI
  36 #define PCI_VENDOR_ID_ALI                       0x10b9
  37 #endif
  38
  39 #ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_DX
  40 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
  41 #endif
  42
  43 #ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_NX
  44 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
  45 #endif
  46
  47 #ifndef PCI_DEVICE_ID_SI_7018
  48 #define PCI_DEVICE_ID_SI_7018           0x7018
  49 #endif
  50
  51 #ifndef PCI_DEVICE_ID_ALI_5451
  52 #define PCI_DEVICE_ID_ALI_5451          0x5451
  53 #endif
  54
  55 #ifndef FALSE
  56 #define FALSE           0
  57 #define TRUE            1
  58 #endif
  59
  60 #define CHANNEL_REGS    5
  61 #define CHANNEL_START   0xe0   // The first bytes of the contiguous register space.
  62
  63 #define BANK_A          0
  64 #define BANK_B          1
  65 #define NR_BANKS                2
  66
  67 #define TRIDENT_FMT_STEREO     0x01
  68 #define TRIDENT_FMT_16BIT      0x02
  69 #define TRIDENT_FMT_MASK       0x03
  70
  71 #define DAC_RUNNING     0x01
  72 #define ADC_RUNNING     0x02
  73
  74 /* Register Addresses */
  75
  76 /* operational registers common to DX, NX, 7018 */
  77 enum trident_op_registers {
  78         T4D_REC_CH      = 0x70,
  79         T4D_START_A     = 0x80, T4D_STOP_A      = 0x84,
  80         T4D_DLY_A       = 0x88, T4D_SIGN_CSO_A  = 0x8c,
  81         T4D_CSPF_A      = 0x90, T4D_CEBC_A      = 0x94,
  82         T4D_AINT_A      = 0x98, T4D_EINT_A      = 0x9c,
  83         T4D_LFO_GC_CIR  = 0xa0, T4D_AINTEN_A    = 0xa4,
  84         T4D_MUSICVOL_WAVEVOL = 0xa8, T4D_SBDELTA_DELTA_R = 0xac,
  85         T4D_MISCINT     = 0xb0, T4D_START_B     = 0xb4,
  86         T4D_STOP_B      = 0xb8, T4D_CSPF_B      = 0xbc,
  87         T4D_SBBL_SBCL   = 0xc0, T4D_SBCTRL_SBE2R_SBDD    = 0xc4,
  88         T4D_STIMER      = 0xc8, T4D_LFO_B_I2S_DELTA      = 0xcc,
  89         T4D_AINT_B      = 0xd8, T4D_AINTEN_B    = 0xdc
  90 };
  91
  92 enum ali_op_registers {
  93         ALI_GLOBAL_CONTROL      = 0xd4,
  94         ALI_STIMER              = 0xc8
  95 };
  96
  97 enum ali_global_control_bit {
  98         ALI_PCM_IN_ENABLE       = 0x80000000,
  99         ALI_PCM_IN_DISABLE      = 0x7fffffff
 100 };
 101
 102 enum ali_pcm_in_channel_num {
 103         ALI_PCM_IN_CHANNEL      = 31
 104 };
 105
 106 enum ali_pcm_out_channel_num {
 107         ALI_PCM_OUT_CHANNEL_FIRST = 1,
 108         ALI_PCM_OUT_CHANNEL_LAST = 30
 109 };
 110
 111 enum ali_ac97_power_control_bit {
 112         ALI_EAPD_POWER_DOWN     = 0x8000
 113 };
 114
 115 enum ali_update_ptr_flags {
 116         ALI_ADDRESS_INT_UPDATE  = 0x01
 117 };
 118
 119 /* S/PDIF Operational Registers for 4D-NX */
 120 enum nx_spdif_registers {
 121         NX_SPCTRL_SPCSO = 0x24, NX_SPLBA = 0x28,
 122         NX_SPESO        = 0x2c, NX_SPCSTATUS = 0x64
 123 };
 124
 125 /* OP registers to access each hardware channel */
 126 enum channel_registers {
 127         CH_DX_CSO_ALPHA_FMS = 0xe0, CH_DX_ESO_DELTA = 0xe8,
 128         CH_DX_FMC_RVOL_CVOL = 0xec,
 129         CH_NX_DELTA_CSO     = 0xe0, CH_NX_DELTA_ESO = 0xe8,
 130         CH_NX_ALPHA_FMS_FMC_RVOL_CVOL = 0xec,
 131         CH_LBA              = 0xe4,
 132         CH_GVSEL_PAN_VOL_CTRL_EC      = 0xf0
 133 };
 134
 135 /* registers to read/write/control AC97 codec */
 136 enum dx_ac97_registers {
 137         DX_ACR0_AC97_W        = 0x40, DX_ACR1_AC97_R = 0x44,
 138         DX_ACR2_AC97_COM_STAT = 0x48
 139 };
 140
 141 enum nx_ac97_registers {
 142         NX_ACR0_AC97_COM_STAT  = 0x40, NX_ACR1_AC97_W           = 0x44,
 143         NX_ACR2_AC97_R_PRIMARY = 0x48, NX_ACR3_AC97_R_SECONDARY = 0x4c
 144 };
 145
 146 enum si_ac97_registers {
 147         SI_AC97_WRITE       = 0x40, SI_AC97_READ = 0x44,
 148         SI_SERIAL_INTF_CTRL = 0x48, SI_AC97_GPIO = 0x4c
 149 };
 150
 151 enum ali_ac97_registers {
 152         ALI_AC97_WRITE       = 0x40, ALI_AC97_READ = 0x44
 153 };
 154
 155 /* Bit mask for operational registers */
 156 #define AC97_REG_ADDR      0x000000ff
 157
 158 enum ali_ac97_bits {
 159         ALI_AC97_BUSY_WRITE = 0x8000, ALI_AC97_BUSY_READ = 0x8000,
 160         ALI_AC97_WRITE_ACTION = 0x8000, ALI_AC97_READ_ACTION = 0x8000,
 161         ALI_AC97_AUDIO_BUSY = 0x4000, ALI_AC97_SECONDARY  = 0x0080,
 162         ALI_AC97_READ_MIXER_REGISTER = 0xfeff,
 163         ALI_AC97_WRITE_MIXER_REGISTER = 0x0100
 164 };
 165
 166 enum sis7018_ac97_bits {
 167         SI_AC97_BUSY_WRITE = 0x8000, SI_AC97_BUSY_READ = 0x8000,
 168         SI_AC97_AUDIO_BUSY = 0x4000, SI_AC97_MODEM_BUSY = 0x2000,
 169         SI_AC97_SECONDARY  = 0x0080
 170 };
 171
 172 enum trident_dx_ac97_bits {
 173         DX_AC97_BUSY_WRITE = 0x8000, DX_AC97_BUSY_READ = 0x8000,
 174         DX_AC97_READY      = 0x0010, DX_AC97_RECORD    = 0x0008,
 175         DX_AC97_PLAYBACK   = 0x0002
 176 };
 177
 178 enum trident_nx_ac97_bits {
 179         /* ACR1-3 */
 180         NX_AC97_BUSY_WRITE = 0x0800, NX_AC97_BUSY_READ = 0x0800,
 181         NX_AC97_BUSY_DATA  = 0x0400, NX_AC97_WRITE_SECONDARY = 0x0100,
 182         /* ACR0 */
 183         NX_AC97_SECONDARY_READY = 0x0040, NX_AC97_SECONDARY_RECORD = 0x0020,
 184         NX_AC97_SURROUND_OUTPUT = 0x0010,
 185         NX_AC97_PRIMARY_READY   = 0x0008, NX_AC97_PRIMARY_RECORD   = 0x0004,
 186         NX_AC97_PCM_OUTPUT      = 0x0002,
 187         NX_AC97_WARM_RESET      = 0x0001
 188 };
 189
 190 enum serial_intf_ctrl_bits {
 191         WARM_REST   = 0x00000001, COLD_RESET  = 0x00000002,
 192         I2S_CLOCK   = 0x00000004, PCM_SEC_AC97= 0x00000008,
 193         AC97_DBL_RATE = 0x00000010, SPDIF_EN  = 0x00000020,
 194         I2S_OUTPUT_EN = 0x00000040, I2S_INPUT_EN = 0x00000080,
 195         PCMIN       = 0x00000100, LINE1IN     = 0x00000200,
 196         MICIN       = 0x00000400, LINE2IN     = 0x00000800,
 197         HEAD_SET_IN = 0x00001000, GPIOIN      = 0x00002000,
 198         /* 7018 spec says id = 01 but the demo board routed to 10
 199            SECONDARY_ID= 0x00004000, */
 200         SECONDARY_ID= 0x00004000,
 201         PCMOUT      = 0x00010000, SURROUT     = 0x00020000,
 202         CENTEROUT   = 0x00040000, LFEOUT      = 0x00080000,
 203         LINE1OUT    = 0x00100000, LINE2OUT    = 0x00200000,
 204         GPIOOUT     = 0x00400000,
 205         SI_AC97_PRIMARY_READY   = 0x01000000,
 206         SI_AC97_SECONDARY_READY = 0x02000000,
 207 };
 208
 209 enum global_control_bits {
 210         CHANNLE_IDX = 0x0000003f, PB_RESET    = 0x00000100,
 211         PAUSE_ENG   = 0x00000200,
 212         OVERRUN_IE  = 0x00000400, UNDERRUN_IE = 0x00000800,
 213         ENDLP_IE    = 0x00001000, MIDLP_IE    = 0x00002000,
 214         ETOG_IE     = 0x00004000,
 215         EDROP_IE    = 0x00008000, BANK_B_EN   = 0x00010000
 216 };
 217
 218 enum channel_control_bits {
 219         CHANNEL_LOOP   = 0x00001000, CHANNEL_SIGNED = 0x00002000,
 220         CHANNEL_STEREO = 0x00004000, CHANNEL_16BITS = 0x00008000,
 221 };
 222
 223 enum channel_attribute {
 224         /* playback/record select */
 225         CHANNEL_PB     = 0x0000, CHANNEL_SPC_PB = 0x4000,
 226         CHANNEL_REC    = 0x8000, CHANNEL_REC_PB = 0xc000,
 227         /* playback destination/record source select */
 228         MODEM_LINE1    = 0x0000, MODEM_LINE2    = 0x0400,
 229         PCM_LR         = 0x0800, HSET           = 0x0c00,
 230         I2S_LR         = 0x1000, CENTER_LFE     = 0x1400,
 231         SURR_LR        = 0x1800, SPDIF_LR       = 0x1c00,
 232         MIC            = 0x1400,
 233         /* mist stuff */
 234         MONO_LEFT      = 0x0000, MONO_RIGHT     = 0x0100,
 235         MONO_MIX       = 0x0200, SRC_ENABLE     = 0x0080,
 236 };
 237
 238 enum miscint_bits {
 239         PB_UNDERRUN_IRO = 0x00000001, REC_OVERRUN_IRQ = 0x00000002,
 240         SB_IRQ          = 0x00000004, MPU401_IRQ      = 0x00000008,
 241         OPL3_IRQ        = 0x00000010, ADDRESS_IRQ     = 0x00000020,
 242         ENVELOPE_IRQ    = 0x00000040, ST_IRQ          = 0x00000080,
 243         PB_UNDERRUN     = 0x00000100, REC_OVERRUN     = 0x00000200,
 244         MIXER_UNDERFLOW = 0x00000400, MIXER_OVERFLOW  = 0x00000800,
 245         ST_TARGET_REACHED = 0x00008000, PB_24K_MODE   = 0x00010000,
 246         ST_IRQ_EN       = 0x00800000, ACGPIO_IRQ      = 0x01000000
 247 };
 248
 249 #define TRID_REG( trident, x ) ( (trident) -> iobase + (x) )
 250
 251 #define VALIDATE_MAGIC(FOO,MAG)                         \
 252 ({                                                \
 253         if (!(FOO) || (FOO)->magic != MAG) { \
 254                 printk(invalid_magic,__FUNCTION__);            \
 255                 return -ENXIO;                    \
 256         }                                         \
 257 })
 258
 259 #define VALIDATE_STATE(a) VALIDATE_MAGIC(a,TRIDENT_STATE_MAGIC)
 260 #define VALIDATE_CARD(a) VALIDATE_MAGIC(a,TRIDENT_CARD_MAGIC)
 261
 262
 263 extern __inline__ unsigned ld2(unsigned int x)
 264 {
 265         unsigned r = 0;
 266
 267         if (x >= 0x10000) {
 268                 x >>= 16;
 269                 r += 16;
 270         }
 271         if (x >= 0x100) {
 272                 x >>= 8;
 273                 r += 8;
 274         }
 275         if (x >= 0x10) {
 276                 x >>= 4;
 277                 r += 4;
 278         }
 279         if (x >= 4) {
 280                 x >>= 2;
 281                 r += 2;
 282         }
 283         if (x >= 2)
 284                 r++;
 285         return r;
 286 }
 287
 288 #endif /* __TRID4DWAVE_H */
 289