2015-01-03 | Jimmy Zhang | arm: lpae: Set XN and PXN bits for noncacheable regions Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> |
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2014-12-19 | Jimmy Zhang | nyan*: Add fast link training functions Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> |
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2014-12-16 | Jimmy Zhang | nyan*: debug: Add sor registers dump function Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> |
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2014-12-16 | Jimmy Zhang | nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 register Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> |
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2014-12-16 | Jimmy Zhang | nyan*: merge a couple of sor setting difference from... Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> |
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2014-12-16 | Jimmy Zhang | nyan*: Apply sor fix from kernel dc driver Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> |
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2014-12-15 | Jimmy Zhang | tegra124: set safe values for href_to_sync and vref_to_sync Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> |
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2014-11-14 | Jimmy Zhang | t124: Clean up display init functions Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> |
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2014-11-13 | Jimmy Zhang | t124: Skip PLLP init to 408MHz Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> |
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2014-11-13 | Jimmy Zhang | t124: nyan: Enable lock bit on pll Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> |
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2014-11-13 | Jimmy Zhang | nyan: Add 4GB bct support Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> |
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2014-11-12 | Jimmy Zhang | tegra124: enable JTAG in Security Mode Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> |
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