From cfe15a20880ecb873942c4c272b6464448137d24 Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Tue, 5 Oct 2021 08:33:08 +0800 Subject: [PATCH] mb/ocp/deltalake: Fix SMBIOS type 9 bugs 1. Fix PCIe slot capabilities not being really read from an IIO root port device. The Hot-Plug capability of IIO root port cannot be enabled due to FSP limitation (v2.1-0.2.2.0), but the code should reflect the true capabilities by reading the root port device's CSR. 2. Initialize the characteristics flags to 0 in the for-loop to fix the issue of the flags values persists to the next iterations. Tested=On OCP Delta Lake, dmidecode -t 9 shows the expected results. For example without the fix it shows 'Hot-plug devices are supported' but in fact it's not: System Slot Information Designation: SSD1_M2_Data_Drive Type: x4 PCI Express 3 x4 Current Usage: Available Length: Short ID: 1 Characteristics: 3.3 V is provided PME signal is supported Hot-plug devices are supported Bus Address: 0000:00:1d.0 With the fix it shows the correct result: Handle 0x0016, DMI type 9, 19 bytes System Slot Information Designation: SSD1_M2_Data_Drive Type: x4 PCI Express 3 x4 Current Usage: Available Length: Short ID: 1 Characteristics: 3.3 V is provided PME signal is supported Bus Address: 0000:00:1d.0 Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9 Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/58100 Reviewed-by: Johnny Lin Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Jonathan Zhang Tested-by: build bot (Jenkins) --- src/mainboard/ocp/deltalake/ramstage.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 8d9de82751..d8653b9002 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -194,11 +194,9 @@ static int create_smbios_type9(int *handle, unsigned long *current) uint8_t sec_bus; uint8_t slot_usage; uint8_t pcie_config = 0; - uint8_t characteristics_1 = 0; - uint8_t characteristics_2 = 0; uint32_t vendor_device_id; uint8_t stack_busnos[MAX_IIO_STACK]; - pci_devfn_t pci_dev; + pci_devfn_t pci_dev_slot, pci_dev = 0; unsigned int cap; uint16_t sltcap; @@ -209,6 +207,9 @@ static int create_smbios_type9(int *handle, unsigned long *current) stack_busnos[index] = get_stack_busno(index); for (index = 0; index < ARRAY_SIZE(slotinfo); index++) { + uint8_t characteristics_1 = 0; + uint8_t characteristics_2 = 0; + if (pcie_config == PCIE_CONFIG_A) { if (index == 0 || index == 1 || index == 2) printk(BIOS_INFO, "Find Config-A slot: %s\n", @@ -251,14 +252,14 @@ static int create_smbios_type9(int *handle, unsigned long *current) else slot_length = SlotLengthShort; - pci_dev = PCI_DEV(stack_busnos[slotinfo[index].stack], + pci_dev_slot = PCI_DEV(stack_busnos[slotinfo[index].stack], slotinfo[index].dev_func >> 3, slotinfo[index].dev_func & 0x7); - sec_bus = pci_s_read_config8(pci_dev, PCI_SECONDARY_BUS); + sec_bus = pci_s_read_config8(pci_dev_slot, PCI_SECONDARY_BUS); if (sec_bus == 0xFF) { slot_usage = SlotUsageUnknown; } else { - /* Checking for Slot device availability */ + /* Checking for downstream device availability */ pci_dev = PCI_DEV(sec_bus, 0, 0); vendor_device_id = pci_s_read_config32(pci_dev, 0); if (vendor_device_id == 0xFFFFFFFF) @@ -269,13 +270,16 @@ static int create_smbios_type9(int *handle, unsigned long *current) characteristics_1 |= SMBIOS_SLOT_3P3V; // Provides33Volts characteristics_2 |= SMBIOS_SLOT_PME; // PmeSiganalSupported - - cap = pci_s_find_capability(pci_dev, PCI_CAP_ID_PCIE); - sltcap = pci_s_read_config16(pci_dev, cap + PCI_EXP_SLTCAP); + /* Read IIO root port device CSR for slot capabilities */ + cap = pci_s_find_capability(pci_dev_slot, PCI_CAP_ID_PCIE); + sltcap = pci_s_read_config16(pci_dev_slot, cap + PCI_EXP_SLTCAP); if (sltcap & PCI_EXP_SLTCAP_HPC) characteristics_2 |= SMBIOS_SLOT_HOTPLUG; const uint16_t slot_id = index + 1; + /* According to SMBIOS spec, the BDF number should be the end + point on the slot, for now we keep using the root port's BDF to + be aligned with our UEFI reference BIOS. */ length += smbios_write_type9(current, handle, slotinfo[index].slot_designator, slotinfo[index].slot_type, -- 2.11.4.GIT