From b4a169a1e19969ef584e19a57df2a5cd0ae3b573 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 29 Dec 2021 18:36:23 +0000 Subject: [PATCH] soc/intel/alderlake: Add option to make MRC log silent Typically, FSP-M aka MRC debug log level defaults to `3` meaning prints all `Load, Error, Warnings & Info` messages. Sometimes it's too much information to parse even when users aren't required to have such detailed information hence, implement `fsp_map_console_log_level()` that maps coreboot console log level to FSP-M debug log level and suppress verbose MRC debug messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and then the user can enable `DEBUG_RAM_SETUP`. TEST=FSP-M debug log suggested default `SerialDebugMrcLevel` UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP` and user to select `DEBUG_RAM_SETUP` config to override `SerialDebugMrcLevel` UPD value to '5' aka verbose. Signed-off-by: Subrata Banik Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60441 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Nico Huber --- src/soc/intel/alderlake/Kconfig | 1 + src/soc/intel/alderlake/romstage/fsp_params.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0c68351eb3..50c0c0b3e5 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select FSPS_HAS_ARCH_UPD select GENERIC_GPIO_LIB + select HAVE_DEBUG_RAM_SETUP select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 8959bf7d46..0eeaabde69 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -312,6 +312,9 @@ static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { + /* Set MRC debug level */ + m_cfg->SerialDebugMrcLevel = fsp_map_console_log_level(); + /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; -- 2.11.4.GIT