From a0f8dc3bd55d4706606e14173bb9afaa97049287 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 11 Oct 2021 14:01:55 +0200 Subject: [PATCH] soc/intel/cannonlake: Enable Energy/Performance Bias control MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Set POWER_CTL MSR bit 18 to enable Energy/Performance Bias control. TEST=Boot and verify EPB is enabled in coreboot log: cpu: energy policy set to 6 Change-Id: Ibd1db77b5b63cb6e2b0ad9d2f79caa2f3b576ead Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58221 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Patrick Rudolph Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 99fcadd581..8c8cad098e 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -51,6 +51,7 @@ static void configure_misc(void) /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ + msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } -- 2.11.4.GIT