From 8e345d4ca2a13ebdf9edf1071d7c4f03d084d143 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 15 Jan 2013 15:34:08 -0600 Subject: [PATCH] haswell: lapic timer support Haswell's BCLK is fised at 100MHz like Sandy/Ivy. Add Haswell's model to the switch statement. Change-Id: Ib9e2afc04eba940bfcee92a6ee5402759b21cc45 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/2747 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/cpu/x86/lapic/apic_timer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index cd6e472494..b60da27256 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -62,6 +62,8 @@ static int set_timer_fsb(void) break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ + case 0x3c: /* Haswell BCLK fixed at 100MHz */ + case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ timer_fsb = 100; break; default: -- 2.11.4.GIT