From 8b64e7ae21f2042f837f3af222754e1e8ef5b3d6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 22 Sep 2017 12:30:54 +0200 Subject: [PATCH] mb/intel/dg43gt: Add romstage timestamps MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Change-Id: I0383dd9b582d5c77be66ecd74bcf1a438f874cc7 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/21635 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Paul Menzel --- src/mainboard/intel/dg43gt/romstage.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 5b9816345d..6944b1819e 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -25,6 +25,7 @@ #include #include #include +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0) @@ -71,6 +72,9 @@ void mainboard_romstage_entry(unsigned long bist) u8 boot_path = 0; u8 s3_resume; + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -93,7 +97,9 @@ void mainboard_romstage_entry(unsigned long bist) boot_path = BOOT_PATH_WARM_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); + timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); printk(BIOS_DEBUG, "Memory initialized\n"); -- 2.11.4.GIT