From 0515aa1978ad9795ea0e9a1b0dcada7f3a13f21c Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 15 Oct 2021 14:22:30 +0200
Subject: [PATCH] mb/prodrive/hermes: Remove overridetree

There's no need to have an overridetree with a single board variant.

TEST=Compare static.c and observe only device order has changed.

Change-Id: I2097e247c27d5d0c5479cb533b477cd490a4c827
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
---
 src/mainboard/prodrive/hermes/Kconfig              |  3 --
 .../baseboard/overridetree.cb => devicetree.cb}    | 47 ++++++++++++++++++----
 2 files changed, 40 insertions(+), 10 deletions(-)
 rename src/mainboard/prodrive/hermes/{variants/baseboard/overridetree.cb => devicetree.cb} (82%)

diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig
index bdb8e497b2..2fecc06f6d 100644
--- a/src/mainboard/prodrive/hermes/Kconfig
+++ b/src/mainboard/prodrive/hermes/Kconfig
@@ -51,9 +51,6 @@ config MAX_CPUS
 	int
 	default 16
 
-config OVERRIDE_DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-
 config CONSOLE_POST
 	bool
 	default y
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb
similarity index 82%
rename from src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
rename to src/mainboard/prodrive/hermes/devicetree.cb
index 16ba724e9e..69658211f9 100644
--- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
+++ b/src/mainboard/prodrive/hermes/devicetree.cb
@@ -1,9 +1,4 @@
 chip soc/intel/cannonlake
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
 	# FSP configuration
 
 	register "SataMode" = "0"		# AHCI
@@ -100,7 +95,6 @@ chip soc/intel/cannonlake
 	# Thermal
 	register "tcc_offset" = "1"     # TCC of 99C
 
-
 	# Disable S0ix
 	register "s0ix_enable" = "0"
 
@@ -133,15 +127,39 @@ chip soc/intel/cannonlake
 
 	register "DisableHeciRetry" = "1"
 
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
 	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on # PEG x8             / Slot 2
+			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT2" "SlotDataBusWidth8X"
+		end
+		device pci 01.1 on # PEG x4 or x8       / Slot 6
+			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT6" "SlotDataBusWidth4X"
+		end
+		device pci 01.2 on # PEG x4 or disabled / Slot 4
+			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT4" "SlotDataBusWidth4X"
+		end
 		device pci 02.0 on end	# Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 08.0 on  end # Gaussian Mixture
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # RAM controller
 		device pci 14.3 on
 			chip drivers/wifi/generic
 				register "wake" = "PME_B0_EN_BIT"
 				device generic 0 on end
 			end
 		end  # CNVi wifi
-
+		device pci 14.5 off end # SDCard
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 on  end # Management Engine Interface 2
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 17.0 on  end # SATA
 		# This device does not have any function on CNP-H, but it needs
 		# to be here so that the resource allocator is aware of UART 2.
 		device pci 19.0 hidden end
@@ -189,7 +207,11 @@ chip soc/intel/cannonlake
 			register "PcieRpEnable[13]" = "1"
 		end
 		device pci 1d.6 on	# PCIe root port 15 (BMC)
+			device pci 00.0 on	# Aspeed PCI Bridge
+				device pci 00.0 on end  # Aspeed 2500 VGA
+			end
 			register "PcieRpEnable[14]" = "1"
+			register "PcieRpSlotImplemented[14]" = "1"
 		end
 		device pci 1d.7 on	# PCIe root port 16 (M.2 E/CNVi)
 			# Disabled when CNVi is present
@@ -200,5 +222,16 @@ chip soc/intel/cannonlake
 		device pci 1e.1 on  end # UART #1
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on	# LPC Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+			# AST2500, but not enabled to decode LPC cycles
+		end
+		device pci 1f.1 on     end # P2SB
+		device pci 1f.2 hidden end # Power Management Controller
+		device pci 1f.3 on     end # Intel HDA
+		device pci 1f.4 on     end # SMBus
+		device pci 1f.5 on     end # PCH SPI
 	end
 end
-- 
2.11.4.GIT