| commit | fd46b497ead843eccfd80124ca8fbba7e57a3631 | |
| author | Angel Pons <th3fanbus@gmail.com> | |
| Wed, 8 Sep 2021 12:30:07 +0000 (8 14:30 +0200) | ||
| committer | Matt DeVillier <matt.devillier@gmail.com> | |
| Tue, 16 Apr 2024 01:45:36 +0000 (16 01:45 +0000) | ||
| tree | 597063b76d3b640d5d71e40d060a6cd954342dce | treesnapshot (tar.gz zip) |
| parent | ebba6da073e51569bd962e86bf8162e7b4da9321 | commitdiff |
lynxpoint/broadwell: Correct L1 exit latency with ASPM
Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit
latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does
the same. Correct the condition accordingly. On Lynx Point, also remove
a now-redundant write to the LCAP register (offset 0x4c).
Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit
latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does
the same. Correct the condition accordingly. On Lynx Point, also remove
a now-redundant write to the LCAP register (offset 0x4c).
Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/broadwell/pch/pcie.c | diffblobblamehistory | |
| src/southbridge/intel/lynxpoint/pcie.c | diffblobblamehistory |