| commit | fc752b69183e0c2b37fa50f03d89aeb59c876c4f | |
| author | Furquan Shaikh <furquan@google.com> | |
| Wed, 13 May 2020 19:14:11 +0000 (13 12:14 -0700) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Thu, 14 May 2020 21:25:50 +0000 (14 21:25 +0000) | ||
| tree | 31577a1e166e10947b28e4b9e770bd1e343db1b9 | treesnapshot (tar.gz zip) |
| parent | ffa5e8ddcfb099eff56eb8e6cd70ca4bd0b2545d | commitdiff |
soc/amd/stoneyridge: add resources during read_resources()
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources
during read_resources().
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I532f508936d5ec154cbcb3538949316ae4851105
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources
during read_resources().
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I532f508936d5ec154cbcb3538949316ae4851105
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/amd/stoneyridge/chip.c | diffblobblamehistory | |
| src/soc/amd/stoneyridge/include/soc/northbridge.h | diffblobblamehistory | |
| src/soc/amd/stoneyridge/northbridge.c | diffblobblamehistory |