| commit | fc458cdc5374a293483455acdd42cdbdd032ae27 | |
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | |
| Thu, 27 Sep 2018 14:23:15 +0000 (27 08:23 -0600) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Mon, 1 Oct 2018 14:30:45 +0000 (1 14:30 +0000) | ||
| tree | 41659c036bc61e28137ce574c99eb2bf2c675441 | treesnapshot (tar.gz zip) |
| parent | 87471366e42106b136d6cd0fba008b8c7eb53f85 | commitdiff |
amd/stoneyridge: Create gnvs entries for AOAC devices
A later patch will leverage AMD's ASL support for handling AOAC
devices. This will gather coreboot's device enables from a bitwise field,
where each bit corresponds to the register offset used to control
each devices.
Create an identical structure, and add it to the nvs ASL and global_nvs_t
structure.
BUG=b:77602074
Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
A later patch will leverage AMD's ASL support for handling AOAC
devices. This will gather coreboot's device enables from a bitwise field,
where each bit corresponds to the register offset used to control
each devices.
Create an identical structure, and add it to the nvs ASL and global_nvs_t
structure.
BUG=b:77602074
Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
| src/soc/amd/stoneyridge/acpi/globalnvs.asl | diffblobblamehistory | |
| src/soc/amd/stoneyridge/include/soc/nvs.h | diffblobblamehistory | |
| src/soc/amd/stoneyridge/include/soc/southbridge.h | diffblobblamehistory |