soc/intel/common: Add method to modify GPIO community PM config
commitf98bbda5fb145287c75e944b7c8d91e7c57a672e
authorVenkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Tue, 7 Apr 2020 23:16:38 +0000 (7 16:16 -0700)
committerDuncan Laurie <dlaurie@chromium.org>
Wed, 29 Apr 2020 03:01:22 +0000 (29 03:01 +0000)
tree7fa7ef6cb1248e03fcd2a3ac2d14fbf57b0809e7
parent64f477b401ecc885ba678c77d01757118c84bd55
soc/intel/common: Add method to modify GPIO community PM config

This patch adds CGPM, a helper method to configure GPIO power management
bits that are part of miscellaneous config. This is needed for
configuration of these bits on S0ix entry and exit.

BUG=b:148892882
BRANCH=none
TEST="BUILD volteer and ripto"

Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40260
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
src/soc/intel/common/acpi/gpio.asl [new file with mode: 0644]