| commit | f95b4a708e021f4eb3cb36aa1f3bc6a2076f2f6b | |
| author | Duncan Laurie <dlaurie@google.com> | |
| Mon, 29 Oct 2018 23:48:02 +0000 (29 16:48 -0700) | ||
| committer | Duncan Laurie <dlaurie@chromium.org> | |
| Fri, 2 Nov 2018 16:06:53 +0000 (2 16:06 +0000) | ||
| tree | b3b57e453814c58c71fea1dfeb8130158cfad7d5 | treesnapshot (tar.gz zip) |
| parent | 51f2f2eba1778167e9d281b8c7a7c9b9792a37cb | commitdiff |
soc/intel: Enable GPIO functions in verstage
Enable GPIO functionality in verstage so platforms can read a
PCH GPIO in verstage to determine recovery mode.
Change-Id: Icd4344c4d66dbe21fda9dc27e61a836c1dd9be07
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29407
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable GPIO functionality in verstage so platforms can read a
PCH GPIO in verstage to determine recovery mode.
Change-Id: Icd4344c4d66dbe21fda9dc27e61a836c1dd9be07
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29407
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/cannonlake/Makefile.inc | diffblobblamehistory | |
| src/soc/intel/common/block/gpio/Makefile.inc | diffblobblamehistory | |
| src/soc/intel/common/block/pcr/Makefile.inc | diffblobblamehistory |