| commit | f87427f1a4303d6cab26f29641831b4d3dec8451 | |
| author | Raul E Rangel <rrangel@chromium.org> | |
| Tue, 9 Feb 2021 17:54:57 +0000 (9 10:54 -0700) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Wed, 10 Feb 2021 19:00:17 +0000 (10 19:00 +0000) | ||
| tree | c1878b2ea1ba29a4c87065c9172b97656ee186b3 | treesnapshot (tar.gz zip) |
| parent | 78452a584a7f2c201a6e9917c034b42f6fed89c6 | commitdiff |
soc/amd/stoneyridge: Add SPI registers
This is a copy/paste of amdblocks/lpc.h. The registers are different for
picasso and cezanne, so I'm moving them to soc.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is a copy/paste of amdblocks/lpc.h. The registers are different for
picasso and cezanne, so I'm moving them to soc.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
| src/soc/amd/stoneyridge/include/soc/lpc.h | [new file with mode: 0644] | blob |