soc/intel/skylake: Limit xDCI feature when VBOOT is enabled
commitf5116952bb77ac361ad541dea00d9df28067219e
authorDuncan Laurie <dlaurie@chromium.org>
Mon, 26 Mar 2018 09:24:18 +0000 (26 02:24 -0700)
committerDuncan Laurie <dlaurie@chromium.org>
Wed, 28 Mar 2018 22:52:38 +0000 (28 22:52 +0000)
tree16ef5146141c8cd340d6f67605234870f36c89d6
parent8b76605a4af9b45894c39cd7b9c480bd96f523cd
soc/intel/skylake: Limit xDCI feature when VBOOT is enabled

Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it.  Otherwise, disable the
PCI device if it has been enabled in devicetree.

To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.

This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.

Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
15 files changed:
src/mainboard/google/chell/devicetree.cb
src/mainboard/google/eve/devicetree.cb
src/mainboard/google/fizz/devicetree.cb
src/mainboard/google/glados/devicetree.cb
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
src/mainboard/google/poppy/variants/nami/devicetree.cb
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
src/mainboard/google/poppy/variants/soraka/devicetree.cb
src/mainboard/intel/saddlebrook/devicetree.cb
src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
src/soc/intel/skylake/Kconfig
src/soc/intel/skylake/chip.c
src/soc/intel/skylake/chip.h
src/soc/intel/skylake/chip_fsp20.c