| commit | f4fa1e1d06b5c68b746274c39f23cc8b05801d90 | |
| author | Angel Pons <th3fanbus@gmail.com> | |
| Mon, 3 Aug 2020 12:12:13 +0000 (3 14:12 +0200) | ||
| committer | Angel Pons <th3fanbus@gmail.com> | |
| Tue, 4 Aug 2020 21:28:05 +0000 (4 21:28 +0000) | ||
| tree | 71791abd70eaa3d21b38c284ded82eee8bdf4743 | treesnapshot (tar.gz zip) |
| parent | 90de10c17a2d72065592875b4af206e9cb1a7feb | commitdiff |
nb/intel/haswell: Deduplicate PCIEXBAR decoding
Add `decode_pcie_bar` for consistency with other Intel northbridges.
Change-Id: If04ca3467bb067b28605a3acccb8bda325735999
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add `decode_pcie_bar` for consistency with other Intel northbridges.
Change-Id: If04ca3467bb067b28605a3acccb8bda325735999
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| src/northbridge/intel/haswell/acpi.c | diffblobblamehistory | |
| src/northbridge/intel/haswell/haswell.h | diffblobblamehistory | |
| src/northbridge/intel/haswell/northbridge.c | diffblobblamehistory |