| commit | f4e64669244054a079d1d5e647ddc86ef4f08d71 | |
| author | Felix Held <felix-coreboot@felixheld.de> | |
| Tue, 3 Aug 2021 01:05:39 +0000 (3 03:05 +0200) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Thu, 9 Sep 2021 17:49:48 +0000 (9 17:49 +0000) | ||
| tree | 8991191f4a17bf083bddde52cb81a75f8e80fd12 | treesnapshot (tar.gz zip) |
| parent | 711023590278eb1cfdb050b5e68d14827c63527a | commitdiff |
soc/amd/cezanne/include/gpio: add remote GPIO pin mux definitions
Add the pin definitions for the remote GPIOs and the GPIO pin mux values
for the GPIO mode of those pins. For now, accessing the remote GPIOs is
only supported from the native coreboot code running on the x86 cores
and not from verstage on PSP or ACPI.
BUG=b:194524995
TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and
then toggling that GPIO in an infinite loop in the mainboard's bootblock
code results in GPIO 262 toggling as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add the pin definitions for the remote GPIOs and the GPIO pin mux values
for the GPIO mode of those pins. For now, accessing the remote GPIOs is
only supported from the native coreboot code running on the x86 cores
and not from verstage on PSP or ACPI.
BUG=b:194524995
TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and
then toggling that GPIO in an infinite loop in the mainboard's bootblock
code results in GPIO 262 toggling as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| src/soc/amd/cezanne/include/soc/gpio.h | diffblobblamehistory |