Sklrvp: Select PCIEXP_L1_SUB_STATE config symbol
commitf077de66ffdbbd191f09ae8a4d6f08d0313be90f
authorNaveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Mon, 6 Jul 2015 11:12:56 +0000 (6 16:42 +0530)
committerPatrick Georgi <pgeorgi@google.com>
Tue, 21 Jul 2015 18:06:08 +0000 (21 20:06 +0200)
tree4430104180f6586f9518a43d5f8f05306c1b6a6a
parent02b3243dd39291425c325a1e2df6618c5a45d934
Sklrvp: Select PCIEXP_L1_SUB_STATE config symbol

This patch selects the config symbol PCIEXP_L1_SUB_STATE to enable L1
substate for PCIe.

BRANCH=None
BUG=chrome-os-partner:42331
TEST=Build for sklrvp; boot and check "dmesg | grep iwl" shows
"L1 enabled and LTR enabled"

Change-Id: I97552c7700649a9f5d8646a03027c5c5e0b477b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d3115816fbdd11c7f8ff418e0b5c86b8650c8b83
Original-Change-Id: Iaf307cb2d623cc1ce97b01d15a6b42569fd0c0c4
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284775
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
src/mainboard/intel/sklrvp/Kconfig