ipq8064: add DRAM initialization code
commitef77f873721afc52d988c0291e26ed90dbc8ea55
authorVadim Bendebury <vbendeb@chromium.org>
Thu, 11 Dec 2014 04:42:58 +0000 (10 20:42 -0800)
committerPatrick Georgi <pgeorgi@google.com>
Wed, 15 Apr 2015 19:56:15 +0000 (15 21:56 +0200)
tree30c8f4397e3ef6754d5240a38088033eb8655096
parent6fe4e5e34c584f7f4ad2c071b311e6b6a878b623
ipq8064: add DRAM initialization code

Read two blobs from CBFS: cdt.mbn (memory configuration descriptor)
and ddr.mbn (actual memory initialization code).

Pointer to CDT which starts right above the MBN header is passed to
the memory initialization routine. Zero return value means memory
initialization succeeded.

BRANCH=storm
BUG=chrome-os-partner:34161
TEST=with upcoming patches memory initialization succeeds.

Change-Id: Ia0903dc4446c03f7f0dc3f4cc3a34e90a8064afc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1d79dadd7d47dd6d01e031bc77810c9e85dd854b
Original-Change-Id: Ib5a7e4fe0eb24a7bd090ec3553c57cd1b7e41512
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234644
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9686
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
src/mainboard/google/storm/romstage.c
src/soc/qualcomm/ipq806x/Makefile.inc
src/soc/qualcomm/ipq806x/blobs_init.c [new file with mode: 0644]
src/soc/qualcomm/ipq806x/include/soc/soc_services.h [copied from src/mainboard/google/storm/romstage.c with 78% similarity]
src/soc/qualcomm/ipq806x/mbn_header.h [copied from src/mainboard/google/storm/romstage.c with 69% similarity]