| commit | eee4f6b224b897184327539fcbeb23f9b26f02d9 | |
| author | Arthur Heymans <arthur@aheymans.xyz> | |
| Mon, 2 Jan 2017 23:49:45 +0000 (3 00:49 +0100) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Sun, 22 Jan 2017 19:23:17 +0000 (22 20:23 +0100) | ||
| tree | 4b16cd646deb66fdcfdde8954798b1698666e155 | treesnapshot (tar.gz zip) |
| parent | acbb70b810c6eb17e403c37fa2888b479e5b23a9 | commitdiff |
nb/x4x/raminit: Fix programming dram timings
The results were obtained by comparing the MCHBAR registers of vendor bios
with coreboot at the same dram timings.
This fixes 2 issues:
* 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with
800MHz raminit failed;
* 1067MHz fsb CPUs did not boot when second dimm slot was populated.
TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with
DDR2 667 and 800MHz dimms.
Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18022
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
The results were obtained by comparing the MCHBAR registers of vendor bios
with coreboot at the same dram timings.
This fixes 2 issues:
* 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with
800MHz raminit failed;
* 1067MHz fsb CPUs did not boot when second dimm slot was populated.
TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with
DDR2 667 and 800MHz dimms.
Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18022
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
| src/northbridge/intel/x4x/raminit.c | diffblobblamehistory | |
| src/northbridge/intel/x4x/raminit_ddr2.c | diffblobblamehistory |