| commit | ed3e6b8b946e0c5fbc417551750da67c284eaf8b | |
| author | Lijian Zhao <lijian.zhao@intel.com> | |
| Tue, 26 Sep 2017 20:56:24 +0000 (26 13:56 -0700) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Tue, 3 Oct 2017 20:24:42 +0000 (3 20:24 +0000) | ||
| tree | d91520a8122ca71345e53427817e9c78accdc768 | treesnapshot (tar.gz zip) |
| parent | 5d11cc9d7e0ee016d6b6c540d010b212291d61cd | commitdiff |
soc/intel/cannonlake: Disable CPU ratio override
Disable CPU Ratio override as input to FSP Memory init.
Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Disable CPU Ratio override as input to FSP Memory init.
Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/soc/intel/cannonlake/romstage/romstage.c | diffblobblamehistory |