| commit | ec7293652af797b2595bec396bae8cd625afbf8e | |
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | |
| Fri, 9 Sep 2016 21:08:50 +0000 (9 14:08 -0700) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Tue, 1 Nov 2016 16:31:59 +0000 (1 17:31 +0100) | ||
| tree | 0dd1005f1eb4212438817bc24aabe6b08f03209e | treesnapshot (tar.gz zip) |
| parent | 25445dca1700bea7c83e6d12c7936253ef9af8ca | commitdiff |
soc/apollolake: Add soc core init
Add soc core init to set up the following feature MSRs:
1. C-states
2. IO/Mwait redirection
BUG=chrome-os-partner:56922
BRANCH=None
TEST= Check C-state functioning using 'powertop'. Check 0xE2 and
0xE4 MSR to verify IO/Mwait redirection.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I99b66b02eb790b6b348be7c964d21ec9a6926926
Reviewed-on: https://review.coreboot.org/17168
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add soc core init to set up the following feature MSRs:
1. C-states
2. IO/Mwait redirection
BUG=chrome-os-partner:56922
BRANCH=None
TEST= Check C-state functioning using 'powertop'. Check 0xE2 and
0xE4 MSR to verify IO/Mwait redirection.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I99b66b02eb790b6b348be7c964d21ec9a6926926
Reviewed-on: https://review.coreboot.org/17168
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
| src/soc/intel/apollolake/cpu.c | diffblobblamehistory | |
| src/soc/intel/apollolake/include/soc/cpu.h | diffblobblamehistory | |
| src/soc/intel/apollolake/include/soc/iomap.h | diffblobblamehistory |