| commit | eb86016570d0f7dde331d6df531f386bff590fb1 | |
| author | Angel Pons <th3fanbus@gmail.com> | |
| Sat, 20 Jun 2020 16:03:27 +0000 (20 18:03 +0200) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Mon, 22 Jun 2020 11:43:16 +0000 (22 11:43 +0000) | ||
| tree | 7aad9fe7137b91ed12c29953a06c0dd8c874198d | treesnapshot (tar.gz zip) |
| parent | 645d2a817ab98c75230b1253749746467eacf220 | commitdiff |
nb/intel/haswell: Use 16-bit ops on PCI COMMAND
The PCI COMMAND register is 16 bits wide. So, do not use 32-bit PCI ops
to update it.
Change-Id: I8f8d9e978f3b241cb544dd1d26e0f5fa8997d11e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The PCI COMMAND register is 16 bits wide. So, do not use 32-bit PCI ops
to update it.
Change-Id: I8f8d9e978f3b241cb544dd1d26e0f5fa8997d11e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
| src/northbridge/intel/haswell/minihd.c | diffblobblamehistory |