| commit | eb102ccbd6a41d55478a8b9a95ef1f093ecaf82a | |
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | |
| Mon, 6 Dec 2021 02:20:42 +0000 (6 10:20 +0800) | ||
| committer | Hung-Te Lin <hungte@chromium.org> | |
| Wed, 8 Dec 2021 11:32:14 +0000 (8 11:32 +0000) | ||
| tree | b30de10ab73f6f5752429863695f2d8faca02409 | treesnapshot (tar.gz zip) |
| parent | d22e921178bcbdf1c72a19f95a1067f9074aaf58 | commitdiff |
soc/mediatek/mt8186: Correct SPI_HZ for PLL
The SPI speed is 218.4MHz, so correct the value of SPI_HZ.
BUG=b:202871018
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I6e8ba10a851e1507405cdd41939a176462734487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The SPI speed is 218.4MHz, so correct the value of SPI_HZ.
BUG=b:202871018
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I6e8ba10a851e1507405cdd41939a176462734487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| src/soc/mediatek/mt8186/include/soc/pll.h | diffblobblamehistory |