| commit | e9984c8e4fec24c2fe6320b2b6726f13ed7d7296 | |
| author | Aamir Bohra <aamir.bohra@intel.com> | |
| Wed, 9 Sep 2020 08:58:45 +0000 (9 14:28 +0530) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Mon, 12 Oct 2020 08:50:10 +0000 (12 08:50 +0000) | ||
| tree | ab7f02ad248f57c30f4a4c6275b155c91988f8bb | treesnapshot (tar.gz zip) |
| parent | 7979bf5d0dc7fa0abc1ba8dec1557435012faa06 | commitdiff |
soc/intel/jasperlake: Correct SaGv mapping
Jasper Lake support 3 Memory train frequencies low. mid and high.
Update the SaGv configuration accordingly.
Change-Id: I366de1ea7cf41c56b2954b8032c69bfba81058e2
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Jasper Lake support 3 Memory train frequencies low. mid and high.
Update the SaGv configuration accordingly.
Change-Id: I366de1ea7cf41c56b2954b8032c69bfba81058e2
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
| src/soc/intel/jasperlake/chip.h | diffblobblamehistory |