| commit | e9523926152490d3f1c70ff8773b87ee54084e55 | |
| author | Matt DeVillier <matt.devillier@puri.sm> | |
| Wed, 4 Nov 2020 21:04:06 +0000 (4 15:04 -0600) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Mon, 9 Nov 2020 07:47:36 +0000 (9 07:47 +0000) | ||
| tree | bf35436979110208965bf36d5ad8b9369bd60ba5 | treesnapshot (tar.gz zip) |
| parent | 4d4256e499e850a724d228d2e676c0f32af67093 | commitdiff |
mb/purism/librem_mini: Fix PCIe clock source mapping in devicetree
Correct PCIe clock source mapping in devicetree now that the GPIO
config has been fixed. Move ClkSrcUsage/ClkSrcClkReq registers
under their associated PCIe root ports.
Change-Id: Ibdaba51d971a39a6da6df82652b7420d7324dee5
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Correct PCIe clock source mapping in devicetree now that the GPIO
config has been fixed. Move ClkSrcUsage/ClkSrcClkReq registers
under their associated PCIe root ports.
Change-Id: Ibdaba51d971a39a6da6df82652b7420d7324dee5
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
| src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb | diffblobblamehistory |