| commit | e7a1e7d3c49e980774985f3f6fae697dcb129420 | |
| author | Lijian Zhao <lijian.zhao@intel.com> | |
| Tue, 10 Oct 2017 01:39:30 +0000 (9 18:39 -0700) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Thu, 19 Oct 2017 19:48:43 +0000 (19 19:48 +0000) | ||
| tree | 2d801591554cc48950c343f94467cef6f8ebcef1 | treesnapshot (tar.gz zip) |
| parent | ed1694157c4f14d4ce60e7c053ea044aca6777fb | commitdiff |
soc/intel/cannonlake: Fix HECI error on reset
Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI. Also add fail safe option to reset in case
of HECI command not successful.
TEST= Force global reset from FSP and read back HECI bar in debug print.
Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI. Also add fail safe option to reset in case
of HECI command not successful.
TEST= Force global reset from FSP and read back HECI bar in debug print.
Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>