| commit | e5592d3d99af72be58d8392d7957be8cd9632e7c | |
| author | Felix Held <felix-coreboot@felixheld.de> | |
| Fri, 4 Feb 2022 12:59:29 +0000 (4 13:59 +0100) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Sat, 5 Feb 2022 18:58:48 +0000 (5 18:58 +0000) | ||
| tree | 21a1be8320e4ca9b4c2f7eddac0953f288064672 | treesnapshot (tar.gz zip) |
| parent | 9ec7227c9b43df97e3422877b2539db21d47741b | commitdiff |
soc/amd/common/block/acpimmio/print_reset_status: extend bit name table
Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge
and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on
Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is
only defined for Sabrina. Since the default value of undefined bits is 0
it isn't a problem to have descriptions for reserved reset status bits
on some SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge
and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on
Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is
only defined for Sabrina. Since the default value of undefined bits is 0
it isn't a problem to have descriptions for reserved reset status bits
on some SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| src/soc/amd/common/block/acpimmio/print_reset_status.c | diffblobblamehistory |