| commit | e40b9481e616f8b8a899ac9bb9fbf1cda20d7114 | |
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | |
| Tue, 16 Jun 2020 19:08:20 +0000 (17 00:38 +0530) | ||
| committer | Edward O'Callaghan <quasisec@chromium.org> | |
| Thu, 25 Jun 2020 13:43:01 +0000 (25 13:43 +0000) | ||
| tree | 2affa524a52a7c4b3edf8cf9c0469f4e3139720f | treesnapshot (tar.gz zip) |
| parent | d95dba0ce34df0a0b61e70fa89470ab113e2e918 | commitdiff |
soc/intel/cannonlake: Add PchPmPwrCycDur to chip options
Add PchPmPwrCycDur to chip options to control the UPD FSPS PchPmPwrCycDur
from devicetree. The UPD determines the minimum time a platform will stay
in reset during host partition reset with power cycle or global reset.
This patch also ensures configured PchPmPwrCycDur value doesn't violate
the PCH EDS specification.
TEST=Verified on Hatch and Puff boards
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I55e836c78fab34e34d57b04428a1498b7dc7174b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Add PchPmPwrCycDur to chip options to control the UPD FSPS PchPmPwrCycDur
from devicetree. The UPD determines the minimum time a platform will stay
in reset during host partition reset with power cycle or global reset.
This patch also ensures configured PchPmPwrCycDur value doesn't violate
the PCH EDS specification.
TEST=Verified on Hatch and Puff boards
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I55e836c78fab34e34d57b04428a1498b7dc7174b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
| src/soc/intel/cannonlake/chip.h | diffblobblamehistory | |
| src/soc/intel/cannonlake/fsp_params.c | diffblobblamehistory |